CS8803: Advanced Digital Design for Embedded...

CS8803: Advanced Digital Design for Embedded Hardware

Lecture 2: Boolean Algebra, Gate Network, and

Combinational Blocks

Instructor: Sung Kyu Lim ([email protected])

Website: http://users.ece.gatech.edu/limsk/course/cs8803

Design Specification

Design Partition

Design Entry: VerilogBehavioral Modeling

Simulation/FunctionalVerification

Design Integrationand Verification

Pre-synthesisSign-Off

Synthesize and MapGate-level Netlist

Post-synthesisDesign Validation

Post-synthesisTiming Verification

Test Generation andFault Simulation

Cell Placement, ScanChain and Clock TreeInsertion, Cell Routing

Verify Physical andElectrical Design Rules

Extract Parasitics

Design Sign-Off

Production-readyMasks

1

2

3

4

5

6

7

8

9

10

11

12

13

14

Design flow for HDL-based ASICs

Copyright 2000, 2003 MD Ciletti 6

COMBINATIONAL LOGIC

Combinational logic forms Boolean functions of the input variables. The outputs at any time, t, are a function of only the inputs at time t. The variables are assumed to be binary.

CombinationalLogic

y1

y2

y3

abcd

y1 = f1(a, b, c, d)

y2 = f2(a, b, c, d)

y3 = f3(a, b, c, d)

y4 = f4(a, b, c, d)

A binary variable may have a value of 0 or 1. Later, the logic value system will be

expanded to have more values to support a hardware description language.

POSITIVE LOGIC: Low voltage corresponds to logic 0 and a high voltage corresponds to a logic 1.


LOGIC GATES

ENB

And Gatey = a . b

Or Gatey = a + b

Nand Gate

y = a . b

ab

ab

y

y

yab

ab

Nor Gate

y = a + b

y ab

y

yab

Xor Gatey = a ^ b

Xnor Gate

y = a ^ b

a y

Buffery = a

a a

Invertery = a

Three-State Buffery = a if ENB = 1, else y = z

y y

R.M. Dansereau; v.1.0

INTRO. TO COMP. ENG.CHAPTER IV-3

GATE NETWORKSVALID/INVALID NETWORKS

GATE DESIGN

•GATE NETWORKS-INTRODUCTION

G1 G3

G2

Valid or Invalid?

G1 G3

G2

Valid or Invalid?

G1 G3

G2

Valid or Invalid?

G1

G3

G2

Valid or Invalid?

G6



LOGIC NETWORKSFROM BOOLEAN FUNCTIONS

GATE DESIGN

•LOGIC GATES-NON-INVERTING OPER.-INVERTING OPERATORS-INVERTERS

• Implement the following Boolean function using logic gates

• Possible solution:

• transistors for CMOS technology.

F A BC+( )D( ) C DE+ +=

A

B

C

D

FE

3 6AND× 3 6OR× 3 2NOT×+ + 42=



LOGIC NETWORKSUSING SPECIFIC GATES

GATE DESIGN

•LOGIC GATES•LOGIC NETWORKS

-FROM BOOL. FUNCTIONS

• Because of various implementation reasons, it may be desired to use only

specific sorts of logic gates in an implementation.

• For instance, many CMOS implementations use only NAND gates.

Some implementations use on NOR gates.

• This can be done in a number of manners. One is to rework the Boolean

functions so that only the specific gates desired are used.

• May reduce the physical number of transistors required if the appropriate

types of gates are used.



LOGIC NETWORKSEXAMPLE USING NAND GATES

GATE DESIGN

•LOGIC GATES•LOGIC NETWORKS

-FROM BOOL. FUNCTIONS-USING SPECIFIC GATES

• Implement the following Boolean function using NAND gates

• This Boolean function can be expressed as

F A BC+( )D( ) C DE+ +=

F ABCDCDE A ′ BC ′( )′( )′D( ) C ′( ) DE( )′( )′ ′= =

A

B

C

DE

F

6 4NAND-2× 8NAND-4+ 32=

3 4NAND-2× 8NAND-4 3 2NOT×+ + 26=

transistors

transistors

How to implement4-input NAND?



MIXED LOGICINTRODUCTION

GATE DESIGN

•LOGIC NETWORKS-FROM BOOL. FUNCTIONS-USING SPECIFIC GATES-EXAMPLE USING NAND

• Mixed logic is one approach that makes it easier to redesign a logic

network to use desired types of gates.

• Mixed logic is also self-documenting

• This means that you can see what the original designer started with and

see how the logic network was changed for the implementation.

• The idea behind mixed logic is to diagram out the logic network from the

Boolean equations given, and then make small changes to the logic

network to achieve desired results for implementation.



MIXED LOGICDEMORGAN’S SQUARE

GATE DESIGN

•LOGIC NETWORKS•MIXED LOGIC

-INTRODUCTION

• DeMorgan’s Square

A B0011

0101

1110

NAND

F A B0011

0101

1000

F

NOR

A B0011

0101

0001

AND

F A B0011

0101

0111

F

OR



MIXED LOGICMIXED LOGIC PROCEDURE

GATE DESIGN

•LOGIC NETWORKS•MIXED LOGIC

-INTRODUCTION-DEMORGAN’S SQUARE

• The procedure for performing mixed logic conversions is as follows:

• Draw the logic network for the given Boolean equation.

• Use only AND and OR gates.

• Replace all complements with a bar (no bubbles or inverters yet!)

• Once the initial Boolean equation is drawn with AND gates, OR gates

and bars, the self-documenting redesign begins:

• Add complement bubbles and NOT gates within the network to

appropriately convert logic gates to desired gate sets.

• The rules in adding complement bubbles and NOT gates

• All bubbles must cancel each other out

• Exactly one and only one bubble needed on each bar



MIXED LOGICEXAMPLE #1 (1)

GATE DESIGN

•MIXED LOGIC-INTRODUCTION-DEMORGAN’S SQUARE-MIXED LOGIC PROC.

• Implement the following Boolean function using NAND gates and then also

using NOR gates.

• Solution: Start by drawing the logic network for the Boolean function with

the complements as bars.

• This completes the information needed to get back original equation.

F AB CD+=

AB

CD

F




GATE DESIGN

•MIXED LOGIC-DEMORGAN’S SQUARE-PROCEDURE-EXAMPLE #1

continued... using NAND gates

• This logic network now only uses NAND gates and inverters.

• This results in the following Boolean function, as obtained previously

AB

CD

F

F A B C D E, , , ,( ) ABCD=




GATE DESIGN


continued... using NOR gates

• This logic network now only uses NOR gates and inverters.


AB

CD

F

F A B C D E, , , ,( ) A B+ C D++=




GATE DESIGN


• Implement the following Boolean function using NAND gates

• Solution: Start by drawing the logic network for the Boolean function with

the complements as bars.

F A BC+( )D( ) C DE+ +=

A

B

C

D

FE




GATE DESIGN

•MIXED LOGIC-PROCEDURE-EXAMPLE #1-EXAMPLE #2

continued...

• This logic network now only uses NAND gates and inverters.


A

B

C

D

FE

F A B C D E, , , ,( ) ABCDCDE ABCDCDE= =


BOOLEAN ALGEBRA (p 16)

A binary Boolean algebra consists of a set B = {0, 1} and the operators + and ., having commutative and distributive properties such that for two Boolean variables A and B having values in B, a + b = b + a, and a . b = b . a. The operators + and . have identity elements 0 and 1, respectively, such that for any Boolean variable a, a + 0 = a, and a . 1 = a. Each Boolean variable a has a complement, denoted by a', such that a + a' = 1, and a . a' = 0. Terminology:

• + is called the sum operator, the "OR" operator, or the disjunction operator.

• . is called the product operator, the "AND" operator, or the conjunction operator. • The multi-dimensional space spanned by a set of n binary-valued Boolean variables is

denoted by Bn.

• A point in Bn is called a vertex of and is represented by an n-dimensional vector of binary valued elements, e.g. (100).

• A binary variable can be associated with the dimensions of a binary Boolean space,

and a point is identified with the values of the variables.


BOOLEAN FUNCTIONS

A completely specified m-dimensional Boolean function is a mapping from Bn into Bm, denoted by f: Bn → Bm. An incompletely specified function is defined over a subset of Bn, and is considered to have a value of "don't-care" at points outside of the subset of definition: f: Bn → {0, 1, *}, where * denotes don't-care.

"On" Set: {x: x ∈ Bn and f(x) = 1 } "Off" Set: {x: x ∈ Bn and f(x) = 0 } "dc" Set: {x: x ∈ Bn and f(x) = * }

The don't-care set accommodates input patterns that never care, or outputs that will not be observed.


INTRO. TO COMP. ENG.CHAPTER III-7

BOOLEAN ALGEBRABASIC IDENTITIES

BOOLEAN ALGEBRA

•BOOLEAN OPERATIONS•BOOLEAN ALGEBRA

-PRECEDENCE OF OPER.-FUNCTION EVALUATION

X 0+ X=

X 1+ 1=

X X ′+ 1=

X ′( )′ X=

X Y+ Y X+=

X 1⋅ X=

X 0⋅ 0=

X X′⋅ 0=

XY YX=

X YZ( ) XY( )Z=X Y Z+( )+ X Y+( ) Z+=

X Y Z+( ) XY XZ+= X YZ+ X Y+( ) X Z+( )=

Commutativity

Identity

Involution Law

Associativity

Distributivity

Complement

Idempotent LawX X⋅ X=X X+ X=

Absorption LawX X Y+( ) X=X XY+ X=

SimplificationX X ′ Y+( ) XY=X X ′Y+ X Y+=

DeMorgan’s LawXY( )′ X ′ Y ′+=X Y+( )′ X ′Y ′=

Consensus TheoremX Y+( ) X ′ Z+( ) Y Z+( )XY X ′Z YZ+ + XY X ′Z+= X Y+( ) X ′ Z+( )=



BOOLEAN ALGEBRADUALITY PRINCIPLE

BOOLEAN ALGEBRA

•BOOLEAN ALGEBRA-PRECEDENCE OF OPER.-FUNCTION EVALUATION-BASIC IDENTITIES

• Duality principle:

• States that a Boolean equation remains valid if we take the dual of the

expressions on both sides of the equals sign.

• The dual can be found by interchanging the AND and OR operators

along with also interchanging the 0’s and 1’s.

• This is evident with the duals in the basic identities.

• For instance: DeMorgan’s Law can be expressed in two forms

X Y+( )′ X ′Y ′= XY( )′ X ′ Y ′+=as well as


REPRESENTATION OF COMBINATIONAL LOGIC

Common representations of combinational logic:

• Truth Table • Boolean Equations

• Binary Decision Diagrams • Circuit Schematic

EXAMPLE: HALF-ADDER TRUTH TABLE

ba sum

c_out

a

b

sum

c_outAdd_half

a b c_out sum

0 0 0 00 1 0 11 0 0 11 1 1 0

Inputs Outputs


REPRESENTATION OF COMBINATIONAL LOGIC (Cont.)

EXAMPLE: HALF-ADDER BOOLEAN EQUATIONS

sum = a'b + ab' = a ⊕ b

c_out = a . b

ba sum

c_out

a

b

sum

c_outAdd_half



STANDARD FORMSSUM OF MINTERMS

BOOLEAN ALGEBRA

•BOOLEAN ALGEBRA•STANDARD FORMS

-SOP AND POS-MINTERMS

• Sum-of-minterms standard form expresses the Boolean or switching

expression in the form of a sum of products using minterms.

• For instance, the following Boolean expression using minterms

could instead be expressed as

or more compactly

F A B C, ,( ) ABC ABC ABC ABC+ + +=

F A B C, ,( ) m0 m1 m4 m5+ + +=

F A B C, ,( ) m 0 1 4 5, , ,( )∑ one-set 0 1 4 5, , ,( )= =



STANDARD FORMSPRODUCT OF MAXTERMS

BOOLEAN ALGEBRA

•STANDARD FORMS-MINTERMS-SUM OF MINTERMS-MAXTERMS

• Product-of-maxterms standard form expresses the Boolean or switching

expression in the form of product of sums using maxterms.

• For instance, the following Boolean expression using maxterms

could instead be expressed as

or more compactly as

F A B C, ,( ) A B C+ +( ) A B C+ +( ) A B C+ +( )=

F A B C, ,( ) M1 M4 M7⋅ ⋅=

F A B C, ,( ) M 1 4 7, ,( )∏ zero-set 1 4 7, ,( )= =



STANDARD FORMSMINTERM AND MAXTERM EXP.

BOOLEAN ALGEBRA

•STANDARD FORMS-SUM OF MINTERMS-MAXTERMS-PRODUCT OF MAXTERMS

• Given an arbitrary Boolean function, such as

how do we form the canonical form for:

• sum-of-minterms

• Expand the Boolean function into a sum of products. Then take

each term with a missing variable and AND it with .

• product-of-maxterms

• Expand the Boolean function into a product of sums. Then take

each factor with a missing variable and OR it with .

F A B C, ,( ) AB B A C+( )+=

X X X+

X XX



STANDARD FORMSFORMING SUM OF MINTERMS

BOOLEAN ALGEBRA

•STANDARD FORMS-MAXTERMS-PRODUCT OF MAXTERMS-MINTERM & MAXTERM

• ExampleF A B C, ,( ) AB B A C+( )+ AB AB BC+ += =

AB C C+( ) AB C C+( ) A A+( )BC+ +=

ABC ABC ABC ABC ABC+ + + +=

m 0 1 4 6 7, , , ,( )∑=

A B C F11001011

00001111

00110011

01010101

01

4

67

Minterms listed as1s in Truth Table



STANDARD FORMSFORMING PROD OF MAXTERMS

BOOLEAN ALGEBRA

•STANDARD FORMS-PRODUCT OF MAXTERMS-MINTERM & MAXTERM-FORM SUM OF MINTERMS

• ExampleF A B C, ,( ) AB B A C+( )+ AB AB BC+ += =

A B+( ) A B C+ +( ) A B C+ +( )=

M 2 3 5, ,( )∏=

A B CC+ +( ) A B C+ +( ) A B C+ +( )=

A B C+ +( ) A B C+ +( ) A B C+ +( )=

(using distributivity)

A B C F11001011

00001111

00110011

01010101

23

5

Maxterms listed as0s in Truth Table



STANDARD FORMSCONVERTING MIN AND MAX

BOOLEAN ALGEBRA

•STANDARD FORMS-MINTERM & MAXTERM-SUM OF MINTERMS-PRODUCT OF MAXTERMS

• Converting between sum-of-minterms and product-of-maxterms

• The two are complementary, as seen by the truth tables.

• To convert interchange the and , then use missing terms.

• Example: The example from the previous slides

is re-expressed as

where the numbers 2, 3, and 5 were missing from the minterm

representation.

∑ ∏

F A B C, ,( ) m 0 1 4 6 7, , , ,( )∑=

F A B C, ,( ) M 2 3 5, ,( )∏=


SIMPLIFICATION OF BOOLEAN EXPRESSIONS (Cont.)

A Boolean expression in SOP form is said to be minimal if it contains a minimal number of product terms and literals (i.e. a given term cannot be replaced by another that has fewer literals). A minimum SOP form corresponds to a two-level logic circuit having the fewest gates and the fewest number of gate inputs. A Boolean expression in POS form is said to be minimal of it contains a minimal number of factors and literals (i.e. a given factor cannot be replace by another having fewer literals). Three approaches: (1) Karnaugh maps and extended karnaugh maps (Feasible for up to 6 variables) (2) Quine-McCluskey minimization (computer-based) (3) Boolean minimization (manual) uses the theorems describing relationships between Boolean variables to find simpler equivalent expressions (It is not straightforward, is not easy, and requires experience. Now embedded in synthesis tools such as mis II.)



SIMPLIFICATIONKARNAUGH MAPS

BOOLEAN ALGEBRA

•STANDARD FORMS-SUM OF MINTERMS-PRODUCT OF MAXTERMS-CONVERTING MIN & MAX

• Often it is desired to simplify a Boolean function. A quick graphical

approach is to use Karnaugh maps.

0 1 1 0

0 1 1 1

0

1

00 01 11 10ABC

0 0

0 1

0

1

0 1AB

0 1 0 0

0 1 0 0

1 1 1 1

0 1 0 0

00

01

11

10

00 01 11 10ABCD

2-variableKarnaugh map



F AB= F AB C+= F AB CD+=



SIMPLIFICATIONKARNAUGH MAP ORDERING

BOOLEAN ALGEBRA

•STANDARD FORMS•SIMPLIFICATION

-KARNAUGH MAPS

• Notice that the ordering of cells in the map are such that moving from one

cell to an adjacent cell only changes one variable.

• This ordering allows for grouping of minterms/maxterms for simplification.

0 1 3 2

4 5 7 6

0

1

00 01 11 10ABC

0 1

2 3

0

1

0 1AB

0 1 3 2

4 5 7 6

12 13 15 14

8 9 11 10

00

01

11

10

00 01 11 10ABCD




B

A

A

B

A

A

BB

CC C

DD D

CC

A

A

B

B

B



SIMPLIFICATIONIMPLICANTS

BOOLEAN ALGEBRA

•STANDARD FORMS•SIMPLIFICATION

-KARNAUGH MAPS-KARNAUGH MAP ORDER

• Implicant

• Bubble covering only 1s (size of bubble

must be a power of 2).

• Prime implicant

• Bubble that is expanded as big as possible

(but increases in size by powers of 2).

• Essential prime implicant

• Bubble that contains a 1 covered only by

itself and no other prime implicant bubble.

• Non-essential prime implicant

• A 1 that can be bubbled by more then one

prime implicant bubble.

1 1 0 0

0 0 1 0

0 1 1 1

1 1 0 0

00

01

11

10

00 01 11 10AB

CD



SIMPLIFICATIONPROCEDURE FOR SOP

BOOLEAN ALGEBRA

•SIMPLIFICATION-KARNAUGH MAPS-KARNAUGH MAP ORDER-IMPLICANTS

• Procedure for finding the SOP from a Karnaugh map

• Step 1: Form the 2-, 3-, or 4-variable Karnaugh map as appropriate for

the Boolean function.

• Step 2: Identify all essential prime implicants for 1s in the Karnaugh map

• Step 3: Identify non-essential prime implicants for 1s in the Karnaugh

map.

• Step 4: For each essential and one selected non-essential prime

implicant from each set, determine the corresponding product term.

• Step 5: Form a sum-of-products with all product terms from previous

step.



SIMPLIFICATIONEXAMPLE FOR SOP (2)

BOOLEAN ALGEBRA

•SIMPLIFICATION-IMPLICANTS-PROCEDURE FOR SOP-EXAMPLE FOR SOP

• Simplify the following Boolean function

• Solution:

• The essential prime implicants are and .

• The non-essential prime implicants are or .

• The sum-of-products solution is

or .

F A B C, ,( ) m 0 1 4 6 7, , , ,( )∑ ABC ABC ABC ABC ABC+ + + += =

1 1 0 0

1 0 1 1

0

1

00 01 11 10ABC

zero-set 2 3 5, ,( )one-set 0 1 4 6 7, , , ,( )

AB AB

BC AC

F AB AB BC+ += F AB AB AC+ +=



SIMPLIFICATIONPROCEDURE FOR POS

BOOLEAN ALGEBRA

•SIMPLIFICATION-IMPLICANTS-PROCEDURE FOR SOP-EXAMPLE FOR SOP

• Procedure for finding the SOP from a Karnaugh map

• Step 1: Form the 2-, 3-, or 4-variable Karnaugh map as appropriate for

the Boolean function.

• Step 2: Identify all essential prime implicants for 0s in the Karnaugh map

• Step 3: Identify non-essential prime implicants for 0s in the Karnaugh

map.

• Step 4: For each essential and one selected non-essential prime

implicant from each set, determine the corresponding sum term.

• Step 5: Form a product-of-sums with all sum terms from previous step.



SIMPLIFICATIONEXAMPLE FOR POS (2)

BOOLEAN ALGEBRA

•SIMPLIFICATION-EXAMPLE FOR SOP-PROCEDURE FOR POS-EXAMPLE FOR POS

• Simplify the following Boolean function

• Solution:

• The essential prime implicants

are and .

• The non-essential prime implicants

can be or .

• The product-of-sums solution can be either

or

F A B C, ,( ) M 0 1 5 7 8 9 15, , , , , ,( )∏=

B C+ B C D+ +

A B D+ + A C D+ +

F B C+( ) B C D+ +( ) A B D+ +( )=

F B C+( ) B C D+ +( ) A C D+ +( )=

0 0 1 1

1 0 0 1

1 1 0 1

0 0 1 1

00

01

11

10

00 01 11 10ABCD

zero-set 0 1 5 7 8 9 15, , , , , ,( )one-set 2 3 4 6 10 11 12 13 14, , , , , , , ,( )



SIMPLIFICATIONDON’T-CARE CONDITION

BOOLEAN ALGEBRA

•SIMPLIFICATION-EXAMPLE FOR SOP-PROCEDURE FOR POS-EXAMPLE FOR POS

• Switching expressions are sometimes given as incomplete, or with don’t-

care conditions.

• Having don’t-care conditions can simplify Boolean expressions and

hence simplify the circuit implementation.

• Along with the and , we will also have .

• Don’t-cares conditions in Karnaugh maps

• Don’t-cares will be expressed as an “X” or “-” in Karnaugh maps.

• Don’t-cares can be bubbled along with the 1s or 0s depending on

what is more convenient and help simplify the resulting expressions.

zero-set ( ) one-set ( ) dc ( )



SIMPLIFICATIONDON’T-CARE EXAMPLE (1)

BOOLEAN ALGEBRA

•SIMPLIFICATION-PROCEDURE FOR POS-EXAMPLE FOR POS-DON’T-CARE CONDITION

• Find the SOP simplification for the following Karnaugh map

• Solution:


• There are no non-essential prime implicants.

• The sum-of-products solution is .

0 0 1 1

1 0 0 1

1 X 0 X

0 0 1 X

00

01

11

10

00 01 11 10ABCD

zero-set 0 1 5 7 8 9 15, , , , , ,( )one-set 2 3 4 6 11 12, , , , ,( )dc 10 13 14, ,( )

Takento be 0 Taken

to be 1

BD BC

F BC BD+=



SIMPLIFICATIONDON’T-CARE EXAMPLE (2)

BOOLEAN ALGEBRA

•SIMPLIFICATION-EXAMPLE FOR POS-DON’T-CARE CONDITION-DON’T-CARE EXAMPLE

• Find the POS simplification for the following Karnaugh map

• Solution:


• There are no non-essential prime implicants.

• The product-of-sums solution is .

0 0 1 1

1 0 0 1

1 X 0 X

0 0 1 X

00

01

11

10

00 01 11 10ABCD

zero-set 0 1 5 7 8 9 15, , , , , ,( )one-set 2 3 4 6 11 12, , , , ,( )dc 10 13 14, ,( )

Takento be 1

Takento be 0

B C+ B D+

F B C+( ) B D+( )=


GLITCHES AND STATIC HAZARDS (p 42)

The output of a combinational circuit may make a transition even though the patterns applied at its inputs do not imply a change. These unwanted switiching transients are called "glitches." Glitches are a consequence of the circuit structure and the application of patterns that cause the glitch to occur. A circuit in which a glitch may occur under the application of appropriate inputs signals is said to have a hazard. A static 1-hazard occurs if an output has an initial value of 1, and an input pattern that does not imply an output transition causes the output to change to 0 and then return to 1.

1-Hazard A static 0-hazard occurs if an output has an initial value of 0, and an input pattern that does not imply an output transition causes the output to change to 1 and then return to 0.

0-Hazard


GLITCHES AND STATIC HAZARDS

Static hazards are caused by differential propagation delays on reconvergent fanout paths. A "minimal"realization of a circuit might not be hazard-free. Static hazards can be eliminated by introducing redundant cubes in the cover of the output expression (the added cubes are called a hazard cover).


STATIC HAZARDS: Example

AC

B

F Reconvergentfanout paths

1

1 0

1

0 1 0 1

F0

F1

1 0

1 0 1

Consider F = AC + BC' Initial inputs: A = 1, B = 1, C = 1 and F = 1 New inputs: A = 1, B = 1, C = 0 and F = 1 • In a physical realization of the circuit (i.e. non-zero propagation delays), the path to F1 will be

longer than the path to F0, causing a change in C to reach F1 later than it reaches F0. • Consequently, when C changes from 1 to 0, the output undergoes a momentary transition to 0

and returns to 1. • The presence of a static hazard is apparent in the Karnaugh map of the output.


STATIC HAZARDS: Example (Cont.)

Static 1-Hazard occurswhen F0 and F1 are both

momentarily 0.

y

00

10

11

01

0 1

0AB

C

0

1

1 1

0 1

0F = AC + BC'

00

10

11

01

0 1

0AB

C

0

1

1 1

0 1

0Redundant

cube

• AC de-asserts before BC' asserts

• Hazards might not be significant in a synchronous sequential circuit if the clock period can be extended.

• A hazard is problematic if the signal serves

as the input to an asynchronous subsystem. (e.g a counter or a reset circuit).

• In this example, the hazard occurs because

the cube AC is initially asserted, while BC' is not. The switched input causes AC to de-assert before BC' can assert.

• Hazard Removal: A hazard can be

removed by covering the adjacent prime implicants by a redundant cube (AB, a 'hazard cover") to eliminate the dependency on C (the boundary between the cubes is now covered).


STATIC HAZARDS: Example (Cont.)

• Hazard covers require extra hardware. Example: For the hazard-free cover: F = AC + BC' + AB

AC

B

F


ELIMINATION OF STATIC HAZARDS (SOP Form)

If the output cubes of the initial and final inputs are covered by the same prime implicant, a glitch cannot occur. Otherwise, if the output cubes of the initial and final inputs are not covered by the same prime implicant a glitch can occur, depending on the accumulated delays along the signal propagation paths from the inputs to the output. For a circuit whose static 1-hazard is caused by a transition in a single bit of a single signal:

• Form a SOP cover in which every pair of adjacent 1s is covered by a cube. This gurantees that every single-bit input change is covered by such a prime implicant.

• The set of prime implicants is a hazard-free cover for a two-level (And-Or) realization

of the circuit, but a better alternative might be found.


ELIMINATION OF STATIC HAZARDS (Cont.)

To eliminate a static 0-hazard:

• Method #1: Cover the adjacent 0s in the corresponding POS expression. • Method #2: First eliminate the static 1-hazards. Then form complement function and

consider whether the implicants of the 0s of the expression that is free of static 1-hazards also cover all adjacent 0s of the original function. If they do not, then a static 0-hazard exists.


EXAMPLE: ELIMINATION OF STATIC HAZARDS

Static 1-hazard: f = Σ m(0, 1, 4, 5, 6, 7, 14, 15) = a'c' + bc

00

10

11

01

00 01 11 10

1ab

cd

1 0 0

1 1 1

0 0 1 1

0 0 0 0

1m0 m1 m3 m2

m4 m5 m7 m6

m12 m13 m15 m14

m8 m9 m11 m10

Cover the cubeboundaries byadding a'bd or a'bto eliminate thestatic 1- hazard

a'c'

bc

f = a'c' + bc + a'b

• With a = 0, b = 1, and D = 1, a glitch can occur as c changes from 1 to 0 or visa-versa.

• Adding the redundant prime implicant term eliminates the static 1-hazard.

• Note: m4 and m6 interface

Static 0-hazard (First method): From 0s of the K-map and DeMorgan's Law: f' = ac' + b'c and f = (a' + c) (b + c')

11 10

00

10

11

01

00 01

1ab

cd

1 0 0

1 1 1

0 0 1 1

0 0 0 0

1m0 m1 m3 m2

m4 m5 m7 m6

m12 m13 m15 m14

m8 m9 m11 m10

Cover byadding (a' + b)to eliminatestatic-0 hazardNote: ab'dcovers too, butis not mimimal

f = (a' + c) (b + c') (a' + b) Add a'b to f', and including the redundant prime implicant product factor (a' + b) in f to eliminate the static 0-hazard.


DYNAMIC HAZARDS (Multiple glitches)

• A circuit has a dynamic hazard if an input transition is supposed to cause a single transition

in an output, but causes two or more transitions before reached its expected value.

Dynamic Hazard

• Dynamic hazards are a consequence of multiple static hazards caused by multiply reconvergent paths in a multilevel circuit.

• Dynamic hazards are not easy to eliminate. • Elimination of all static hazards eliminates dynamic hazards.

• Approach: Transform a multilevel circuit into a two-level circuit and eliminate all of the static

hazards.


INTRO. TO COMP. ENG.CHAPTER VI-14

MULTIPLEXERSBASIC MULTIPLEXER (MUX)

COMBINATIONAL LOGIC

•ENCODERS-DESIGN W/ ENCODERS-PRIORITY ENCODERS-DESIGN W/ P-ENCODERS

• Selects one of many inputs to be directed to an output.

4x1

Mul

tiple

xer

S1 S0

0

1

2

3

f

X Y

A0

A1

A2

A3

0

X

1

X

X

X

X

X

X

0

X

1

X

X

X

X

0

0

0

0

0

1

0

1

A0=0

A2=0

A0=1

A2=1

A2A3Y A1 A0X

OutputInputsF

X

X

X

X

0

X

1

X

X

X

X

X

X

0

X

1

1

1

1

1

0

1

0

1

A1=0

A3=0

A1=1

A3=1

E

Module Enable



MULTIPLEXERSUSING PASS GATES

COMBINATIONAL LOGIC

•ENCODERS•MULTIPLEXERS

-BASIC MULTIPLEXER

• The 4x1 mux can be implemented with pass gates as follows.

Out (f)

A0

A1

A2

A3

Y X

Only one of An gets passed to output.Depends on the value of X and Y.



MULTIPLEXERSDESIGN WITH MULTIPLEXERS

COMBINATIONAL LOGIC

•ENCODERS•MULTIPLEXERS

-BASIC MULTIPLEXER-USING PASS GATES

• Any Boolean function can be implemented by setting the inputs

corresponding to the function and the selectors as the variables.

0

1

0

1

0

0

0

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

F1ZYX

8x1

Mul

tiple

xer

S2 S1

0123

f

X Y

0101

E

Module Enable

S0

Z

40506071

Example:


BUILDING BLOCKS: MULTIPLEXERS (p 60)

MUXES PROVIDE STEERING FOR DATAPATHS.

a

b

sel y_out

y_out = sel . a + sel' . b


DEMULTIPLEXERS

A demultiplexer has a single datapath input, n datapath outputs, and m address inputs. The m-bit address determines which of the n outputs is connected to the input.

Address

Data_In

Data_Out [n-1]

Data_Out [0]

m

Address[m-1: 0]

Data_In

Demultiplexer

Output channel selection:

Data_Out [n-1: 0] = Data_In [Address[k]]


ENCODERS

An encoder has n inputs and m outputs, with n = 2m. Ordinarily, only one of the inputs is asserted at a time. A unique output bit pattern (code) is assigned to each of the n inputs. The asserted output is determined by the index of the asserted bit of the n-bit binary input word.

Data_In Data_Out

Encoder

n m

Data_Out

Data_In[n-1]

Encoder

m

Data_In[0] Example: n = 4, m = 2, Data_In [3] = 1 and Data_In [k] = 0 for 0 < k < n, k ≠ 3 Data_Out [1:0] = 112 = 310 A Mux does not change the data input, but encoders transform the data input to form the data output. The encoder assigns a unique bit pattern to each input line.


PRIORITY ENCODERS

A priority encoder allows multiple input bits to be asserted simultaneously, and uses a priority rule to form an output bit pattern. Example:

Data_In [3:0] Data_out [2:0] 1xxx xxxx 000 01xx xxxx 001 001x xxxx 010 0001 xxxx 011 0000 1xxx 100 0000 01xx 101 0000 001x 110 0000 0001 111

Note: "-" denotes a don't care condition.


DECODERS

A decoder has m inputs and n outputs, with n = 2m. Only one of the outputs is asserted at a time. The asserted output is determined by the decimal equivalent of the m-bit binary input word.

Data_In Data_out

Decoder

m n

Data_In

Data_Out[n-1]

Decoder

m

Data_Out[0]

Example: n = 4, m = 2 Data_In = 112 and Data_Out [3] = 1 and Data_Out[k] = 0 for k ≠ 3



DECODERSIMPLEMENTATION

COMBINATIONAL LOGIC

•DECODERS-BASIC DECODER-WITH ENABLE-TRUTH TABLES

• How can a decoder be implemented? Fill in the circuit!

D0

A2A1A0

D1

A2A1A0

D2

A2A1A0

D3

A2A1A0

D4

A2A1A0

D5

A2A1A0

D6

A2A1A0

D7

A2A1A0

A0A1A2



DECODERSDESIGNING WITH DECODERS

COMBINATIONAL LOGIC

•DECODERS-WITH ENABLE-TRUTH TABLES-IMPLEMENTATION

• Any Boolean function can implemented using a decoder and OR gates by

ORing together the function’s minterms.

0

1

1

0

1

1

0

0

0

1

0

1

0

0

0

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

F2F1

OutputsInputsA0A1A2

3-to

-8D

ecod

er

01234567

20

21

22

A0

A1

A2 F2

F1



DECODERSDECODER NETWORKS

COMBINATIONAL LOGIC

•DECODERS-TRUTH TABLES-IMPLEMENTATION-DESIGNING W/DECODERS

• We can also use multiple decoders to form a larger decoder.

2-to

-4D

ecod

er

0123

20

21

A0

A1

D0D1D2D3

D4D5D6D7

E

2-to

-4D

ecod

er

0123

20

21

A2

E

3-to-8 Decoder Implementedwith two 2-to-4 Decoders

A2 used with enable inputto control which decoderwill output the 1.

A1 and A0 used to selectwhich output on specificdecoder will output 1.



ADDERSHALF- AND FULL-ADDERS

COMBINATIONAL LOGIC

•DEMULTIPLEXERS•SHIFTERS•ROTATORS

-BASIC ROTATOR

• Two basic building blocks for arithmetic are half- and full-adders as

depicted by the block diagrams below.

Half-adder Full-adder

HA

BA

S

COUT

Sum

Carry-outFA

BA

S

COUT

Sum

Carry-out

CIN

Carry-in



ADDERSHALF-ADDER (HA)

COMBINATIONAL LOGIC

•SHIFTERS•ROTATORS•ADDERS

-HALF- & FULL-ADDERS

• First of all, how do we add?

• 2’s complement arithmetic allows us to add numbers normally.

0

0

1

1

0

1

0

1

BA

0

0

0

1

0

1

1

0

S COUT

S AB AB+ A B⊕= =

COUT AB=

Sum Carry-outInputs

AB

S

COUT



ADDERSFULL-ADDER (FA) (1)

COMBINATIONAL LOGIC

•ROTATORS•ADDERS

-HALF- & FULL-ADDERS-HALF-ADDER (HA)

• Half-adder missed a possible carry-in. A full-adder (FA) includes this

additional carry-in.

0000

0011

BA

0001

0110

S COUT

S A B⊕( ) CIN⊕=

COUT AB CIN A B⊕( )+=

Sum Carry-outInputs

0101

CIN

Carry-in

1111

0011

0101

1001

0111



ADDERSFULL-ADDER (FA) (2)

COMBINATIONAL LOGIC

•ADDERS-HALF- & FULL-ADDERS-HALF-ADDER (HA)-FULL-ADDER (FA)

S A B⊕( ) CIN⊕=

COUT AB CIN A B⊕( )+=

S

COUT

AB

CIN

Half-adder Half-adder



ADDERSBINARY ADDITION

COMBINATIONAL LOGIC

•ADDERS-HALF- & FULL-ADDERS-HALF-ADDER (HA)-FULL-ADDER (FA)

• A 4-bit binary adder can be formed with four full-adders as follows.

FA

B0A0

S0

C1C0FA

B1A1

S1

C2FA

B2A2

S2

C3FA

B3A3

S3

C4

CS8803: Advanced Digital Design for Embedded...

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