Large Scale Circuit Partitioning - Web Hosting Default...
Transcript of Large Scale Circuit Partitioning - Web Hosting Default...
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Large Scale Circuit Partitioning With Loose/Stable Net Removal
And Signal Flow Based Clustering
Support : DARPA/ITO, NSF, Fujitsu MICRO
Jason CongHonching Li
Sung-Kyu LimDongmin Xu
UCLA VLSI CAD Lab
Toshiyuki Shibuya
Fujitsu Lab, LTD
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Outline
• Loose and Stable net Removal Partitioning Algorithm
• Maximum Fanout Free Subgraph Clustering Algorithm
• Performance of LSR/MFFS
• Conclusion & Ongoing Work
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LSR Partitioning
1. Background
2. Motivation
3. Implementation
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Circuit Partitioning
• Formulation– minimize connection– satisfy area constraint
• Significance– fundamental for hierarchical layout– essential for future technology
• Iterative Improvement Partitioning– flexible, effective, and efficient
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Evolution of IIP Algorithm
• Early Development– KL : Kernighan & Lin [Bell70]– FM : Fiduccia & Mattheyses [DAC82]– LA : Krishnamurthy [TCom84]
• Recent Development– CDIP/PROPf : Dutt & Deng [ICCAD96]– Strawman : Hauck & Borriello [TCAD96]– hMetis : Karypis & Kumar [DAC97]– MLc : Alpert, Huang & Kahng [DAC97]
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FM Algorithm Basics
• Basic Operation : Cell Move– cost : gain (= reduction in cutsize)– constraint : area balance– cell status : free or locked
• Structurewhile (gain > 0)
while (∃ free cell)move cell
retrieve max-gain movespass run
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Loose-net Removal (LR)
• New Gain Formulation
block 0 block 1
FREE net : only free cells
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Loose-net Removal (LR)
• New Gain Formulation
block 0 block 1
LOOSE net : locked cells in one block
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Loose-net Removal (LR)
• New Gain Formulation
block 0 block 1
-3 -2FM :
FREE cells of LOOSE net
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Loose-net Removal (LR)
• New Gain Formulation
block 0 block 1
IMMEDIATE ATTENTION, W > 0
W WLR :
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Loose-net Removal (LR)
• New Gain Formulation
block 0 block 1
WLR : +W
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Loose-net Removal (LR)
• New Gain Formulation
block 0 block 1
LOOSE net removed
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more LOOSE net formed
Loose-net Removal (LR)
• New Gain Formulation
block 0 block 1
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Loose-net Removal (LR)
• New Gain Formulation
block 0 block 1
Net Pulling Effect
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block 0 block 1
LR Implementation
• Gain Increase of LR
favor shorter nets
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LR Implementation
• Gain Increase of LR
block 0 block 1
incr(n) =k
size(n)
33 33
25 25 25
= 100
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LR Implementation
• Gain Increase of LR : upper bound
k
Less Tie-Break
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LR Implementation
• FM Enhancement
while (gain > 0)while (∃ free cell)
move max-gain cell c
retrieve max-gain moves
for (each loose net n incident on c)for (each free cell f of n)
if (f.gain < T)f.gain += incr(n)
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Performance of LR
• Bipartitioning without Clustering
922
1023
1956
1761
500 700 900 1100 1300 1500 1700 1900 2100
LR
CDIP
LA3
FM
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Stable Net Transition (SNT)
• Stable Net [Shibuya et al, FSTJ95]– remain cut during entire run– limit FM solution
• Stable Net Removal– at the end of each run– detect stable net and isolate– new initial partition– fast convergence
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Enhancement of LR
• Benefit of LR + SNT– small loose + big stable net– dynamic + static– speedup LR
• How?– initial partition by SNT for next run of LR– Loose and Stable net Removal (LSR)
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MFFS Clustering
1. Motivation
2. Algorithm
3. Speedup
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Circuit Clustering
• Definition– group closely connected component in
circuits
• Significance– reduce problem size– speedup partitioning– improve partitioning solution– refinement through decomposition
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Maximum Fanout Free Cone
• Significance [Cong & Ding, DAC93]– exploit signal flow during clustering– group logically dependant cells– linear time complexity
• Benefit– partitioning [Cong, Li, & Bagrodia DAC94]– placement [Cong & Xu, ASP-DAC95]
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Definition of MFFC
• Cone Rooted at v : Cv– v and its predecessor s.t. if u in Cv, every
path from u to v resides entirely in Cv
• Fanout Free Cone at v : FFCv– Cv is fanout free if output(Cv) = output(v)
• Maximum FFCv : MFFCv– fanout free and maximum FFCv
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Definition of MFFC
• Find All Single MFFC– complexity : O(|N|+|E|)
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Limitation of MFFC
• Designed for Combinational Circuit– can’t handle cycles in sequential circuit
applyMFFC
algorithm
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Limitation of MFFC
• Designed for Combinational Circuit– can’t handle cycles in sequential circuit
applyMFFS
algorithm
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Definition of MFFS
• For a node v in a sequential circuit;
MFFSv = {u|for all FFSv, u ∈ FFCv } – Maximum Fanout Free Subgraph rooted at v
FFSv = {u|every path from u to somePO passes through v }
– Fanout Free Subgraph rooted at v
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MFFS Construction
• For Single MFFSv
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MFFS Construction
• For Single MFFSv– select root node v and cut its fanout
v
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MFFS Construction
• For Single MFFSv– mark nodes reachable backwards from PO
v
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MFFS Construction
• For Single MFFSv– MFFSv = {unmarked nodes}
v
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MFFS Construction
• For Single MFFSv– complexity : O(|N|+|E|)
v
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MFFS Clustering
• For Clustering Entire Circuit
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MFFS Clustering
• For Clustering Entire Circuit– find MFFSv and remove
v
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MFFS Clustering
• For Clustering Entire Circuit– find MFFSv and remove
v
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MFFS Clustering
• For Clustering Entire Circuit– output to removed nodes is new PO
v
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MFFS Clustering
• For Clustering Entire Circuit– repeat until all nodes are clustered
vv
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MFFS Clustering
• For Clustering Entire Circuit– repeat until all nodes are clustered
v v
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MFFS Clustering
• For Clustering Entire Circuit– repeat until all nodes are clustered
v v
v
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MFFS Clustering
• For Clustering Entire Circuit– repeat until all nodes are clustered
v v
v
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MFFS Clustering
• For Clustering Entire Circuit– complexity : O(|N|• (|N|+|E|))
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Speedup of MFFS Clustering
• Single MFFSv Construction– slow : O(|N|+|E|)
v
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Speedup of MFFS Clustering
• Subset of MFFSv– search on subcircuit
v
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Speedup of MFFS Clustering
• Subset of MFFSv
circuit
h
v
SC (v, h)
– internal node : depth h-BFS at node v
pseudo PIs
pseudo POs
– pseudo PI/PO : I/O to/from subcircuit
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LSR/MFFS Algorithm
• Overview– cluster circuit with MFFS approximation
algorithm– partition clustered circuit with LSR
algorithm– decompose clusters completely– refine cutline with LSR algorithm on
declustered circuit
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Experimental Result
1. Experiment Setting
2. MFFS Clustering
3. LSR/MFFS Partitioning
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Experimental Setting
• Benchmark– 16 MCNC circuits with signal flow info– SPARC 5-85 with gcc v2.4– bipartitioning under 45-55% skew– real cell area
Area Variation Ratio = min cell areamax cell area
• Metric– cutsize : min of 20 runs– runtime : total of 10 runs
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MFFS Clustering Result
Exact Approxckt size AVR # clst time # clst time
s1423 619 1.0 193 0.9 168 1.9
sioo 664 4.6 442 2.3 442 2.6
………
s35932 18148 1.0 5562 420.8 2943 32.1
s38584 20995 1.0 5139 565.1 4242 44.5
avq.sm 21918 4.5 8477 1287.3 8309 116.1
S38417 23949 1.0 5906 452.2 5295 45.1
avq.lg 25178 4.5 9103 1473.2 8658 90.2
Total 150379 48033 4543.9 42494 449.7
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Cutsize Reduction Trend
500 700 900 1100 1300 1500 1700 1900
LSR
LR
SNT
FM
![Page 52: Large Scale Circuit Partitioning - Web Hosting Default Pageusers.ece.gatech.edu/limsk/www/slides/iccad97.pdf · Large Scale Circuit Partitioning ... DARPA/ITO, NSF, Fujitsu MICRO](https://reader031.fdocuments.in/reader031/viewer/2022030421/5aa908d57f8b9a6c188c4d5a/html5/thumbnails/52.jpg)
Cutsize Reduction Trend
500 700 900 1100 1300 1500 1700 1900
LSR
LR
SNT
FM
![Page 53: Large Scale Circuit Partitioning - Web Hosting Default Pageusers.ece.gatech.edu/limsk/www/slides/iccad97.pdf · Large Scale Circuit Partitioning ... DARPA/ITO, NSF, Fujitsu MICRO](https://reader031.fdocuments.in/reader031/viewer/2022030421/5aa908d57f8b9a6c188c4d5a/html5/thumbnails/53.jpg)
Cutsize Reduction Trend
500 700 900 1100 1300 1500 1700 1900
LSR
LR
SNT
FM
![Page 54: Large Scale Circuit Partitioning - Web Hosting Default Pageusers.ece.gatech.edu/limsk/www/slides/iccad97.pdf · Large Scale Circuit Partitioning ... DARPA/ITO, NSF, Fujitsu MICRO](https://reader031.fdocuments.in/reader031/viewer/2022030421/5aa908d57f8b9a6c188c4d5a/html5/thumbnails/54.jpg)
Cutsize Reduction Trend
500 700 900 1100 1300 1500 1700 1900
LSR
LR
SNT
FM
FLATMFFS
LR, SNT, MFFS are all effective
![Page 55: Large Scale Circuit Partitioning - Web Hosting Default Pageusers.ece.gatech.edu/limsk/www/slides/iccad97.pdf · Large Scale Circuit Partitioning ... DARPA/ITO, NSF, Fujitsu MICRO](https://reader031.fdocuments.in/reader031/viewer/2022030421/5aa908d57f8b9a6c188c4d5a/html5/thumbnails/55.jpg)
Runtime Reduction Trend
0 50 100 150
LSR
LR
SNT
FM
![Page 56: Large Scale Circuit Partitioning - Web Hosting Default Pageusers.ece.gatech.edu/limsk/www/slides/iccad97.pdf · Large Scale Circuit Partitioning ... DARPA/ITO, NSF, Fujitsu MICRO](https://reader031.fdocuments.in/reader031/viewer/2022030421/5aa908d57f8b9a6c188c4d5a/html5/thumbnails/56.jpg)
Runtime Reduction Trend
0 50 100 150
LSR
LR
SNT
FM
![Page 57: Large Scale Circuit Partitioning - Web Hosting Default Pageusers.ece.gatech.edu/limsk/www/slides/iccad97.pdf · Large Scale Circuit Partitioning ... DARPA/ITO, NSF, Fujitsu MICRO](https://reader031.fdocuments.in/reader031/viewer/2022030421/5aa908d57f8b9a6c188c4d5a/html5/thumbnails/57.jpg)
Runtime Reduction Trend
0 50 100 150
LSR
LR
SNT
FM
![Page 58: Large Scale Circuit Partitioning - Web Hosting Default Pageusers.ece.gatech.edu/limsk/www/slides/iccad97.pdf · Large Scale Circuit Partitioning ... DARPA/ITO, NSF, Fujitsu MICRO](https://reader031.fdocuments.in/reader031/viewer/2022030421/5aa908d57f8b9a6c188c4d5a/html5/thumbnails/58.jpg)
Runtime Reduction Trend
0 50 100 150
LSR
LR
SNT
FM
FLATMFFS
SNT and MFFS are both effective
![Page 59: Large Scale Circuit Partitioning - Web Hosting Default Pageusers.ece.gatech.edu/limsk/www/slides/iccad97.pdf · Large Scale Circuit Partitioning ... DARPA/ITO, NSF, Fujitsu MICRO](https://reader031.fdocuments.in/reader031/viewer/2022030421/5aa908d57f8b9a6c188c4d5a/html5/thumbnails/59.jpg)
Cutsizes Among IIPs
845
861
872
898
961
1023
700 750 800 850 900 950 1000 1050
LSR/MFFS
MLc
hMetis
Strawman
PROPf
CDIP
achieved BEST cutsize
![Page 60: Large Scale Circuit Partitioning - Web Hosting Default Pageusers.ece.gatech.edu/limsk/www/slides/iccad97.pdf · Large Scale Circuit Partitioning ... DARPA/ITO, NSF, Fujitsu MICRO](https://reader031.fdocuments.in/reader031/viewer/2022030421/5aa908d57f8b9a6c188c4d5a/html5/thumbnails/60.jpg)
Runtimes Among IIPs
1388
3455
1388
12577
5611
5817
0 1000 2000 3000 4000 5000 6000
LSR/MFFS
MLc
hMetis
Strawman
PROPf
CDIP
achieved BEST runtime
???
![Page 61: Large Scale Circuit Partitioning - Web Hosting Default Pageusers.ece.gatech.edu/limsk/www/slides/iccad97.pdf · Large Scale Circuit Partitioning ... DARPA/ITO, NSF, Fujitsu MICRO](https://reader031.fdocuments.in/reader031/viewer/2022030421/5aa908d57f8b9a6c188c4d5a/html5/thumbnails/61.jpg)
Cutsizes Among Non-IIPs
509
516
648
749
300 400 500 600 700
LSR/MFFS
PANZA
FBB
Paraboli
achieved BEST cutsize
![Page 62: Large Scale Circuit Partitioning - Web Hosting Default Pageusers.ece.gatech.edu/limsk/www/slides/iccad97.pdf · Large Scale Circuit Partitioning ... DARPA/ITO, NSF, Fujitsu MICRO](https://reader031.fdocuments.in/reader031/viewer/2022030421/5aa908d57f8b9a6c188c4d5a/html5/thumbnails/62.jpg)
Runtimes Among Non-IIPs
achieved BEST cutsize
1388
16024
24619
0 10000 20000
LSR/MFFS
PANZA
FBB
Paraboli
???
![Page 63: Large Scale Circuit Partitioning - Web Hosting Default Pageusers.ece.gatech.edu/limsk/www/slides/iccad97.pdf · Large Scale Circuit Partitioning ... DARPA/ITO, NSF, Fujitsu MICRO](https://reader031.fdocuments.in/reader031/viewer/2022030421/5aa908d57f8b9a6c188c4d5a/html5/thumbnails/63.jpg)
Conclusion & Ongoing Work
• LSR Partitioning– Loose and Stable net Removal
• MFFS Clustering– Maximum Fanout Free Subgraph
• Performance of LSR/MFFS
• Ongoing Work– LSR : multi-way partitioning– MFFS : multi-level cluster hierarchy– LSR/MFFS : mincut based placement
![Page 64: Large Scale Circuit Partitioning - Web Hosting Default Pageusers.ece.gatech.edu/limsk/www/slides/iccad97.pdf · Large Scale Circuit Partitioning ... DARPA/ITO, NSF, Fujitsu MICRO](https://reader031.fdocuments.in/reader031/viewer/2022030421/5aa908d57f8b9a6c188c4d5a/html5/thumbnails/64.jpg)
Thank You
For Your Attention