CrossTalk and Shielding

8/3/2019 CrossTalk and Shielding

http://slidepdf.com/reader/full/crosstalk-and-shielding 1/6

Optimal Crosstalk Shielding Insertion

along On-Chip Interconnect Trees

Boyan Semerdjiev and Dimitrios VelenisDepartment of Electrical and Computer Engineering

Illinois Institute of Technology

Chicago, IL 60616

Email: [email protected], [email protected]

Abstract— Scaling of the on-chip feature size down into

the deep submicron range has emphasized the importance of

interconnect delay variations due to capacitive coupling. A

methodology for reducing crosstalk noise on tree-structured inter-

connects is proposed in this paper. An algorithm is implemented

to compute the optimal sequence of shielding insertion along a

capacitively coupled interconnect tree. The reduction in crosstalk

is verified through simulation and compared to alternativeshielding schemes, considering the availability of limited shielding

resources. It is demonstrated that the reduction in interconnect

delay variations achieved by the proposed methodology is con-

sistently higher. Furthermore, it is shown that delay variations

between two critical nodes in a tree can also be reduced by the

same shielding insertion approach.

I. INTRODUCTION

The scaling of the on-chip feature size within the deep

submicron range has shifted the design effort of integrated

circuits towards enhancing the performance of on-chip in-

terconnect lines. As interconnect wires become thinner andmore densely routed, the wire capacitance to ground is de-

creased and coupling capacitance among the lines increases

[1]. Crosstalk noise induced by signal switching events on

capacitively coupled interconnects can cause the delay of a

signal to deviate from its target value [2], [3]. Signal delay

variations along a critical path of a system can cause a wrong

data to be latched within a register, thereby causing a circuit to

malfunction. To compensate for the effects of delay variations,

the timing constraints in a system are relaxed and the maxi-

mum operating frequency is reduced [4]. Therefore, alleviating

the effects of coupling capacitance among interconnects is a

critical task for reducing delay variations and enhancing the

circuit performance.Several methods can be utilized to reduce the effects of

crosstalk noise on coupled interconnect lines. Increasing the

spacing among interconnect wires reduces the amount of

coupling and the variations in signal delay [5]. This ap-

proach, however, reduces the interconnect routing density and

therefore the functionality of an integrated system. Alterna-

tively, the routing of power and ground lines among signal

propagating wires can effectively decrease capacitive coupling

and reduce the effects that introduce crosstalk noise [3]. The

insertion of these power and ground supply lines is called

interconnect shielding.

The utilization of interconnect shielding depends upon the

available resources of power and ground lines. The primary

effort in this paper is focused on optimizing the application

of shielding lines, considering the resource constraints. The

proposed methodology can be applied to any tree interconnect

structure in order to reduce the signal delay variations at atree node. In this paper, the application of shielding on clock

trees is considered for reducing the effects of crosstalk noise

on the clock signal arriving at critical registers.

The proposed shield insertion methodology is presented

in Section II. An algorithm that implements the proposed

methodology is described in Section III. The developed algo-

rithm is utilized to determine the application of shielding in a

set of tree structured interconnects. The resulting reduction in

signal delay variations is presented in Section IV. Furthermore,

the proposed methodology is used in Section V to determine

the insertion of shielding when two critical nodes are consid-

ered within a tree. Finally, some conclusions are presented in

Section VI.

II. PATH SHIELDING ALONG TREE STRUCTURED

INTERCONNECTS

In this paper crosstalk noise along clock tree structures is

considered. The clock signal is generated at the source of the

tree and propagates to the clocked registers located at the leaf-

nodes of the tree. The unique route along the tree between the

clock signal source and a register node is defined as the path

between the source and that node. All the other segments on

the clock tree that are not on the path to a node are specified

as branches. A critical node on the tree represents a register of

a critical path. Variations of the clock signal delay to that node

can violate the timing constraints at the register and cause asystem malfunction. The entire tree structure is considered to

be coupled with interconnect lines routed in parallel to the

tree segments. It is assumed that all the coupled lines switch

together at the same time with the clock signal, therefore

introducing the largest amount of crosstalk on the clock tree.

The effects of crosstalk noise among interconnect lines are

described using the aggressor-victim model. A signal transition

on an aggressor line affects the propagation of a signal along

a victim line. In the discussion that follows the clock tree



is considered the victim interconnect structure. The parasitic

capacitance

per unit length for a coupled interconnect wire

is determined by two primary components, the capacitance to

the ground substrate, and the coupling capacitance to adjacent

lines. The total line capacitance is

¡ ¢ ¤ ¢ § ¨ ¡ ¤ ! # % ¡ ( ¤ 0 ¨ 3

(1)

where

¡ ¤

is the ground substrate capacitance,

¡ ( ¤ 0 ¨ 3

is the coupling capacitance between wires, and#

is a constant

that depends upon the signal switching conditions on the cou-

pled lines [6]. If two capacitively coupled interconnect lines

switch in the same direction at the same time then the value of #

is zero and the coupling capacitance component¡ ( ¤ 0 ¨ 3

is cancelled. If the lines switch in opposite directions, then# 8

and the effective coupled capacitance is maximum.

This case represents the worst-case delay of a signal along

the victim line. If the aggressor line does not switch, the

value of #

is one. This variation in the effective capacitance

of an interconnect wire due to crosstalk causes variations in

the signal propagation delay along a line.

Interconnect shielding can alleviate the effects of crosstalk and reduce the delay variations of interconnect signals. A

quiescent power (@ A A

) or ground line is routed between the

two coupled lines, forcing the value of #

factor to become

one and eliminating the variations of the¡

( ¤ 0 ¨ 3

component.

Therefore, the total effective capacitance of a shielded signal

line is constant:¡ C D 3 F ¨ F ¡ ¤ ! ¡ ( ¤ 0 ¨ 3

.

It is demonstrated that interconnect shielding is an efficient

method to reduce crosstalk noise. In order to completely

eliminate the noise effects along a clock tree, power supply

wires are required to be routed parallel to the entire tree

structure which may not be feasible. In a practical design,

the available shielding resources are sufficient for covering

only a portion of the clock tree. The shielding methodologypresented in this paper optimizes the placement of limired

shielding resoures in order to minimize the effects of crosstalk

noise at a critical node within a tree. The basic concept of this

methodology is presented next.

A. Shielding placement along the direct path from the tree

source to a critical node

Initially, the insertion of shielding along the direct path

between the signal source and a critical tree node is consid-

ered. The distributed interconnect resistance and capacitance is

modelled usingT

¡

segments of unit size. It is assumed that

only one unit segment within the clock tree is shielded on

the path from the source to the critical node, as illustrated inFigure 1. Two posible locations are considered for shielding

insertion, one closer to the source as shown in Figure 1(a),

and one closer to the critical node, as illustrated in Figure

1(b). The effect of the shielding placement on the variation of

signal delay at the critical node is evaluated next, considering

that the clock tree and the aggressor line can switch both in

the same and in opposite directions.

The case where both the aggressor line and the clock tree

switch in the same direction is considered first. In this case the

ClockSource

CriticalNode

branch

branch

Direct Path

R

Shielded line segment

Non-shielded line segment

Common path resistance

(a) Close-to-Source Shielding

Clock

Source

Critical

Node

branch

branch

Direct Path

R’

Shielded line segment

Non-shielded line segment

Common path resistance

(b) Close-to-Node Shielding

Fig. 1. Shielding placement along the direct path from the source to a criticalnode

effective capacitance of the non-shielded wire segment will be¡ U V U Y C D 3 F ¨ F ¡ ¤

which is less than the capacitance

of the shielded segment:¡ C D 3 F ¨ F ¡ ¤ ! ¡ ( ¤ 0 ¨ 3

.

Using the Elmore delay model [7] to evaluate the clock signal

delay at the critical node results in a higher delay value when

the shielded segment is placed closer to the node, as shown in

Figure 1(b). The greater delay is due to the greater common

path resistance factor multiplied with the¡ C D 3 F ¨ F

component

in the tree illustrated in Figure 1(b) compared with the tree

shown in Figure 1(a). Therefore, when both lines switch in

the same direction the signal delay is less when shielding is

applied closer to the source of the tree

g

( ¨ ¤ C F Y C ¤ ( F h

g

( ¨ ¤ C F Y ¤ F

(2)

Alternatively, in the case that the aggressor line and the

clock tree switch in opposite directions, the effective ca-

pacitance of the non-shielded segment is¡ U V U Y C D 3 F ¨ F

¡ ¤ ! 8 % ¡ ( ¤ 0 ¨ 3

, which is higher than¡ C D 3 F ¨ F

.

Therefore, the delay of the clock signal is greater when thenon-shielded segment is placed closer to the critical node and

multiplied with the greater common path resistance factor. In

this case, the effect of shielding to the signal delay is

v

( ¨ ¤ C F Y ¤ Fh

v

( ¨ ¤ C F Y C ¤ ( F

(3)

The maximum delay variation at a critical node of the tree

is expressed by the difference in the signal delay when the

lines switch in the same and opposite directions. When the

shielding segment is placed closer to the source of the tree,



the maximum delay variation at the critical node is

y

v

( ¨ ¤ C F Y C ¤ ( F

v

( ¨ ¤ C F Y C ¤ ( F �

g

( ¨ ¤ C F Y C ¤ ( F

(4)

When the shielding segment is placed closer to the critical

node, the maximum delay variation is

y

v

( ¨ ¤ C F Y ¤ F

v

( ¨ ¤ C F Y ¤ F�

g

( ¨ ¤ C F Y ¤ F

(5)

Considering the expressions (2) and (3) it can be shown thaty

v

( ¨ ¤ C F Y C ¤ ( F �y

v

( ¨ ¤ C F Y ¤ F

(6)

It is shown by expression 6 that the variations in signal

delay are greater when the shielding is applied further away

from the critical nodes of the clock tree. Therefore, inserting

shielding lines closer to a critical node in a clock tree results in

greater efficiency in the utilization of the shielding resources.

B. Shielding placement along the tree branches

Furthermore, the effect of shielding at a tree branch segment

upon the delay variation of the clock signal arriving at a critical

node is investigated. A tree branch is considered a line segment

that does not belong in the path from the clock source to a

critical node. A unit wire segment along a branch of a clock

tree is shielded on two different locations, as shown in Figure

2. The shielded segment can be closer to the direct path from

the source to a critical node as shown in Figure 2(a), or farther

away, as illustrated in Figure 2(b).

ClockSource

CriticalNode

branch

Direct Path

Shi elded line seg ment Non -shielded line segment

branch

(a) Close-to-Path Shielding

ClockSource

CriticalNode

branch

Direct Path

Shielded line segmentNon-shielded line segment

branch

(b) Far-from-Path Shielding

Fig. 2. Shielding placement along a tree branch, with respect to the directpath from source to a critical node

The effect of the shielding placement on the variation of

the signal delay at the critical node is evaluated next. Initially

it is assumed that the clock tree and the aggressor lines are

switching in the same direction. Applying the Elmore delay

model provides exactly the same delay values for both shield-

ing locations, since the branch capacitances are multiplied by

the same resistive coefficient. More accurate delay values at a

critical node of the tree can be obtained with the use of the

lognormal delay metric [8]–[11] given by:

� � � � � �

�

8

�

�

(7)

where �

� represents the Elmore delay and �

�

characterizes

the second moment of the tree circuit at the critical node.� � �

represents the signal delay to the critical node. Using this

approach, it is shown that the signal delay at the critical node

of the clock tree is higher for the circuit shown in Figure 2(a),

compared with the circuit illustrated in Figure 2(b). Therefore,

when both the clock tree and the aggressor lines switch in the

same direction, the effect of shielding location on a branch is

g �

§ Y 0 § ¢ Dh

g

( ¨ ¤ C F Y 0 § ¢ D

(8)

Alternatively, when the aggressor lines and the clock tree

switch in opposite directions, the delay at a critical node is

smaller when the branch shielding is applied closer to the

direct path to that node. Therefore, for opposite switching

interconnects:

v

( ¨ ¤ C F Y 0 § ¢ D h

v

�

§ Y 0 § ¢ D

(9)

The maximum delay variation at a critical node of the tree

is expressed by the difference between the signal delay when

the lines switch in the same and opposite directions. When

shielding is placed closer to the direct path to the critical node,

the delay variation at that node is

y

v

( ¨ ¤ C F Y 0 § ¢ D

v

( ¨ ¤ C F Y 0 § ¢ D�

g

( ¨ ¤ C F Y 0 § ¢ D

(10)

When the shielding segment is placed farther on the branch,

the delay variation is

y

v

�

§ Y 0 § ¢ D

v

�

§ Y 0 § ¢ D �

g�

§ Y 0 § ¢ D

(11)

Considering the expressions 8 and 9 it can be shown that

y

v

�

§ Y 0 § ¢ D �y

v

( ¨ ¤ C F Y 0 § ¢ D

(12)

Therefore, it is demonstrated that the variations in signal

delay are less when shielding on a branch is applied at acloser location to the direct path from the tree source to a

critical node. Considering the analysis of shielding on the

direct path that was discussed earlier, it can be concluded

that the closer the application of shielding is to a critical

tree node, the greater the reduction of the delay variations at

that node. This is the basic concept of the proposed shielding

methodology that enhances the shielding efficiency on tree

structured interconnects. An algorithm that implements this

approach is described in the next section.



III. SHIELDING INSERTION ALGORITHM

It is demonstrated in section II that the effectiveness of

interconnect shielding on reducing delay variation at a critical

node is enhanced when shielding is applied in the close

proximity of that node. An algorithm that implements this

concept is developed and presented in this section. This

algorithm determines the optimum segments of a tree that

should be shielded in order to achieve the greatest reductionin signal delay variations at a specific node. Constraints in the

availability of shielding resources are also considered within

the proposed approach and they are expressed as the maximum

percentage of the tree structure that can be shielded.

The position of a critical node within a tree is the preferred

location to begin the application of shielding. The entire tree

structure is subdivided into unit length segments. Shielding

is applied iteratively at single unit segment steps from the

location of the critical node towards the source of the tree.

The set of possible unit segments that can be shielded in a

single iteration is defined as the shielding frontier .

In the first iteration of the algorithm the shielding frontier

is the wire segment adjacent to the critical node. In every

iteration the frontier advances by one unit segment towards

the source of the tree. When a branch node within the tree

is reached, the segments on both downstream directions of

the branch node are inserted in the frontier. In the next

iteration two segments are candidates for shield insertion. To

determine which one is the best candidate, the reduction in

delay variation at the critical node is calculated assuming that

each one of the frontier segments is shielded. The segment

resulting in the greatest reduction in delay variation is selected

and the segment(s) downstream are added to the frontier.

An example of the application of the algorithm on a tree

structure is illustrated in Figure 3. In the tree circuit shown in

VPULSECL

A

B

C

(a) Step 1 - Three segments inthe frontier

VPULSE

A

B (Shielded)

C

D

CL

(b) Step 2 - Segment�

isshielded and � is added to thefrontier

VPULSE

Shielded

C

D

E

F CL

A

(c) Step 3 - Segments�

and

are added to the frontier aftershielding segment

VPULSE

C

DShielded

F

G

CL

E

(d) Step 4 - Segment�

isshielded and segment

is in-

serted in the froniter

Fig. 3. Example of shielding application sequence

Figure 3(a) the shielding sequence was initiated at the critical

node and has propagated toward the source of the tree. There

are three segments

,

, and¡

in the frontier. The reduction

in the delay variation at the critical node is calculated assuming

that each one of the segments

,

, and¡

are shielded.

It is assumed that the shielding of segment

produces the

greatest reduction in delay variation. Therefore, segment

is shielded and the downstream segment�

is inserted in the

frontier, as shown in Figure 3(b). The shielding of segments

,¡

, and�

in the frontier is evaluated again and segment

is selected, as illustrated in Figure 3(c). After segment

is shielded, segments and j are inserted in the frontier. In

the following step segment

is selected for shielding among

segments¡

,�

, , and j , as shown in Figure 3(d). At the

end of this step the frontier set contains the nodes¡

,�

,j

,

and k .

The lognormal delay metric [8] is utilized within the

algorithm to determine the reduction in the delay variation

when the shielding of each candidate segment is considered.

Calculating the first and second moments at the critical node

has a quadratic dependence on the total number of unit lengthsegments in the tree. The first and second moments can

potentially be calculated for every unit segment in the tree.

Therefore, the complexity of the algorithm is l m

� o

, where�

is the total number of unit segments. The pseudocode of

the algorithm is listed in Figure 4. Notice in Figure 4 that the

algorithm terminates when either the frontier set is empty (i.e.

the entire tree is shielded), or when all the available shielding

resources are utilized.

z { | } } ~ { { { { z ~ { z

{ ~ { { { { }

{ ~ { { ~ | ~ z { {

z } { { ~ { ~ } }

} } { } } z { {

{ ~ { { { ~ { ~ } }

} { { ~ { ~ } }

� z } { { ~ { ~ } }

} } { } } z { {

{ ~ { { { ~ { ~ } }

} { { ~ { ~ } }

} � { { { ~ { ~ } }

� � � � � � � � � � � � � � � � � � � �

� � � � � � � � � � � � � � � � � � � � � � � � � � � � �

�

� � � � � � � � � � � � � � � � � � �

� � � � � � �

� � � � � � � � � � � � � � � � � � � � � � � � � � �

� � � � � � � � � � � � � � � � �

� � � � � � � � � � � ª � � � � � � � � � � � �

� � � � � � �

� � � � � � � � � � � � � � � � � �

« ¬ � � � � �

� ¬ � � � � � � � � � � � �

� � � � � � � � �

� � � ¬ � � � � � � � � ª � � � � � � � �

Fig. 4. Program Pseudocode

IV. SHIELDING APPLICATION RESULTS

The developed algorithm is applied to a set of interconnect

tree structures in order to evaluate the effect of the proposed

path-and-branch shielding methodology on the signal delay

variations at a critical tree node. The proposed approach

CrossTalk and Shielding

Documents

Transcript of CrossTalk and Shielding