CPRE491 Team Dec11‐08 Project Plan

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Introduction Write blockers are devices that allow acquisition of hard disk data without the possibility of accidental contamination by modification. A write blocker allows read commands and drops write commands to a device.

Currently many USB 2.0 to SATA write blocking devices exist, but none for USB 3.0. The projects scope will be to develop a working prototype of a USB 3.0 to SATA

write blocker. The device would act as a bridge between USB 3.0 and a SATA Hard drive.

Purpose The project is to design a blocker device that protects any USB 3.0 SATA hard drive. Audience Project client Course instructor Faculty advisor Team members

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Frontal Material USB 3.0 Write Blocker Project Plan Project/team number Dec11-08 Client’s name Electronic Crime Institute - Des Moies Area Community College Faculty advisor’s name Dr. Zhao Zhang Team members’ names Chen Zhao Elphas Sang Yan Fang Date submitted Jan, 18, 2011 Table of contents

contents Page number

Frontal material 2

Introductory material 3

System requirements 4

Project management 8

Conclusion 11

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Introductory Material Executive summary

This project requires at least one programmable hardware development board that

supports USB 3.0 standards and either a SATA interface or a daughterboard with SATA

interface. The project also needs a software platform corresponding to the hardware to

do hardware programming and configuration.

The principle of the project is to conduct FPGA design on a programmable

hardware platform to make it capable of data processing conforming to USB 3.0

standards. The processor designed is to filter various writing commands to keep the

SATA hard drive from data contamination. There are two main issues to deal with within

the project. The first is to achieve the high speed data transfer and bidirectional data

flow on the processor, required by USB 3.0 standards. The second is to correctly

perform blocking, which is the purpose of the project.

Acknowledgement

Electronic Crime Institute

Iowa State University

Problem statement

General problem statement

1. High- speed performance on the processor

2. Correct design of a command filter

General solution approach

1. In FPGA, we can simulate the CPU perform parallel computing by dividing the

core into multi-core parts. This is a demanding task in computer architecture. The

eventual performance of the block depends both on the CPU capability itself and

the architecture.

2. The filtering feature is realized in the circuit logic, which captures any data

modification commands and disables them. It is possible that the CPU is

configured to hold a processing unit to make input checking and output the result.

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System requirements

Operating environment and constraints

The device works between any USB 3.0 interface and a SATA hard drive.

Intended users and intended uses

Those who use a SATA hard drive (usually an external hard drive) on the computer that

supports USB 3.0 and want their hard drive data well protected

Assumptions and limitations

Initial assumptions list

1. The device is used for USB 2.0 or any other standards other than USB 3.0

2. The device is only used for SATA hard drive. No other HDD.

Initial limitations list

1. The device worked out in the project is only a prototype that may need external

power supply every time it is used.

2. The product of the project requires program loading every time.

3. The size of this prototype may not be sufficiently portable.

Expected end product and other deliverables

1. A logically development board with USB 3.0 interface

2. A daughter board that is open to SATA interface

3. A well-written hardware configuration program that performs all features of the

device

4. A test report of the product

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Use-case scenarios

The user interacts only with PC and he/she may perform any disk operation on the PC. It is

responsible for the write blocker to detect any invalid operation. The PC should be able to get

response from the USB port whenever a writing operation is denied.

System block diagram

PC

USB 3.0 USB write blocker SATA HDD

User

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Functional requirements

1. Data Bridge between USB 3.0 and SATA

This device acts as bridge for dataflow. It processes data transfer and controls

data package.

2. Lossless Data Transfer

Data transfer does not allow any information loss. The data transfer should not

be affected by the blocker except that no writing operation to hard drive is allowed.

3. A speed approximately at 300 MB/s

This is the USB 3.0 standard, under the constraint of SATA capability. The

highest speed of SATA is 300MB/s.

Non-functional requirements

1. Product Quality (Reliability)

The ability of a system or component to perform its required functions under

stated conditions for a specified period of time.

2. Portability

The ability for the device to be moved from point A to point B. The device may

easily be used on different computers and for different hard drives.

3. Maintainability

The product is maintainable which means the hardware configuration is well

documented and may be updated and improved for later on projects.

4. Testability

Tests are easily performed on the device. And these tests demonstrate the

capability of the final product.

5. Usability

Ease-of-use requirements address the factors that constitute the capacity of the

software to be understood, learned, and used by its intended users.

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Security considerations The main security issue for this product is to synchronize the data transfer between PC

and hard drive. That means the device is responsible to report every action to PC to let

the PC know what happened to the hard drive. If the device fails or misses the status

report, the PC may assume some operation is successful or not. In this case, hard drive

is no longer synchronized with PC, which causes failure of the device.

Safety considerations

The only safety consideration is that the device does no harm to the user’s hard drive.

This device never modifies the data on the user’s hard drive, nor the user’s PC.

Intellectual property The manufacturer of the development reserves its intellectual property. The design of the product has its Intellectual property belonged according to the policy of Iowa State University. Technology consideration The idea of the project design is develop prototype that resembles a current USB 2.0 write blocker. Higher speed and efficiency will be considered for USB 3.0 in this project. Market and literature There are quite a few products for USB 2.0 with similar functions around the market nowadays. For example, Taleau provides solutions for USB 2.0 to SATA bridge. ForensicPC has a series of Forensic write-block products.

But there is still no USB 3.0 blocker product in the market. In 2009, Fujitsu

Microelectronics shipped its first generation of USB 3.0-Serial SATA bridge IC.

MB86C30A incorporates USB and SATA signal communication control circuits, protocol

and command control circuits with a high-speed encryption/decryption engine on a

single device.

This product is close to the goal of this project. The concept of the design is to resemble

such a control circuit that incorporates USB 3.0 and SATA communication with a

command filter.

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Project Management

Work breakdown structure & Statement of Work To start the design of the processor, the first step is to determine what the processor is to do, by implementing the circuit logic in hardware language. Then using the feature of the development board, C program is used to perform a correct memory mapping for I/O. The next step is to design the circuit logic, which is filtering to process data from USB port. This is the core of the whole design. All the programs and codes are to be loaded into the memory on the board and they are also to be well documented for later testing purpose.

Write Blocker

Behavioral module

Device interface module

Data & documentation

module

VHDL hardware design

I/O mapping (C programming)

USB 3.0 data package receiver

Data banker (Memory)

Systematic testing

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Project Schedule

Resource management

Total Budget: $2000.00

Building Board

(HTG-V5-DDR3-PCIE-FX70T) $1695.00

Accessories

(HTG-COM-MDL) $495.00

Total cost estimated: $2190.00

Potential risks and mitigation

1. Schedule Risks

Development Board Choice is the first step of the project and is the crucial step. A

rational choice should be made considering the difficulty level of implementation and

reliability of the final product.

2. Technical Risks

11/18/2010 2/26/2011 6/6/2011 9/14/2011 12/23/2011

Study the software developmentplatform

Design the hardware

Starting writing code, Testing

Code documentation & Problemanalysis

Second system testing process

Design presented to client

Project status report

start date

completion

remaining

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The hardware configuration consists of module implementation and integration.

This is a complex procedure and it takes a long time to put a module into work.

3. Operational Risks

Improper operation on the device (especially during the testing process) may

cause irreversible hardware damage.

4. Financial Risks

Budget may not be sufficient for the whole project.

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Conclusion Referenced cited

Fujitsu Microelectronics America, Inc.

http://www.fujitsu.com/us/news/pr/fma_20090727.html

Project team contact infomation

Team members:

Yan Fang E E tears232@iastate.edu Chen Zhao CPR E czhao@iastate Elphas Sang E E eksang@iastate.edu

Client:

Electronic Crime Institute - Des Moies Area Community College

Project contact: Joe Lane jrlane@dmacc.edu

Advisor: Zhao Zhang zzhang@iastate.edu