Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference...

Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference is listed on each page, section, or graphic utilized.

A Review of Time Jitter and Digital Systems

Victor S. ReinhardtRaytheon Space and Airborne Systems

El Segundo California

Presented atThe 2005 Joint IEEE International Frequency Control

Symposium and Precise Time and Time Interval (PTTI) Systems and Applications Meeting(Paper to be Published in Proceedings)

The Hyatt Regency Hotel, Vancouver, Canada.August 29-31, 2005

A Review of Time Jitter and Digital Systems-Victor S. Reinhardt Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source

reference is listed on each page, section, or graphic utilized.

Introduction — Overview

• Time jitter is an important parameter for determining the performance of digital systems

• This paper will review the mechanics how time jitter impacts the performance of such systems

~ Agenda ~

• Introduction & overview

• A statistical framework for later discussions

• Discuss time jitter impact by category of digital system

• Conclusions-Summary

Note: This presentation has been updated based on audience comments



Categories of Digital Systems for Discussing Impact Time Jitter

• Categories somewhat overlap• Synchronous data transfer

– Common clock distributed along with data– Cancels most direct effects from clock oscillator– Gate timing jitter generates bit errors

• Asynchronous data transfer – Only data distributed & local clocks regenerated– Includes digital communications systems – Additional bit errors caused by relative

master-local clock oscillator (MO-LO) jitter

• Digital sampling– Analog signals are sampled & digitized or visa

versa– A/Ds & D/As: Sampling clock jitter generates

noise power– Communications systems decision circuits:

Sampling clock jitter causes bit error rate (BER) degradation

Dig Dig

Clock

Data

Dig Dig

Clock

Data

A/DDigital

Data

Clock

Analog

Digital sampling

Asynchronous

Synchronous

Voltage

PLLClock



Types of Degradation Caused by Time Jitter

• Hard bit errors– Direct bit errors without any other factors

involved– Data clock jitter moves clock edge out of

correct data transfer window

• Soft bit errors (BER degradation)– Increase in BER when thermal noise is

present (no errors when no thermal noise)– Occur in symbol (or bit) decision circuits

which turn an analog signal into digital symbol stream by sampling

– Clock jitter causes BER degradation by generating variations in sampled signal

• A/D & D/A noise power– Sampled voltage noise caused by time

jitter induced variations – This noise power decreases the effective

number of bits (ENOB) of A/Ds & D/As

Time Jitter Causes DataTransfer Errors

Data

Hard ErrorsData Window

Clock

Soft Errors & Noise Power

V

t

Time JitterCauses BER Degradation

& Generates

Noise Power

V

Clock



Defining Time Error in Digital Systems

• Two definitions of time error– Data transfer: Time error is between data

clock edges & data symbol centers– Digital sampling: Time error is between

sampling clock edges and correct analog epoch

• Time error broken into two components– Skew = average error

• Fixed plus long term and environmental changes

• Usually measured by an N-sample mean– Jitter = short term variation

• Specified as RMS, peak, or peak-to-peak relative to skew

• RMS usually interpreted as N-sample standard deviate

• Bit errors function of total error so jitter must reference skew

• Noise power caused by jitter alone so reference to skew not important (Skew important for sampling accuracy)

Jitter

Data

Clock

Data TransferSkew

JitterDigital Sampling

t

Total Time Error = Skew + Jitter

V(t)

Error

Error

Skew



A Statistical Frameworkfor Time Jitter & Digital Systems

Background for Statistical Approach Chosen

• Digital community has historically dealt with time jitter using stationary statistics– The standard variance generally used as the jitter measure– Bandwidth (BW) and non-stationary noise (1/f

n noise) issues often not explicitly dealt with

– Become important to treat BW & 1/fn issues explicitly because time jitter requirements now in ps & sub-ps regions

• Precise time community has historically dealt with BW & 1/f n issues

using 2nd difference measures of jitter– But these 2nd difference measures not easily connected to the skew

• The statistical framework presented here will attempt to meld both approaches– Will use the standard variance as jitter measure because it directly

references the skew– Will rigorously deal with BW and 1/f

n noise issues– Will show that the standard variance can be used with 1/f

n noisebecause of unique properties of digital systems



Definition of Two Associated Time Error Variables

• Clock reading (normalized phase) error

x(t) = (t)/ – Difference between subject and

reference clock readings at same time

– x(t) can be considered continuous variable--derived from (t)

– Will use x in presentation • Time (zero crossing) error

t(tn) = t’n – tn – x(tn)– Difference between subject and

reference clock edgesat same cycle or period count

– Is approximately the negative of x(tn)

• x(t) is the derivative of the fractional frequency error

y = f/fo = dx/dt = - d(t)/dt– x preferred because no minus sign

fo

Freq Source Cycle Counter

Basic Clock ClockReading= Cycles

in 1/fo units

x

t

t

t’n

RefClock

Reading

Subject ClockReading

t

tn

V(t) = A(t)F(t+ (t))

Vref(t) = AoF(t)

ref = 0 By DefinitionF(.) = Periodic Function



• Jitter measure will be N-sampleunbiased standard variance

– Ensemble average of the arithmetic mean of N squared1st differences between xn and skew Mx(N)

– Has well known convergence problems for 1/f3 noise– Will show is mitigated in digital systems by hs(t)

• N samples xn spaced by interval

• xn derived from convolution of continuous x(t) with explicit system phase response function hs(t)

– Explicit use of hs(t) will be important

• Skew = N-sample arithmetic mean

Discrete Samples xn and Jitter Measure

N

1n

2xn

2xd )Mx(

1N

1)N,(

N

1nn

1x xN)N(M

SystemResponse

Phasehs(t)

Contin-uous

x(t) = (t)/

N DiscreteSamples

xn Spaced

by

)tn(h)t(x dtx sn

<…> =EnsembleAverage



Closest 2nd Difference Variance For Comparison

• Ensemble average of arithmetic mean of N squared 2nd differences of xn’s

• More familiarly written in terms of N-sample fractional frequency Allan variance 2

y(N,,) *

• Well behaved for 1/f3 noise• But eliminates direct reference to skew Mx(N)

N

1n

21N

n1n2xa N

xxxx

)1N(4

1)N,(

),,N(25.0)My(1N

25.0)N,( 2

y2

N

1n

2yn

22xa

)xx(y 1nn1

n

N

1nn

1y yNM

* See: B. E. Blair, Ed, Time and Frequency Fundamentals, NBS Monograph 140, U. S. Govt. Printing office, 1974 (CODEN:NBSMA6), p 166.



• Kernel Kx(f) = Kxd(f) or Kxa(f) Describes the variance– Why a kernel? Kx(f) for N samples

cannot be represented by the square of a single response function

• Sx(f) = Double-sideband (DSB) power spectral density (PSD) of x(t) Describes the noise– Lx(f) = ½Sx(f) = SSB PSD

• Hs(f) = DSB Fourier transform of hs(t) Describes the system– System assumed linear in phase– Hs(f) can contain high & low

frequency BW cut-offs

Spectral Integral of Variances 2

xd(,N) & 2xa(,N)

df)f(K|)f(H|)f(S0

x2

sx2x

System

Response|Hs(f)|2

System Properties

VarianceKernelKx(f)

Variance Properties

Sx(f) x2

Frequency from Carrier f

Sx(f) (double sideband PSD)

IntegrationRegion

|Hs(f)|2Kx(f)Hs(f) can have LF cut-off



Kernels of 2xd(,N) & 2

xa(,N)

• Standard Variance 2xd(,N)

– For Nf << 1: Kxd(f) f2

– Converges for Sx(f) = 1/f0 … 1/f2

– Also converges for 1/f3 & 1/f4 if Hs(f) contains appropriate highpass filter

• 2nd Difference Variance 2xa(,N)

– For Nf << 1: Kxa(f) f4

– 2xa converges for Sx(f) = 1/f0… 1/f4

)f(sinN

)fN(sin1)f(sin

1N

N)f(K

22

22

xa

)f(sin

)fN(sin

N

11

1N

N)f(K

2

2

2xd

-70-60-50-40-30-20-10

010

-6 -5 -4 -3 -2 -1 0 1Log(f)

dB

Kxd

Kxa

(N=100)

f = 1/N

Kxd & Kxa vs f

f4

f2

f2



Properties of 2xd(,N) as N

• When N Kxd 1

and 2xd(,N) Single point standard variance 2

x-std

– Again 2x-std can exist for 1/fn noise because of |Hs(f)|2

– When there are mathematical difficulties with 2x-std

can fall back on 2xd(N) with large but finite N

• |Hs(f)|2 often approximated by square bandpass filter

– Then

– fl = low frequency cut-off – fh = high frequency cut-off

h

l

f

fx

2bpassx

2stdx )f(S df

0

x2

s2

nn2

stdx2xd )f(S|)f(H|df )xx( )N,(



Impact of Time Jitter on Digital Systems by Category

• Will use framework just presented to discuss impact by category

– Synchronous data transfer systems

– Asynchronous data transfer systems

– Digital sampling systems

• Will show that 2xd(, N) & 2

x-std can be used because of properties of these systems



Time jitter & Synchronous Systems

• Common clock oscillator distributed to all units– Cancels most direct clock oscillator effects – There is some residual high pass filtered oscillator noise

due to time misalignment between clocks• Hs(f) = 4sin2(m) f2 for fm << 1

• Both gate and residual oscillator noise can be modeled by white plus 1/f noise terms

Sx(f) = g0(1 + fk/f)– fk = 1/f or flicker knee freq where 1/f noise PSD = white noise PSD

• Hs(f) can be approximated by square lowpass filter – fl = 0 – fh = fg = gate noise bandwidth

• Note fh is not equal to fo the clock frequency but fg

• Usually fg >> fo so aliasing of white noise is a major issue

Common Clock OscillatorFrequency = fo

Gate Noise BW = fg

DigitalSubsystem

Common Clock

DataDigital

Subsystem

Delay m



Aliasing of White Noise in Digital Systems

• Aliasing occurs because discrete digital system is equivalent to system sampled at fo

– Logic sees noise frequencies up to fh = fg (and fg >> fo)

– The sampling aliases the original Sx(f) over BW fg into BW fo

– This aliasing multiplies white Sx(f) by factor of fg/fo

• Aliasing can also impact counter measurementsbecause of large counter fh compared with fo

– Counter fh may be much higher than gate BW fg

Sx(f) Sx multiplied by (fg/fo) due to aliasing

Original Sx(f)

fgfo 2fo 3fo. . . .

Freq from carrier

Sampled noisehas same in BW fo

Analog noise

nT0To 2To 3To. . .

Clock Cycles



For Synchronous Systems1/f Effects are Negligible

• For Sx(f) = g0(1 + fk/f) can calculate 2xd(, N)

• Time Tk = N where 1/f noise term = white noise term given by

• For all logic types Tk >>> Life of universe

and 1/f noise can be ignored for all practical N values

• Thus for synchronous systems need use only white noise component of Sx(f)

g

f/f

k f

eNT

kg

oggok2xd gf)fNln(gf)N,( [N >>1]

og2

stdx2xd gf)N,(



Time Jitter & Asynchronous Systems(Shown as Communications System)

• Data sent between units without clock *– Clock recovery phase locked loop (PLL) regenerates clock & tracks Rx

clock LO to Tx clock MO– Because of this there is additional MO-LO clock oscillator jitter

• System response has two components– Clock recovery PLL response Hp(f)--provides low frequency cut-off at

loop BW Bp

– Tx-Rx link response Hh(f)--provides high frequency cut-off • fh Rs/2 (Rs = Symbol rate) for communications systems

• Also other asynchronous systems such as RS-422– fh less easily specified (Worst case fh = fg)

TxFilter

ModulatedData

Clock Recovery PLLHp(f)Loop BW = Bp

Clock Master Osc (MO)

TxDigital

Mod-ulator

Transmitter

RxFilter

RxDigital

De-Mod

Link Response Hh(f)

* See: Victor S. Reinhardt, The Calculation of Frequency Source Requirements for Digital Communications Systems, Proceedings of the IEEE International Frequency Control Symposium 50th Anniversary Joint Conference, 24-27 August, 2004, Montréal, Canada. Slides at http://www.ieee-uffc.org/freqcontrol/Reinhardt_files/frame.htm

Clock Local Osc (LO)

Receiver

Deci-sion



• Sx(f) = sum of PSD’s of all oscillatorsin Tx-Rx link

• Hp(f) = clock recovery PLL response function

• Hh(f) = DSB complex envelope response function of Tx-Rx link

• |1 – Hp(f)|2 provides LF cut-off at PLL loop BW Bp

– 2nd PLL will cancel 1/f3 noise completely

– 1st order PLL will leave residual 1/ffor 1/f3 Sx(f)

• But has negligible effect on 2xd (,N)

(See synchronous systems)

• However susceptible to cycle slipping

• |Hh(f)|2 provides high freq cut-off fh

Standard Variance for MO-LO Jitter

h

p

f

Bx

0

2h

2px

2stdx df)f(Sdf|)f(H||)f(H1|)f(S

Sx(f) (Sum of all Clocks )

Frequency from Carrier f

fh

|1-Hp(f)|2|Hh(f)|2

fl = Bp

Variance Integration

Region

f4 for2nd

Order PLLs



Time Jitter & Digital Sampling

• Time jitter generates random variations in sampled voltage

• In communications systems decision circuits– Random voltage variations interact with thermal variations

to produce BER degradation

– BER degradation is derived using a Gaussian xn with 2x-std

from asynchronous transfer

– Time jitter requirements approach 1 ps at > GHz symbol rates

-12-11-10

-9-8-7-6-5

30 40 50 60 70 80 90Symbol Rate - dBHz

Jitt

er -

lo

g(s

ec)

RMS Jitter Reqs for QPSK @ 0.1 dB BER Deg

TimeJitter

GeneratesRandom

Variationsin

SampledVoltage

V(t)

t

Timing Skew

1-bit

0-bit

Time Jitter & Digital Sampling



• Noise power consists of random variations in sampled voltage generated by slope modulation of signal

• For sinewave signal *

SNRjitter-1 2 = s

2 x-std2 = V

2/Ps

– fh = fg unless otherwise restricted

– Note SNRjitter is independent ofnumber of digitized bits

– Means SNRjitter reqs more severe asnumber of bits increases

• Can convert SNRjitter to an ENOB by

– By equating SNRjitter to quant error SNR

– And assuming a given signal power level

• Voltage PSD for white-x noise

SV(f) (fh/fo) s2goPs (x-std

2 = fhgo)

In A/Ds & D/As Time JitterGenerates Noise Power

* see: Analog Devices, Mixed-Signal and DSP Design Techniques, Section 2, Sampled Data Systems, http://www.analog.com/Analog_Root/static/pdf/dataConverters/MixedSignal_Sect2.pdf, p35

Near Zero: = sx = V/As = 2fs =SW Ang freq

-Ps = SW power = A2/2

- fo = Sampling clock freq

Sinewave (SW) SignalV(t) = A sin(st+ )

TimeJitter

NoisePower V

2A

x

PhaseJitter



• ENOBtot values generated from *– Signal level @ 10 dB back-off (BO)

from full scale (FS)• Typical BO for complex signals

– SNRtot = 2SNRjitter = SNRquant

• Assumes SNRjitter = SNRquant

• Is major limiting issue for high speed A/Ds and D/As

ENOB Limits from Time Jitter Generate Stringent Requirements

* Differs from ENOB defined inother sources which use fullscale signal level– 10 dB BO more realistic

(& conservative)

20

40

60

80

100

120

6 7 8 9 10

Log10(SW Freq – Hz)

SN

Rto

t-d

B -

dB

1 ns

0.1 ns

10 ps

1 ps

0.1 ps

Time

Jitter

EN

OB

tot f

or

10 d

B B

O

86

1012141618

20

Jitter 1 ps 0.1 psENOB

totSW Freq

MHzSW Freq

MHz16 4 4412 71 70910 284 28388 1135 11351



Noise Power & Non-White noise

• For non-white noise the appropriate 2xd(,N) & 2

x-std can be generated as follows

• Synchronous sampling system– Sampling clock derived directly from the analog signal clock– See 2

x-std from synchronous data transfer

• Asynchronous sampling system– Sampling clock locked to analog signal clock though PLL (or equivalent)– For MO-LO jitter see 2

x-std from asynchronous data transfer

– For gate jitter see 2x-std from synchronous data transfer

– Total variance is sum of the above

• Unsynchronized sampling system– Independent sampling and signal clocks– For up to 1/f2 noise can use 2

xd(,N) – There will be divergence and accuracy issues from 1/f3 noise unless there

is calibration in system that has implicit low frequency cut-off



Conclusions--Summary

• Should explicitly use system response hs(t) so standard variances 2

xd(,N) & 2x-std can be used with 1/fn noise

• For synchronous transfer need only use white noise component of Sx(f) for 2

xd(,N) & 2x-std

– Common clock cancels out oscillator 1/f2 and 1/f3 noise

– 1/f noise term negligible compared with white noise term

– Aliasing significantly increases white noise PSD

– Time jitter causes hard errors

• For asynchronous transfer there is an additional MO-LO jitter term– Has oscillator 1/f2 and 1/f3 noise components

– PLL loop BW provides LF cut-off so 2xd(,N) & 2

x-std exists

– Time jitter also causes BER degradation (soft errors)

• Noise power in digital sampling (A/Ds & D/As)– Limits effective number of bits (ENOB)

– Clock jitter is critical limitation on high speed A/D & D/A performance

Copyright 2005 Victor S. Reinhardt--Rights to copy material is granted so long as a source reference...

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