CoolSET -F3R (Jitter Version)

CoolSET®-F3R

(Ji t ter Vers ion)

ICE3B0365J

ICE3B0565J

ICE3B1565J

ICE3B2065J

Off-Line SMPS Current ModeContro l ler with integrated 650VCoolMOS® and Startup cel l( f requency j i t ter Mode) in DIP-8

N e v e r s t o p t h i n k i n g .

Power Management & Supp ly

Datasheet , Vers ion 2.7, 9 May 2012

Edition 2012-5-09

Published byInfineon Technologies AG,81726 Munich, Germany,© 2012 Infineon Technologies AG.All Rights Reserved.

Legal disclaimer

The information given in this document shall in no event be regarded as a guarantee of conditions orcharacteristics. With respect to any examples or hints given herein, any typical values stated herein and/or anyinformation regarding the application of the device, Infineon Technologies hereby disclaims any and all warrantiesand liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rightsof any third party.

Information

For further information on technology, delivery terms and conditions and prices, please contact your nearestInfineon Technologies Office (www.infineon.com).

Warnings

Due to technical requirements, components may contain dangerous substances. For information on the types inquestion, please contact your nearest Infineon Technologies Office.

Infineon Technologies Components may be used in life-support devices or systems only with the express writtenapproval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failureof that life-support device or system or to affect the safety or effectiveness of that device or system. Life supportdevices or systems are intended to be implanted in the human body or to support and/or maintain and sustainand/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons maybe endangered.

For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany orthe Infineon Technologies Companies and Representatives worldwide: see our webpage at http://www.infineon.com

CoolMOS®, CoolSET® are trademarks of Infineon Technologies AG.

CoolSET®-F3RICE3Bxx65JRevision History: 2012-5-09 Datasheet Version 2.7

Previous Version: 2.6

Page Subjects (major changes since last revision)

23 Revised typo in outline dimension

Type Package Marking VDS FOSC RDSon1)

1) typ @ T=25°C

230VAC ±15%2)

2) Calculated maximum input power rating at Ta=75°C, Tj=125°C and without copper area as heat sink

85-265 VAC2)

ICE3B0365J PG-DIP-8 ICE3B0365J 650V 67kHz 6.45W 22W 10W



ICE3BR2065J PG-DIP-8 ICE3B2065J 650V 67kHz 0.92W 57W 28W

Version 2.7 3 9 May 2012

CoolSET®-F3RICE3Bxx65J

Off-Line SMPS Current Mode Controller withintegrated 650V CoolMOS® and Startup cell(frequency jitter Mode) in DIP-8

PG-DIP-8

Product Highlights

• Active Burst Mode to reach the lowest Standby PowerRequirements < 100mW

• Adjustable Blanking Window for High Load Jumps toincrease Reliability

• Frequency Jittering for Low EMI• Pb-free lead plating, RoHS compilantFeatures• 650V Avalanche Rugged CoolMOS® with built in

switchable Startup Cell• Active Burst Mode for lowest Standby Power

@ light load controlled by Feedback Signal• Fast Load Jump Response in Active Burst Mode• 67 kHz fixed Switching Frequency• Auto Restart Mode for Over temperature

Detection• Auto Restart Mode for Overvoltage Detection• Auto Restart Mode for Overload and Open Loop• Auto Restart Mode for VCC Undervoltage• User defined Soft Start• Minimum of external Components required• Max Duty Cycle 75%• Overall Tolerance of Current Limiting < ±5%• Internal Leading Edge Blanking• BiCMOS technology provides wide VCC Range• Frequency Jittering for Low EMI

DescriptionThe CoolSET®-F3(Jitter version) meets the requirementsfor Off-Line Battery Adapters and low cost SMPS for thelower power range. By use of a BiCMOS technology a wideVCC range up to 26V is provided. This covers the changesin the auxiliary supply voltage if a CV/CC regulation isimplemented on the secondary side. Furthermore an ActiveBurst Mode is integrated to fullfill the lowest Standby PowerRequirements <100mW at no load and Vin = 270VAC. Asduring Active Burst Mode the controller is always activethere is an immediate response on load jumps possiblewithout any black out in the SMPS. In Active Burst Modethe ripple of the output voltage can be reduced <1%.Furthermore Auto Restart Mode is entered in case ofOvertemperature, VCC Overvoltage, Output Open loop orOverload and VCC Undervoltage. By means of the internalprecise peak current limitation, the dimension of thetransformer and the secondary diode can be lowered whichleads to more cost efficiency.

CSoftS

CVCC

CBulk

ConverterDC Output

+

Snubber

Power Management

PWM ControllerCurrent Mode

85 ... 270 VAC

Typical Application

RSense

SoftS

FB

GNDActive Burst Mode

Auto Restart Mode

ControlUnit

-

CS

VCC

Startup Cell

Precise Low Tolerance PeakCurrent Limitation

Drain

CoolSET™ -F3(Jitter Version)

Depl. CoolMOS™


Table of Contents Page


1 Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51.1 Pin Configuration with PG-DIP-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51.2 Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

2 Representative Blockdiagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73.2 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73.3 Startup Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83.4 PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93.4.1 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93.4.2 PWM-Latch FF1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93.4.3 Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

3.5 Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103.5.1 Leading Edge Blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103.5.2 Propagation Delay Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103.6 Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113.6.1 Adjustable Blanking Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113.6.2 Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123.6.2.1 Entering Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123.6.2.2 Working in Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123.6.2.3 Leaving Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123.6.3 Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133.6.3.1 Auto Restart Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164.3 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164.3.1 Supply Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164.3.2 Internal Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

4.3.3 PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174.3.4 Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174.3.5 Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184.3.6 CoolMOS® Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

5 Temperature derating curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

6 Outline Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

7 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

8 Schematic for recommended PCB layout . . . . . . . . . . . . . . . . . . . . . . . .26



1 Pin Configuration and Functionality1.1 Pin Configuration with PG-DIP-8

Figure 1 Pin Configuration PG-DIP-8(top view)

Note: Pin 4 and 5 are shorted within the DIPpackage.

1.2 Pin Functionality

SoftS (Soft Start, Auto Restart & FrequencyJittering Control)

The SoftS pin combines the function of Soft Startduring Start Up and error detection for Auto RestartMode. These functions are implemented and can beadjusted by means of an external capacitor at SoftS toground. This capacitor also provides an adjustableblanking window for high load jumps, before the ICenters into Auto Restart Mode. Furthermore this pin isalso used to control the period of frequency jitteringduring normal load.

FB (Feedback)

The information about the regulation is provided by theFB Pin to the internal Protection Unit and to the internalPWM-Comparator to control the duty cycle. The FB-Signal controls in case of light load the Active BurstMode of the controller.

CS (Current Sense)

The Current Sense pin senses the voltage developedon the series resistor inserted in the source of theintegrated CoolMOS®. If CS reaches the internalthreshold of the Current Limit Comparator, the Driveroutput is immediately switched off. Furthermore thecurrent information is provided for the PWM-Comparator to realize the Current Mode.

Drain (Drain of integrated CoolMOS®)

Pin Drain is the connection to the Drain of the internalCoolMOSTM.

VCC (Power supply)

The VCC pin is the positive supply of the IC. Theoperating range is between 10.3V and 26V.

GND (Ground)

The GND pin is the ground of the controller.

Pin Symbol Function

1 SoftS Soft-Start

2 FB Feedback

3 CS Current Sense/

650V1) CoolMOS® Source

4 Drain 650V1) CoolMOS® Drain

1) at Tj = 110°C

5 Drain 650V1) CoolMOS® Drain

6 N.C. Not Connected

7 VCC Controller Supply Voltage

8 GND Controller Ground

Package PG-DIP-8

1

6

7

8

4

3

2

5

GNDSoftS

FB

CS

VCC

N.C

Drain Drain



2 Representative Blockdiagram

Figure 2 Representative Blockdiagram



3 Functional DescriptionAll values which are used in the functional descriptionare typical values. For calculating the worst cases themin/max values which can be found in section 4Electrical Characteristics have to be considered.

3.1 Introduction

CoolSET®-F3 Jitter version is the further developmentof the CoolSET®-F2 to meet the requirements for thelowest Standby Power at minimum load and no loadconditions. A new fully integrated Standby Powerconcept is implemented into the IC in order to keep theapplication design easy. Compared to CoolSET®-F2 nofurther external parts are needed to achieve the lowestStandby Power. An intelligent Active Burst Mode isused for this Standby Mode. After entering this modethere is still a full control of the power conversion by thesecondary side via the same optocoupler that is usedfor the normal PWM control. The response on loadjumps is optimized. The voltage ripple on Vout isminimized. Vout is further on well controlled in thismode.

The usually external connected RC-filter in thefeedback line after the optocoupler is integrated in theIC to reduce the external part count.

Furthermore a high voltage Startup Cell is integratedinto the IC which is switched off once the UndervoltageLockout on-threshold of 18V is exceeded. This StartupCell is part of the integrated CoolMOS®. The externalstartup resistor is no longer necessary as this StartupCell is connected to the Drain. Power losses aretherefore reduced. This increases the efficiency underlight load conditions drastically.

The Soft-Start capacitor is also used for providing anadjustable blanking window for high load jumps. Duringthis time window the overload detection is disabled.With this concept no further external components arenecessary to adjust the blanking window.

An Auto Restart Mode is implemented in the IC toreduce the average power conversion in the event ofmalfunction or unsafe operating condition in the SMPSsystem. This feature increases the system’srobustness and safety which would otherwise lead to adestruction of the SMPS. Once the malfunction isremoved, normal operation is automatically initiatedafter the next Start Up Phase.

The internal precise peak current limitation reduces thecosts for the transformer and the secondary diode. Theinfluence of the change in the input voltage on thepower limitation can be avoided together with theintegrated Propagation Delay Compensation.Therefore the maximum power is nearly independenton the input voltage which is required for wide rangeSMPS. There is no need for an extra over-sizing of theSMPS, e.g. the transformer or the secondary diode.

3.2 Power Management

Figure 3 Power Management

The Undervoltage Lockout monitors the externalsupply voltage VVCC. When the SMPS is plugged to themain line the internal Startup Cell is biased and startsto charge the external capacitor CVCC which isconnected to the VCC pin. The VCC charge currentthat is provided by the Startup Cell from the Drain pin is1.05mA. When VVCC exceeds the on-thresholdVCCon=18V, bias circuit is switched on. Then theStartup Cell is switched off by the UndervoltageLockout and therefore no power losses present due tothe connection of the Startup Cell to the Drain voltage.To avoid uncontrolled ringing at switch-on a hysteresisis implemented. The switch-off of the controller canonly take place after active mode was entered andVVCC falls below 10.3V.

The maximum current consumption before thecontroller is activated is about 300uA.

Internal Bias

VoltageReference

Power Management

5V

VCC

Undervoltage Lockout

18V

10.3

T1

Power-Down Reset

SoftS

Active BurstMode

Auto RestartMode

Startup Cell

Drain



When VVCC falls below the off-threshold VCCoff=10.3Vthe bias circuit is switched off and the Power Downreset let T1 discharging the soft-start capacitor CSoftS atpin SoftS. Thus it is ensured that at every startup cyclethe voltage ramp at pin SoftS starts at zero.

The bias circuit is switched off if Auto Restart Mode isentered. The current consumption is then reduced to300uA.

Once the malfunction condition is removed, this blockwill then turn back on. The recovery from Auto RestartMode does not require disconnecting the SMPS fromthe AC line.

When Active Burst Mode is entered, some internal Biasis switched off in order to reduce the currentconsumption to about 500uA while keeping acomparator (which trigger if VFB has exceeded 3.61V)and the Soft Start capacitor clamped at 3.0 V as this isnecessary in this mode.

3.3 Startup Phase

Figure 4 Soft Start

At the beginning of the Startup Phase, the IC providesa Soft Start duration whereby it controls the maximumprimary current by means of a duty cycle limitation. Acapacitor CSofts in combination with the internal pull up

resistor RSoftS determines the duty cycle until VSoftS

exceeds 3.1V.

When the Soft Start begins, CSoftS is immediatelycharged up to approx. 0.8V by T2. Therefore the SoftStart Phase takes place between 0.8V and 3.1V.Above VSoftsS = 3.1V there is no longer duty cyclelimitation DCmax which is controlled by comparator C7since comparator C2 blocks the gate G7 (see Figure5).This maximum charge current in the very first stagewhen VSoftS is below 0.8V, is limited to 0.9mA.

Figure 5 Startup Phase

By means of this extra charge stage, there is no delayin the beginning of the Startup Phase when there is stillno switching. Furthermore Soft Start is finished at 3.1Vto have faster the maximum power capability. The dutycycles DC1 and DC2 are depending on the mains andthe primary inductance of the transformer. Thelimitation of the primary current by DC2 is related toVSoftS = 3.1V. But DC1 is related to a maximum primarycurrent which is limited by the internal Current Limitingwith CS = 1V. Therefore the maximum Startup Phaseis divided into a Soft Start Phase until t1 and a phasefrom t1 until t2 where maximum power is provided ifdemanded by the FB signal.

Soft-StartComparator

Soft Start

&

G7

C7

CSoftS

RSoftS

T2

3.25k5V

T3

0.8VSoftS

Gate Driver

0.6V

x3.2

PWM OP

CS

3.1V

C2

Freq JitterChargingcurrent I

FJ

Freq JitterDischargingcurrent I

FJFreq Jitter

Control

DCmax

DC1

DC2

t

t

VSoftS

max. Soft Start Phase

0.8V

3.1V

4.0V

max. Startup Phase

t1 t2



3.4 PWM Section

Figure 6 PWM Section

3.4.1 Oscillator and Jittering

The oscillator generates a fixed frequency withfrequency jittering of ±4% from the fixed frequency(which is ±2.7kHz from 67kHz) at a jittering period TFJ.The switching frequency is fswitch = 67kHz.

A resistor, a capacitor and a current source and currentsink which determine the frequency are integrated. Thecharging and discharging current of the implementedoscillator capacitor are internally trimmed, in order toachieve a very accurate switching frequency. The ratioof controlled charge to discharge current is adjusted toreach a maximum duty cycle limitation of Dmax=0.75.

Once the Soft Start period is over and when the IC goesinto normal mode, the Soft Start capacitor will becharged and discharged through internal currentsource, IFJ to generate a triangular waveform with ajittering period TFJ which is externally adjustable by theSoft Start capacitor, CSoftS (See Figure 4).

TFJ = kFJ * CSoftS

where kFJ is a constant = 4 ms/uF

eg. TFJ = 4 ms if CSoftS = 1uF

3.4.2 PWM-Latch FF1

The oscillator clock output provides a set pulse to thePWM-Latch when initiating the internal CoolMOS®

conduction. After setting the PWM-Latch can be resetby the PWM comparator, the Soft Start comparator orthe Current-Limit comparator. In case of resetting thedriver is shut down immediately.

3.4.3 Gate Driver

The Gate Driver is a fast totem pole gate drive which isdesigned to avoid cross conduction currents.

The Gate Driver is active low at voltages below theundervoltage lockout threshold VVCCoff.

Figure 7 Gate Driver

Oscillator

DutyCyclemax

Gate Driver

0.75

Clock

&

G9

1

G8

PWM Section

FF1

R

S

Q

Gate

Soft StartComparator

PWMComparator

CurrentLimiting

FrequencyJitter

SoftS

VCC

1

PWM-Latch

Depl. CoolMOS™

Gate Driver

Gate



3.5 Current Limiting

Figure 8 Current Limiting

There is a cycle by cycle Current Limiting realized bythe Current-Limit comparator C10 to provide anovercurrent detection. The source current of theintegrated CoolMOS® is sensed via an external senseresistor RSense . By means of RSense the source currentis transformed to a sense voltage VSense which is fedinto the pin CS. If the voltage VSense exceeds theinternal threshold voltage Vcsth the comparator C10immediately turns off the gate drive by resetting thePWM Latch FF1. A Propagation Delay Compensationis added to support the immediate shut down withoutdelay of the integrated internal CoolMOS® in case ofCurrent Limiting. The influence of the AC input voltageon the maximum output power can thereby be avoided.

To prevent the Current Limiting from distortions causedby leading edge spikes a Leading Edge Blanking isintegrated in the current sense path for thecomparators C10, C12 and the PWM-OP.

The output of comparator C12 is activated by the GateG10 if Active Burst Mode is entered. Once activated thecurrent limiting is thereby reduced to 0.32V. Thisvoltage level determines the power level when theActive Burst Mode is left if there is a higher powerdemand.

3.5.1 Leading Edge Blanking

Figure 9 Leading Edge Blanking

Each time when the integrated internal CoolMOS® isswitched on a leading edge spike is generated due tothe primary-side capacitances and secondary-siderectifier reverse recovery time. This spike can causethe gate drive to switch off unintentionally. To avoid apremature termination of the switching pulse, this spikeis blanked out with a time constant of tLEB = 220ns.During this time, the gate drive will not be switched off.

3.5.2 Propagation Delay Compensation

In case of overcurrent detection, the switch-off of theintegrated internal CoolMOS® is delayed due to thepropagation delay of the circuit. This delay causes anovershoot of the peak current Ipeak which depends onthe ratio of dI/dt of the peak current (see Figure 10).

Figure 10 Current Limiting

The overshoot of Signal2 is bigger than of Signal1 dueto the steeper rising waveform. This change in theslope is depending on the AC input voltage.Propagation Delay Compensation is integrated to limitthe overshoot dependency on dI/dt of the rising primarycurrent. That means the propagation delay timebetween exceeding the current sense threshold Vcsth

and the switch off of the integrated inernal CoolMOS®

is compensated over temperature within a wide range.

Current Limiting

C10

C12

&

0.32VG10

Propagation-DelayCompensation

Vcsth

Active BurstMode

PWM LatchFF1

10k

D1

1pF

PWM-OP

CS

LeadingEdge

Blanking220ns

t

VSense

Vcsth

tLEB = 220ns

t

ISense

ILimit

tPropagation Delay

IOvershoot1

Ipeak1

Signal1Signal2

IOvershoot2Ipeak2



Current Limiting is now possible in a very accurate way.

E.g. Ipeak = 0.5A with RSense = 2. Without PropagationDelay Compensation the current sense threshold is setto a static voltage level Vcsth=1V. A current ramp ofdI/dt = 0.4A/µs, that means dVSense/dt = 0.8V/µs, and apropagation delay time of i.e. tPropagation Delay =180nsleads then to an Ipeak overshoot of 14.4%. By means ofpropagation delay compensation the overshoot is onlyabout 2% (see Figure 11).

Figure 11 Overcurrent Shutdown

The Propagation Delay Compensation is realized bymeans of a dynamic threshold voltage Vcsth (see Figure12). In case of a steeper slope the switch off of thedriver is earlier to compensate the delay.

Figure 12 Dynamic Voltage Threshold Vcsth

3.6 Control Unit

The Control Unit contains the functions for Active BurstMode and Auto Restart Mode. The Active Burst Modeand the Auto Restart Mode are combined with anAdjustable Blanking Window which is depending on theexternal Soft Start capacitor. By means of thisAdjustable Blanking Window, the IC avoids enteringinto these two modes accidentally. Furthermore it alsoprovides a certain time whereby the overload detectionis delayed. This delay is useful for applications whichnormally works with a low current and occasionallyrequire a short duration of high current.

3.6.1 Adjustable Blanking Window

Figure 13 Adjustable Blanking Window

VSoftS swings between 3.2V and 3.6V after the SMPS issettled and S2 is on while S3 is off, this is due to thefrequency jittering function that is making use of theSoft Start pin. If overload occurs VFB is exceeding 4.5V.Auto Restart Mode can’t be entered as the gate G5 isstill blocked by the comparator C3. But after VFB has

0,9

0,95

1

1,05

1,1

1,15

1,2

1,25

1,3

0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2

with compensation without compensation

dt

dVSense s

V

Sen

seV

V

t

Vcsth

VOSC

Signal1 Signal2

VSense Propagation Delay

max. Duty Cycle

off time

t

C3

4.0V

C4

4.5V

C5

1.35V

&

G5

&

G6

3.0V

S1

Control Unit

ActiveBurstMode

AutoRestartMode

RSoftS

5VSoftS

FB

FrequencyJitterS2

S3



exceeded 4.5V the switch S2 is opened and S3 isclosed. The external Soft Start capacitor can now becharged further by the integrated pull up resistor RSoftS

via switch S3. The comparator C3 releases the gatesG5 and G6 once VSofts has exceeded 4.0V. Thereforethere is no entering of Auto Restart Mode possibleduring this charging time of the external capacitorCSoftS. The same procedure happens to the externalSoft Start capacitor if a low load condition is detectedby comparator C5 when VFB is falling below 1.35V.Only after VSoftS has exceeded 4.0V and VFB is stillbelow 1.35V Active Burst Mode is entered.

3.6.2 Active Burst Mode

The controller provides Active Burst Mode for low loadconditions at VOUT. Active Burst Mode increasessignificantly the efficiency at light load conditions whilesupporting a low ripple on VOUT and fast response onload jumps. During Active Burst Mode which iscontrolled only by the FB signal the IC is always activeand can therefore immediately response on fastchanges at the FB signal. The Startup Cell is keptswitched off to avoid increased power losses for theself supply.

Figure 14 Active Burst Mode

The Active Burst Mode is located in the Control Unit.Figure 14 shows the related components.

3.6.2.1 Entering Active Burst Mode

The FB signal is always observed by the comparatorC5 if the voltage level falls below 1.35V. In that case theswitch S1 and S2 is released which allows thecapacitor CSoftS to be charged via S3 starting from theswinging voltage level between 3.2V and 3.6V innormal operating mode. If VSoftS exceeds 4.0V thecomparator C3 releases the gate G6 to enter the ActiveBurst Mode. The time window that is generated bycombining the FB and SoftS signals with gate G6avoids a sudden entering of the Active Burst Mode dueto large load jumps. This time window can be adjustedby the external capacitor CSoftS.

After entering Active Burst Mode a burst flag is set andthe internal bias is switched off in order to reduce thecurrent consumption of the IC down to approx. 500uA.Also, switch S1 is closed to clamped the Soft Startvoltage to 3.0V. In this Off State Phase the IC is nolonger self supplied so that therefore CVCC has toprovide the VCC current (see Figure 15). Furthermoregate G11 is then released to start the next burst cycleonce VFB has 3.0V exceeded.

It has to be ensured by the application that the VCCremains above the Undervoltage Lockout Level of10.3V to avoid that the Startup Cell is accidentallyswitched on. Otherwise power losses are significantlyincreased. The minimum VCC level during Active BurstMode is depending on the load conditions and theapplication. The lowest VCC level is reached at no loadconditions at VOUT.

3.6.2.2 Working in Active Burst Mode

After entering the Active Burst Mode the FB voltagerises as VOUT starts to decrease due to the inactivePWM section. Comparator C6a observes the FB signalif the voltage level 3.61V is exceeded. In that case theinternal circuit is again activated by the internal Bias tostart with switching. As now in Active Burst Mode thegate G10 is released the current limit is only 0.32V toreduce the conduction losses and to avoid audiblenoise. If the load at VOUT is still below the starting levelfor the Active Burst Mode the FB signal decreasesdown to 3.0V. At this level C6b deactivates again theinternal circuit by switching off the internal Bias. Thegate G11 is released as after entering Active BurstMode the burst flag is set. If working in Active BurstMode the FB voltage is changing like a saw toothbetween 3.0V and 3.61V (see figure 15).

3.6.2.3 Leaving Active Burst Mode

The FB voltage immediately increases if there is a highload jump. This is observed by comparator C4. As thecurrent limit is ca. 32% during Active Burst Mode acertain load jump is needed that FB can exceed 4.5V.At this time C4 resets the Active Burst Mode which also

C3

4.0V

C4

4.5V

C6a

3.61V

C5

1.35V

FB

Control Unit

ActiveBurstMode

3.0V

S1 Internal Bias

RSoftS

5V

SoftS

&

G10

CurrentLimiting

&

G6

C6b

3.0V

&G11

FrequencyJitter

S2

S3



blocks C12 by the gate G10. Maximum current can nowbe provided to stabilize VOUT.

Figure 15 Signals in Active Burst Mode

3.6.3 Protection Modes

The IC provides several protection features thatincrease the SMPS system’s robustness and safety.The following table shows the possible system failuresand the corresponding protection modes.

3.6.3.1 Auto Restart Mode I

Figure 16 Auto Restart Mode I

The VCC voltage is observed by comparator C13 if20.5V is exceeded. The output of C13 is combined withboth the output of C3 which checks for VSoftS < 4.0V andthe output of C4 which checks for VFB > 4.5V. Thereforethe overvoltage detection can only be active during SoftStart Phase (VSoftS < 4.0V) and when FB signal isoutside the operating range > 4.5V. This means any

1.35V

3.61V

4.5V

VFB

3.0V

4.0V

VSoftS t

t

0.32V

1.0V

VCS

10.3V

VVCC t

t

500uA

IVCC

t

2mA

VOUT

t

Max. Ripple < 1%

Blanking Window

Current limit levelduring Active BurstMode

3.0V

EnteringActive BurstMode

LeavingActive BurstMode

3.6V~3.2V

VCC Overvoltage Auto Restart Mode I

Over temperature Auto Restart Mode I

Overload Auto Restart Mode II

Open Loop Auto Restart Mode II

VCC Undervoltage Auto Restart Mode II

Short Optocoupler Auto Restart Mode II

C3

SpikeBlanking

8.0us

Thermal Shutdown

Tj>140°C

AutoRestartMode

InternalBias

Control Unit

C13

20.5V

VCC

C4

4.5V

FB

4.0V

SoftS

&

G12

&

G13FF2

R

S

QUVLO



small voltage overshoots of VVCC during normaloperating cannot trigger the Auto Restart Mode I.

In Order to ensure system reliability and prevent anyfalse activation, a blanking time is implemented beforethe IC can enter into the Auto Restart Mode I. Theoutput of the VCC overvoltage detection is fed into aspike blanking with a time constant of 8.0us.

The other fault detection which can result in the AutoRestart Mode I and has this 8.0us blanking time is theOvertemperature detection. This block checks for ajunction temperature of higher than 140°C formalfunction operation.

Once Auto Restart Mode is entered, the internal bias isswitched off in order to reduce the current consumptionof the IC as much as possible. In this mode, theaverage current consumption is only 300uA as the onlyworking blocks are the reference block and theUndervoltage Lockout(UVLO) which controls theStartup Cell by switching on/off at VVCCon/VVCCoff.

As there is no longer a self supply by the auxiliarywinding, VCC starts to drop. The UVLO switches on theintegrated Startup Cell when VCC falls below 10.3V. Itwill continue to charge VCC up to 18V whereby it isswitched off again and the IC enters into the Start UpPhase.

As long as all fault conditions have been removed, theIC will automatically power up as usual with switchingcycle at the GATE output after Soft Start duration. Thusthe name Auto Restart Mode.

3.6.3.2 Auto Restart Mode II

Figure 17 Auto Restart Mode II

In case of Overload or Open Loop, FB exceeds 4.5Vwhich will be observed by C4. At this time, the externalSoft Start capacitor can now be charged further by theintegrated pull up resistor RSoftS via switch S3 (seeFigure 13). If VSoftS exceeds 4.0V which is observed byC3, Auto Restart Mode II is entered as both inputs ofthe gate G5 are high.

This charging of the Soft Start capacitor from3.2V~3.6V to 4.0V defines a blanking window whichprevents the system from entering into Auto RestartMode II unintentionally during large load jumps. In thisevent, FB will rise close to 5.0V for a short durationbefore the loop regulates with FB less than 4.5V. Thisis the same blanking time window as for the ActiveBurst Mode and can therefore be adjusted by theexternal CSoftS.

In case of VCC undervoltage, ie. VCC falls below10.3V, the IC will be turned off with the Startup Cellcharging VCC as described earlier in this section. OnceVCC is charged above 18V, the IC will start a newstartup cycle. The same procedure applies when thesystem is under Short Optocoupler fault condition, as itwill lead to VCC undervoltage.

C3

4.0V

C4

4.5V &

G5

Control Unit

SoftSInternal

Bias

AutoRestartMode

FB



4 Electrical Characteristics

Note: All voltages are measured with respect to ground (Pin 8). The voltage levels are valid if other ratings arenot violated.

4.1 Absolute Maximum Ratings

Note: Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destructionof the integrated circuit. For the same reason make sure, that any capacitor that will be connected to pin 7(VCC) is discharged before assembling the application circuit.

Parameter Symbol Limit Values Unit Remarks

min. max.

Drain Source Voltage VDS - 650 V Tj = 110°C

Pulse drain current,tp limited by max.Tj=150°C

ICE3B0365J ID_Puls1 - 1.6 A




Avalanche energy,repetitive tAR limitedby max. Tj=150°C1)

1) Repetetive avalanche causes additional power losses that can be calculated as PAV=EAR* f

ICE3B0365J EAR1 - 0.005 mJ

ICE3B0565J EAR2 - 0.01 mJ



Avalanche current,repetitive tAR limitedby max. Tj=150°C1)

ICE3B0365J IAR1 - 0.3 A

ICE3B0565J IAR2 - 0.5 A

ICE3B1565J IAR3 - 1.5 A

ICE3B2065J IAR4 - 2.0 A

VCC Supply Voltage VVCC -0.3 27 V

FB Voltage VFB -0.3 5.0 V

SoftS Voltage VSoftS -0.3 5.0 V

CS Voltage VCS -0.3 5.0 V

Junction Temperature Tj -40 150 °C Controller & CoolMOS®

Storage Temperature TS -55 150 °C

Thermal ResistanceJunction-Ambient

RthJA - 90 K/W PG-DIP-8

ESD Capability VESD - 2 kV Human body model2)

2) According to EIA/JESD22-A114-B (discharging a 100pF capacitor through a 1.5kW series resistor)



4.2 Operating Range

Note: Within the operating range the IC operates as described in the functional description.

4.3 Characteristics

4.3.1 Supply Section

Note: The electrical characteristics involve the spread of values guaranteed within the specified supply voltageand junction temperature range TJ from – 25 oC to 130 oC. Typical values represent the median values,which are related to 25°C. If not otherwise stated, a supply voltage of VCC = 18 V is assumed.

Parameter Symbol Limit Values Unit Remarks

min. max.

VCC Supply Voltage VVCC VVCCoff 26 V

Junction Temperature of Controller TjCon -25 130 °C Max value limited due tointegrated thermal shut down

Junction Temperature ofCoolMOS®

TJCoolMOS -25 150 °C

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.

Start Up Current IVCCstart - 300 450 mA VVCC = 17V

VCC Charge Current IVCCcharge1 - - 5.0 mA VVCC = 0V

IVCCcharge2 0.55 1.05 1.60 mA VVCC = 1V

IVCCcharge3 - 0.88 - mA VVCC = 17V

Leakage Current ofStart Up Cell & CoolMOS

IStartLeak - 0.2 50 mA VDrain= 450Vat Tj = 100°C

SupplyCurrent withInactive Gate

ICE3B0365JICE3B0565JICE3B1565J

IVCCsup_ng1 - 1.7 2.5 mA Soft Start pin is open

ICE3B2065J IVCCsup_ng2 - 3.3 4.2 mA

Supply Current with Active Gate IVCCsup_g - 2.5 3.6 mA VSoftS = 3.0VIFB = 0

Supply Current inAuto Restart Modewith Inactive Gate

IVCCrestart - 300 - mA IFB = 0ISofts = 0

Supply Current inActive Burst Modewith Inactive Gate

IVCCburst1 - 500 950 uA VFB = 2.5VVSoftS = 3.0V

IVCCburst2 - 500 950 uA VVCC = 11.5VVFB = 2.5VVSoftS = 3.0V

VCC Turn-On ThresholdVCC Turn-Off ThresholdVCC Turn-On/Off Hysteresis

VVCCon

VVCCoff

VVCChys

17.09.6-

18.010.37.7

19.011.0-

VVV



4.3.2 Internal Voltage Reference

4.3.3 PWM Section

4.3.4 Control Unit


min. typ. max.

Trimmed Reference Voltage VREF 4.90 5.00 5.10 V measured at pin FBIFB = 0


min. typ. max.

Fixed Oscillator Frequency fOSC3 58 67 76 kHz

fOSC4 62 67 74.5 kHz Tj = 25°C

Frequency Jittering Range fdelta - ±2.7 - kHz Tj = 25°C

Max. Duty Cycle Dmax 0.70 0.75 0.80

Min. Duty Cycle Dmin 0 - - VFB < 0.3V

PWM-OP Gain AV 3.0 3.2 3.4

Max. Level of Voltage Ramp VMax-Ramp - 0.6 - V

VFB Operating Range Min Level VFBmin - 0.5 - V

VFB Operating Range Max level VFBmax - - 4.3 V CS=1V limited byComparator C41)

1) This parameter is not subject to production test - verified by design/characterization

Feedback Pull-Up Resistor RFB 9 14 22 kW

Soft-Start Pull-Up Resistor RSoftS 30 45 62 kW


min. typ. max.

Deactivation Level for SoftSComparator C7 by C2

VSoftSC2 2.98 3.10 3.22 V VFB = 5V

Clamped VSoftS Voltage duringBurst Mode

VSoftSclmp_bm 2.88 3.00 3.12 V

Activation Limit ofComparator C3

VSoftSC3 3.85 4.00 4.15 V VFB = 5V

SoftS Startup Current ISoftSstart - 0.9 - mA VSoftS = 0V

Over Load & Open LoopDetection Limit forComparator C4

VFBC4 4.33 4.50 4.67 V VSoftS = 4.5V

Active Burst Mode Level forComparator C5

VFBC5 1.23 1.35 1.43 V VSoftS = 4.5V

Active Burst Mode Level forComparator C6a

VFBC6a 3.48 3.61 3.76 V After Active BurstMode is entered



Note: The trend of all the voltage levels in the Control Unit is the same regarding the deviation except VVCCOVP

4.3.5 Current Limiting

4.3.6 CoolMOS® Section

Active Burst Mode Level forComparator C6b

VFBC6b 2.88 3.00 3.12 V After Active BurstMode is entered

Overvoltage Detection Limit VVCCOVP 19.5 20.5 21.5 V VFB = 5V, VSoftS = 3V

Thermal Shutdown1) TjSD 130 140 150 °C

Spike Blanking tSpike - 8.0 - ms

1) The parameter is not subject to production test - verified by design/characterization


min. typ. max.

Peak Current Limitation (incl.Propagation Delay Time)(see Figure 11)

Vcsth 1.01 1.06 1.11 V dVsense / dt = 0.6V/ms

Peak Current Limitation duringActive Burst Mode

VCS2 0.27 0.32 0.37 V

Leading Edge Blanking tLEB - 220 - ns VSoftS = 3.0V

CS Input Bias Current ICSbias -1.0 -0.2 0 µA VCS = 0V


min. typ. max.

Drain Source BreakdownVoltage

V(BR)DSS 600650

--

--

VV

Tj = 25°CTj = 110°C

Drain SourceOn-Resistance

ICE3B0365J RDSon1 --

6.4513.70

7.5017.00

WW

Tj = 25°CTj = 125°C1)

at ID = 0.3A


4.7010.00

5.4412.50

WW

Tj = 25°CTj = 125°C1)

at ID = 0.5A


1.703.57

1.964.12

WW

Tj = 25°CTj = 125°C1)

at ID = 1.5A


0.921.93

1.052.22

WW

Tj = 25°CTj = 125°C1)

at ID = 2.0A

Effective outputcapacitance,energy related

ICE3B0365J Co(er)1 - 3.65 - pF VDS = 0V to 480V

ICE3B0565J Co(er)2 - 4.75 - pF

ICE3B1565J Co(er)3 - 11.63 - pF

ICE3B2065J Co(er)4 - 21 - pF



Rise Time trise - 302) - ns

Fall Time tfall - 302) - ns

1) The parameter is not subject to production test - verified by design/characterization

2) Measured in a Typical Flyback Converter Application



5 Temperature derating curve

Figure 18 Safe Operating area ( SOA ) curve for ICE3B0365J




Figure 22 SOA temperature derating coefficient curve



6 Outline Dimension

Figure 23 PG-DIP-8 ( Pb-free lead plating Platic Dual-in-Line Outline )

PG-DIP-8(Plastic Dual In-Line Outline)



7 Marking

Figure 24 Marking for ICE3B0365J


Marking

Marking





Marking

Marking



Schematic for recommended PCB layout

8 Schematic for recommended PCB layout

Figure 28 Schematic for recommended PCB layout

General guideline for PCB layout design using F3 CoolSET (refer to Figure 26):

1. “Star Ground “at bulk capacitor ground, C11:

“Star Ground “means all primary DC grounds should be connected to the ground of bulk capacitor C11separately in one point. It can reduce the switching noise going into the sensitive pins of the CoolSET deviceeffectively. The primary DC grounds include the followings.

a. DC ground of the primary auxiliary winding in power transformer, TR1, and ground of C16 and Z11.

b. DC ground of the current sense resistor, R12

c. DC ground of the CoolSET device, GND pin of IC11; the signal grounds from C13, C14, C15 and collector ofIC12 should be connected to the GND pin of IC11 and then “star “connect to the bulk capacitor ground.

d. DC ground from bridge rectifier, BR1

e. DC ground from the bridging Y-capacitor, C4

2. High voltage traces clearance:

High voltage traces should keep enough spacing to the nearby traces. Otherwise, arcing would incur.

a. 400V traces (positive rail of bulk capacitor C11) to nearby trace: > 2.0mm

b. 600V traces (drain voltage of CoolSET IC11) to nearby trace: > 2.5mm

3. Filter capacitor close to the controller ground:

Filter capacitors, C13, C14 and C15 should be placed as close to the controller ground and the controller pinas possible so as to reduce the switching noise coupled into the controller.

Guideline for PCB layout design when >3KV lightning surge test applied (refer to Figure 26):

1. Add spark gap

Spark gap is a pair of saw-tooth like copper plate facing each other which can discharge the accumulatedcharge during surge test through the sharp point of the saw-tooth plate.

a. Spark Gap 3 and Spark Gap 4, input common mode choke, L1:

Gap separation is around 1.5mm (no safety concern)


Schematic for recommended PCB layout


b. Spark Gap 1 and Spark Gap 2, Live / Neutral to GROUND:

These 2 Spark Gaps can be used when the lightning surge requirement is >6KV.

230Vac input voltage application, the gap separation is around 5.5mm

115Vac input voltage application, the gap separation is around 3mm

2. Add Y-capacitor (C2 and C3) in the Live and Neutral to ground even though it is a 2-pin input

3. Add negative pulse clamping diode, D11 to the Current sense resistor, R12:

The negative pulse clamping diode can reduce the negative pulse going into the CS pin of the CoolSET andreduce the abnormal behavior of the CoolSET. The diode can be a fast speed diode such as IN4148.

The principle behind is to drain the high surge voltage from Live/Neutral to Ground without passing through thesensitive components such as the primary controller, IC11.

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Published by Infineon Technologies AG

CoolSET -F3R (Jitter Version)

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