Controller Design For SEPIC Converter Using Model Order Reduction

ASAR International Conference, Bangalore Chapter- 2013, ISBN: 978-81-927147-0-7

51

CONTROLLER DESIGN FOR SEPIC CONVERTER USING MODEL ORDER REDUCTION

1BINOD KUMAR PADHI, 2ANIRUDHA NARAIN

Department of Electrical Engineering, Motilal Nehru National Institute of Technology, Allahabad

AbstractA SEPIC (Single-Ended Primary Inductor Converter) is a DC-DC converter, capable of operating both in step-up or step-down mode and widely used in battery-operated applications. There are two possible modes of operation in the SEPIC converter: Continuous Conduction Mode (CCM) and Discontinuous Conduction Mode (DCM). This paper presents modeling of a SEPIC converter operating in CCM using the State-Space Averaging (SSA) technique. SEPIC converter consists of two inductor and two capacitor hence it is fourth order dc-dc converter. Design of feedback compensator for fourth order system is quite complex. In this paper, model order reduction technique is used for controller design of SEPIC converter. First small signal dynamic model for SEPIC converter is obtained using SSA technique which provides fourth order transfer function. Then this fourth order transfer function is reduced to second order using Pad approximation. Then the compensator is designed for the reduced order model of the SEPIC converter. Result shows that the compensator designed for reduced order model gives the quite satisfactory response with the original system. Keywords- SEPIC Converter, CCM, State-Space Averaging, Model Order Reduction, Pad-Approximation, Compensator I. INTRODUCTION

he switched mode dc-dc converters are the power electronic systems that convert one level electrical

voltage to another level of electrical voltage by the help of switching action. These are extensively used in battery operated portable electronic equipment and system because of its greater efficiency, smaller size and lighter weight [1, 5]. The SEPIC converter is a type of dc-dc converter and is capable of providing a non-inverted output voltage which is either greater than, less than or equal to the input voltage and widely used in battery operated equipments. The output of the SEPIC converter is controlled by the duty cycle of the control transistor. The SEPIC converter has two modes of operation one is Continuous Conduction Mode (CCM) and the other one is Discontinuous Conduction Mode (DCM). Here the SEPIC is operated in CCM. SEPIC converter has excellent properties like capacitive energy transfer, full transformer utilization, excellent transient performance and good steady-state performances such as wide conversion ratio, continuous current at input and capacitor voltage.

The dynamic response, however, is affected by the fourth order characteristic, which generally calls for closed-loop bandwidth limitations in order to ensure large-signal stabilization. Moreover, stability may require big energy transfer capacitors in order to decouple input and output stages.

The robust multivariable controllers could be used to optimize the converter dynamics and ensuring the correct operation in any working condition however this involves considerable complexity of both theoretical analysis and control

implementation. So in order to remove these difficulties first we reduce the order of transfer function of SEPIC converter then design the controller.

The SEPIC converter is made up of two capacitors, two inductors, a power switch and a diode thus it is fourth order non-linear system and in this paper the equivalent series resistances (ESR) of the inductors and capacitors are considered. For the feedback control design linear model is needed. The linear model of the converter is derived by the replacement of switch and diode of converter by small signal averaged switch model [7]. In this paper the desired transfer function is obtained using state space averaging technique [1, 2, 6, and 9]. This paper presents the modeling and control of SEPIC converter operating in continuous conduction mode. In continuous conduction mode, inductor current never falls to zero during one switching period. The SSA technique is used to find small signal linear model and its various forms of transfer functions. Depending on control-to-output transfer function, the PWM feedback controller [8-9] is designed to regulate the output voltage of the SEPIC converter. The higher order system increases the complexity of the controller. So, in order to remove these difficulties the higher order system is reduced to 2nd order system by using model order reduction technique [12-15]. In this paper the Pad approximation [12] model reduction technique is used to reduce the higher order system. This paper is organized as follows: SSA Technique is given in section II. Modeling of SEPIC converter by SSA Technique is shown in section III. Control Strategy is shown in section IV and Conclusion in section V.

T

Controller Design For SEPIC Converter Using Model Order Reduction

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II. SSA TECHNIQUE

State space modeling is a technique that describes a given system using a system of linear differential equations. The power stage of closed loop system is a non-linear system. The non-linear systems are usually difficult to model and are also difficult to predict the behavior of the non-linear system. So, it is better to approximate the non-linear system to a linear system. For the linearized power stage of dc-dc converter Bode plot can be used to determine suitable compensation in feedback loop for desired steady state and transient response. For this the state space averaging technique is used.

In dc-dc converter operating in CCM has two circuit states: one when the switch is turned on and other when the switch is turned off. During switch on:

1 1 dX A X B V 0< t < dT

0 1 1 dV C X E V (1) During switch off:

2 2 dX A X B V 0< t < (1-d)T

0 2 2 dV C X E V (2) To produce an average description of the circuit over a switching period, the equations corresponding to the two foregoing states are time weighted and averaged, resulting in the following equations:

1 2 1 2[ (1 )] [ (1 )] dX Ad A d X B d B d V (3)

0 1 2 1 2[ (1 )] [ (1 )] dV C d C d X E d E d V (4) III. MODELING OF A SEPIC CONVERTER

BY SSA TECHNIQUE

The SEPIC converter shown in Fig. 1(a) contains two capacitors C1 and C2 with equivalent series resistors rC1 and rC2 respectively, two inductors L1 and L2 with equivalent series resistors rL1, rL2 respectively, a MOSFET switch Q and a diode D. The resistor R is represents the load. The SEPIC converter exchanges the energy between the capacitors and inductors in order to convert from one voltage to another. The amount of energy exchanged is controlled by the control transistor i.e. MOSFET. A SEPIC is said to be in CCM if the current through the inductor L1 never falls to zero. In CCM, the converter has two states. During the first state i.e. when Q is turned on (Fig. 1(b)) L1 is charged by the source Vd and L2 is charged by the capacitor C1. Hence current iL1 and iL2 increases linearly. During the second state i.e. when Q is turned off (Fig. 1(c)) L1 and L2 are in a discharging phase and release the stored energy to the capacitors and load respectively. Hence iL1 and iL2 decreases linearly. In ideal SEPIC converter the ESRs are zero. For the ideal converter the relationship between the Vd and V0 is given by:

1o

d

V dV d

(5)

Where d is the duty cycle of the switch. This equation shows that by controlling the duty cycle of the switch the output voltage Vo can be controlled and output voltage can be higher or lower than or equal to the input voltage Vd. The duty cycle of the SEPIC converter can be varied during operation by using a controller and the circuit can also be made to reject disturbances [11].

A. State Space Description The state space equations for SEPIC converter

during switch on and off are During switch ON:

1 1 1

1 1

dL L L Vdi r idt L L

(6)

1 2 2 12

2 2

( )C L L CL r r i Vdidt L L

(7)

1 2

1

C LdV idt C

(8)

2 2

2 2( )C C

C

dV Vdt C R r

(9)

20

2

E C

C

R VVr

(10)

During switch OFF 11

11 1 12 2 13 21 1

C dLL L C

V Vdi S i S i S Vdt L L

(11)

22 2 1 2 2

1 2 2 2 2

( ) E CL E L E L LC

R Vdi C R i R r idt C L L L r

(12)

1 1

1

C LdV idt C

(13)

2 21 2

1 2 2 2 2 2( )C CE L E L

C C C

dV VR i R idt C r C r C R r

(14)

20 1 2

2

E CE L E L

C

R VV R i R ir

(15)

Where 2 1 1 111

1 1

( )E L CC R C r rSL C

(16)

2 2 1 2 112 2

1

L L EL r L r L RSL

(17)

13

1

ER RSRL

(18)

And states of the SEPIC converter are iL1, iL2, VC1, VC2.

The averaged matrices for the steady-state and linear small-signal state-space equations can be written according to above equations.

1

1 2

2

1

2 21

2

0 0 0

( ) 10 0

10 0 01

10 0 0( )

L

C L

C

rL

r rL LA

C

C R r

(19)

Controller Design For SEPIC Converter Using Model Order Reduction

ASAR International Conference, Bangalore Chapter- 2013, ISBN: 978-81-927147-0-7

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2

2

2 2 2

11 12 131

2

1 2 2 22

1

1 2 2

1

0

1 0 0 0

10( )

E LE E

C

E E

C C C

S S SL

R rC R RC L L L r

A

CR R

C r C r C R r

(20)

1

1 2

1

000

LB B B

(21)

2

1 0 0 0 EC

RCr

(22)

2

2 R R 0 EE EC

RCr

(23)

1 2 [ 0 ]E E E (24) B. Finding Transfer Function With the state space matrices defined above, the

control to output transfer function can be calculated as:

1( )d v d dG C S I A B E (25)

Where 1 2 (1 )A A d A d (26) 1 2 (1 )B B d B d (27) 1 2(1 )C C d C d (28) 1 2 (1 )E E d E d (29)

1 2 1 2( ) ( )d dB A A X B B V (30) Output to input transfer function

1( )vvG C S I A B (31)

1dX A B V

(32)

Fig. 1(a) SEPIC Converter.

Fig. 1(b) SEPIC Converter when switch is ON.

Fig. 1(c) SEPIC Converter when switch is OFF. Fig. 1. Operation of SEPIC Converter in CCM.

IV. CONTROL STRATEGY

C. PWM Feedback Control The SEPIC converter with PWM feedback control

is shown in the Fig. 2(a). The output voltage V0 is compared with the reference voltage Vref. The error voltage Ve between output voltage and reference voltage is passed through the compensator Gc(s) to generate a control signal VC and compared with the saw-tooth voltage of amplitude VM by using the PWM comparator. Finally the PWM comparator converts the control signal into a waveform that drives the MOSFET switch. As depicted in Fig. 2(b), the MOSFET switch is turned on when Vc is larger than Vsaw, and turned off when Vc is smaller than Vsaw. If V0 is changed, feedback control will respond by adjusting Vc and then duty cycle of the MOSFET until V0 is again equal to Vref.

Fig. 3 shows a small-signal block diagram of the converter of Fig. 2(a). The power stage transfer functions are represented by Gdv(s) which is derived earlier. The transfer function of the PWM comparator can be derived from the wave form in Fig. 2 (b). It is given by:

1M

M

FV

(33)

Where VM is the amplitude of saw-tooth waveform and GC(s) is a controller or compensator. From Fig 3 the open loop transfer function can be defined as:

( ) ( ) ( )C dv MT s G s G s F (34) The loop gain T(s) is defined as the product of the

small signal gain in the forward and feedback paths of the feedback loop. It is found that the transfer function from a disturbance to the output is multiplied by the factor 1/(1+T(s)). So the loop gain magnitude || T || is a measure of how well the feedback system works.

Fig. 2(a) SEPIC converter with PWM feedback control.

Controller Design For SEPIC Converter Using Model Order Reduction

ASAR International Conference, Bangalore Chapter- 2013, ISBN: 978-81-927147-0-7

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Fig. 2(b) Waveform of PWM Comparator.

Fig. 3.Small-signal block diagram of SEPIC converter with

PWM feedback control. D. Example

TABLE I. Converter Parameters Circuit Parameters Values

Input Voltage Vd 10 V Output Voltage V0 15 V

Switching frequency 100 kHz Load R 1

PWM Gain FM 1/7 L1 100 H rL1 1 m L2 100 H rL2 1 m C1 800F rC1 3 m C2 3000F rC2 1 m

Output ripple 5% The transfer function of the converter is obtained

from (25) is as follows: 3 6 2 8 13

4 3 6 2 9 12

1.998 2.496 10 1.056 10 2.13 10( )373.5 8.88 10 2.91 10 3.215 10dv

s s sG ss s s s

(35) This is a fourth order transfer function. It has two pair of complex pole and three zeros (one pair of complex zero and one real zero). Zeros and poles of the converter are as given as: Poles are: -16.0968180026888 + 2913.77550013486i -16.0968180026888 - 2913.77550013486i -170.653181997311 + 591.221469408464i -170.653181997311 - 591.221469408464i Zeros are: -1249213.77176921 -17.7387400194398 + 2921.22945653372i -17.7387400194398 - 2921.22945653372i

E. Model Order Reduction Using Pad-Approximation method [12], the

reduced order transfer function of the converter is obtained as follows:

6

2 5

2.371 2.508 10( )341.2 3.786 10Rdv

sG ss s

(36) This is a 2nd order transfer function. It has one pair of complex pole and one real zero. Poles and zeros of reduced system are: Poles are: -170.58530739407 + 591.192159394338i -170.58530739407 - 591.192159394338i Zeros are: -1058144.2919679

Fig. 4, Fig. 5 and Fig. 6 clearly shows that the step response and Bode plot of the reduced system closely approximates with the step response and bode plot of the original system. Integral Square Error (ISE) between original system and reduced order system is 4.77710-8. Then the next objective is to design the controller for the reduced order converter.

0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.040

1

2

3

4

5

6

7

8

9

10

Step Response

Time (sec)

Ampl

itude

Original SystemReduced model

Fig. 4. Step response of open loop original system and reduced

model.

0 0.005 0.01 0.015 0.02 0.025 0.03 0.0350

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

Step Response

Time (sec)

Ampl

itude

Original SystemReduced model

Fig. 5. Step response of closed loop original system and reduced model.

Controller Design For SEPIC Converter Using Model Order Reduction

ASAR International Conference, Bangalore Chapter- 2013, ISBN: 978-81-927147-0-7

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-200

-150

-100

-50

0

50M

agni

tude

(dB)

101

102

103

104

105

106

107

108

-225

-180

-135

-90

-45

0

Phas

e (d

eg)

Bode Diagram

Frequency (rad/sec)

Original SystemReduced Model

Fig. 6. Bode plot of open loop original system and reduced

model.

-200

-150

-100

-50

0

50

Mag

nitu

de (d

B)

101

102

103

104

105

106

107

108

-225

-180

-135

-90

-45

0

Phas

e (d

eg)

Bode DiagramGm = 7.99 dB (at 2.9e+003 rad/sec) , Pm = 13.3 deg (at 1.68e+003 rad/sec)

Frequency (rad/sec) Fig. 7. Bode plot of uncompensated open loop system which has

gain margin 7.98dB and phase margin 13.3 deg. Fig. 7 shows that the Bode plot of the system

without compensator has phase margin of 13.3 deg which is not sufficient for a stable system. Hence a compensator is designed to obtain the suitable phase margin.

F. Feedback Loop Compensation In this paper voltage-mode linear averaged

feedback controllers [9-10] for dcdc converter is designed in frequency domain. The main objective of the controller design is to obtain stable operation of the converter by varying the duty cycle. Following points are taken care while designing of the compensator.

First the averaged mathematical model is accurate up to one tenth of switching frequency. Here the switching frequency is taken as 100 kHz therefore the bandwidth (0 dB cross over frequency of closed loop system) should be near 10 kHz. Secondly high gain at low frequency region provides good output voltage regulation. And phase margin determines the transient response to sudden change in input voltage. The suitable phase margin is in between 450 to 600 degree.

G. Steps For Compensator Design Step 1: Select a resistor value for R1. Step 2: Select calculate the compensators maximum phase frequency wm using the equation m cw w (37) Where wc is the desired cross-over frequency. Step 3: Calculate the difference between the zero's frequency and pole's frequency using the equation

)cot()1( 2 mpcd (38)

Where m is the desired phase margin and P is the control plant gain. Step 4: Calculate the zero's frequency z and pole's frequency p using the following equations:

)4(5.0 22 dmdz (39)

)4(5.0 22 dmdp (40)

Step 5: Calculate the compensators constant gain G

using the equation 2

2

)(1

)(1

z

c

p

c

p

c

GG

(41)

Step 6: Calculate C1 using the equation GR

Cp

z

11

(42) Step 7: Calculate C2 using the equation

11

21 C

GRC

(43)

Step 8: Calculate R2 using the equation 2

21C

Rz

(44) Step 9: Plot the loop Bode plot and verify the phase margin. Step 10: Check the gain margin. If the gain margin is not satisfied, adjust and go back to step 2 to re-design the compensator.

Using the steps for compensator design the compensator is designed whose transfer function is:

6

1 6 2

9 .9 4 3 1 0 15 .4 7 9 1 0 0 .0 0 0 7 7 4 2c

sGs s

(45)

Controller Design For SEPIC Converter Using Model Order Reduction

ASAR International Conference, Bangalore Chapter- 2013, ISBN: 978-81-927147-0-7

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and therefore, the overall open-loop transfer of the reduced order model with compensator is

7 2 4

16 4 3 2

7.605 10 0.8809 8.09 10( )5.479 10 0.0007742 0.2642 293.1R

s sT ss s s s

(46) And similarly the open loop transfer function for the original system with compensator is

7 4 3 4 2 7 11

16 6 5 4 3 6 2 9 11

10 0.865 8.055 10 1.024 10 6.871 10

5.479 10 0.0007742 0.2892 6876 2.334 10 2.499 10 6.871 10( )

s s s s

s s s s s sT s

(47)

Fig. 8 shows that the Bode plot of open loop original system with compensator which has gain margin of 1.87 dB and phase margin of 53.1 deg and Bode plot of open loop reduced model with compensator which has gain margin of 1.87 dB and phase margin of 53 deg. Fig. 9 shows that step responses of compensated reduced order model closely approximates with the step response of compensated original system.

-200

-100

0

Mag

nitu

de (d

B)

101

102

103

104

105

106

107

108

-315

-270

-225

-180

-135

-90

Phas

e (d

eg)

Bode DiagramGm = 1.87 dB (at 617 rad/sec) , Pm = 53 deg (at 431 rad/sec)

Gm = 1.87 dB (at 616 rad/sec) , Pm = 53.1 deg (at 430 rad/sec)

Frequency (rad/sec)

Original System with CompensatorReduced model with Compensator

Fig. 8. Bode plot of original system and reduced model with

compensator.

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.450

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Step Response

Time (sec)

Ampl

itude

Original System with CompensatorReduced model with compensator

Fig. 9. Step response of original system and reduced model

with compensator.

CONCLUSION

This paper deals with modeling and control of SEPIC converter operating in continuous conduction mode (CCM). The state space averaging technique is applied to find out the linear model of SEPIC converter and the desired transfer function in terms of duty ratio to output voltage (Gdv) is obtained which is a fourth order transfer function. Designing a compensator for the fourth order system is very difficult. Therefore, fourth order transfer function of SEPIC converter is reduced to second order and it is found that step response of reduced order model closely follow the original system. The compensator designed for second order system gives quite satisfactory response with the original system. REFERENCES [1] R. W. Erickson and D. Makdimovic, Fundamental of Power

Electronics, 2nd ed., Kluwer Academic Publishers, 2001. [2] R. D. Middlebook and S. Cuk, A General Unified Approach to

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[4] R. Ridley, Analyzing the sepic converter, Power Systems Design Europe Magazine, pp. 14-18, November 2006.

[5] M. H. Rashid, Power Electronics Handbook: Devices, Circuits, and Applications, 2nd ed, Elsevier Inc, 2007.

[6] E. Vuthchhay, P. Unnat, and C. Bunlaksananusorn, "Modeling of a sepic converter operating in continuous conduction mode," 6th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology 2009 (ECTI-CON 2009), pp. 136-139, May 2009.

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[8] A. J. Forsyth and S.V. Mollov, "Modelling and control of DC-DC converters," IEEE Power Engineering Journal, pp. 229-236, 1998.

[9] E. Vuthchhay, C. Bunlaksananusorn, and H. Hirata, "Dynamic Modeling and Control of a Zeta Converter," International Symposium on Communications and Information Technologies 2008 (ISCIT 2008), Oct. 2008.

[10] B. C. Kuo, Automatic Control Systems, 7th ed., Prentice Hall Inc, 1995.

[11] A. Chuinard, T. Chairet, " Feedback compensation techniques to improve input disturbance response in the Cuk converter," June . 2009.

[12] Y. Shamash, "Stable reduced-order models using Pad type approximations," IEEE Transactions automatic control, vol.19, no.5, pp. 615- 616, Oct 1974.

[13] C.B Vishwakarma, R. Prasad, System reduction using Modified Pole Clustering and Pade Approximation, National systems conference, NSC 2008, December 17-19 2008.

[14] V. Krishnamurthy and V. Seshadri, Model Reduction Using the Routh Stability Criterion, IEEE Transactions On Automatic Control, VOL. AC-2-3, NO. 4, AUGUST 1978.

[15] Vimal Singh, Dinesh Chandra, and Haranath Kar, Improved RouthPad Approximants: A Computer-Aided Approach, IEEE Transactions On Automatic Control, Vol. 49, No. 2, February 2004.