Connectivity and Interoperability Solutions Page 25.../INIT /SELECTIN /EPPINIT /PINIT PE /INIT...

Connectivity and Interoperability Solutions Page 25

Philips Semiconductors - Asia Product Innovation CentreVisit http://www.flexiusb.com

Figure 4-3: Schematic of the main board.

D12-EVAL-102M 1.2

D12 USB-EPP Evaluation Main Board

Custom

1 2T hursday, August 13, 1998

T itle

Size Document Number Rev

Date: Sheet of

VCC

VCC

VCC

VCC

VCC

VCC

V_BUS

VCC

V_BUS

+5V

VCC

+3V3

+3V3

VCC

VCC

VCC

VCC

VCC

Signals RegisterD0-D7 D0-D7 D0-D7nERROR S3 UDB2SELECT S4

S5S6/S7/C0/C1C2/C3

PaperEndnACKBUSYnStrobenAutoLFnInitnSlectIn

XFlag/UDB3UDB1IntrnWaitnWritenDStrbnInitnAstrb

EPP Mode

MAX202/ADM202

APIC, Philips Semiconductors

TestingHeaderFor D12

Female

FemaleStyle

Testing Ground

PowerSupply

Don't install when usingSoftConnect

Power Supply for Daughter BoardDefault 1-2

Pin No.

2-915131210111141617

GND 18-25

Expansion Header For MCU

For U1For U2For U3For U4For U5For U5For U5For U5For U6

Decoupling Capacitors

Size: 18.0' x 12.0'

EPP InterfaceTest Header

ISPConnector

Wake-upbutton

EPP Interface Module

Decoupling Capacitors Module

MicroController Module

RS232 Monitoring Module

USB Interface PDIUSBD12 Module

Power(SelfPower/BusPower) Switching Module

DMA and EPP Control Module

Chassis

SelfPower

BusPower

Decoding

XTAL2XTAL1

/D12CS

USBDP

D12DP

D12DM

PD0PD1PD2PD3

/WRITE/DSTROBE

PD0

PD1

PD2

PD3

D0

CPLDTDO

CPLDT CK

/D12DACK/D12DACK D12DREQD12DREQ

/D12WR

/D12WR

/D12RD

/D12RD

/D12EOT

CPLDTMS

MCURST

/HOSTDACK

CPLDTDI

/STROBE/AUTOFD

/SHDN

/STROBE/AUTOFD

/SELECTIN

/D12EOT

/D12EOT

D12A0

D12DPD12DM

XTAL2XTAL1GOODLNK

/D12EOT/D12DACKD12DREQ/D12WR/D12RD

RS232RXD

RS232TXD

GOODLNK

PD4

EPP_DIRPD5

PD5PD4PD6

PD6PD7

PD7

BUSY/ACK /INTR

/WAIT

SELECT

PE

LA0

SWM0

/WRITE/DSTROBE/ASTROBE/WAIT/INTRPE/ERRORSELECTMCURST

S232TXD ALE/PSEN/D12INTALE1SUSPENDSWM0RLED0

RLED1 SWM1DMARD_WR/MCUWRWHICH_PW/MCURD/EPPINITMCUX2

CLK12M /HOSTDACKHOSTDREQ

S232RXD

LA1

D12A0

SWM1

/D12INTCLK12MSUSPEND/D12CS

/ASTROBE

/AUTOFD/ERROR

/SELECTIN

/STROBEPD0PD1PD2PD3PD4PD5PD6PD7/ACKBUSY

SELECT

CPLDTMSCPLDTDICPLDTDO

CPLDT CK

/INIT

/SELECTIN

/EPPINIT /PINIT

PE

/INIT

/PINIT

D12A0EPP_DIR/SHDN

LA1LA0

/D12CS

D12DREQ

D0D1SUSPEND/ASTROBE/HOSTDACK/WRITE

ALE

HOSTDREQ

USBDM

RLED0

D5/MCUWR

/MCUWR

SUSPEND

/DSTROBE/WRITE

D7/EPPINIT

/DSTROBE

D7

RLED1

SELECT

/ASTROBE

D4SWM1DMARD_WR

/HOSTDACK

WHICH_PW

D4

SWM0

/WRITE

D6

WHICH_PW

D2

D7

D3

D1

D7

DMARD_WR

D3

/D12INT

/MCURD

/WAIT

MCURST

D1

S232TXD

D4

D2

D6

D6

HOSTDREQ

/ERRORPE/INTR

RLED0

D1D1

D5

/ERROR

RLED1

ALE/D12INT

ALE

D2

D5

D4

CLK12M

D[7:0]

/MCURD

S232RXD

/PSEN

D3

ALE1

D0

S232TXD

D0

D0

D2

MCURST

SUSPEND

S232RXD

D3

CLK12M

/WAIT

D6D5

MCUX2

D0D1D2D3D4D5D6D7

/DSTROBE

L1

6MHzX1

J8

UP_CONN

VBUS1

D-2

D+3

GND4

SHIELD5

C160.1uF

C170.1uF

C180.1uF

C190.1uF

C200.1uF

C210.1uF

R2

20K

R154.7K

C150.1uF

R124.7K

U6 PDIUSBD12DATA0

1

DATA12

DATA23

DATA34

GND5

DATA46

DATA57

DATA68

DATA79

ALE10

CS_N11

SUSPEND12

CLKOUT13

INT_N14

RD_N15WR_N 16DMREQ17DMACK_N 18EOT_N19RESET_N 20GL_N21XTAL1 22XTAL223VCC 24D-25D+26VOUT 3.3 27A028

R14

470R

R8

18R+/-1%

R7

18R+/-1%

L2C8

0.1uFC9

68pF

C10

22pF

R161M

R9

1M

R10

1M

C4

0.1uF

C1

0.1uF

C5

0.1uF

C34.7uF16V

+

U1

ADM222

NC1

C1+2

V+3

C1-4

C2+5

C2-6

V-7

T 2OUT8

R2IN9 R2OUT 10T 2IN11T 1IN 12R1OUT13R1IN 14T 1OUT15GND 16VCC17/SHDN 18

C2

0.1uF

C220.1uF

C230.1uF

R13

470R

D3LED_RED

C7 470pF

C12

0.1uFC111.0uF16V

+

J11

HEADER 2

12

J7RCA JACK

C64.7uF16V

+

J3

SUB-D 9

594837261

D1LED_GREEN

R5

1.5K

S2 SW PUSHBUTTON

J5HEADER 20

123456789

1011121314151617181920

C24100pF C25

100pF

D2LED_RED

U5

PZ5032

IN1

1

IN3

2

VC

C3

A0-C

K1

4

A1

5

A2

6

A3-TDI7

A48

A59

GND10

A611

A712

A8-TMS13

A914

VCC15

A1016

A1117

A12

18

A13

19

A14

20

A15

21

GN

D22

VC

C23

B15

24

B14

25

B13

26

B12

27

B11

28

B10 29GND30B9 31B8-T CK32B7 33B634VCC 35B536B437B3-TDO 38B239

B1

40

B0

41

GN

D42

CK

043

GT

SN

44

S3 SW PUSHBUTTON

J9

HEADER 18

123456789

101112131415161718

S4SW DPDT

J4

Header 5_2

P11

P22

P33

P44

P55

P6 6

P77

P88

P9 9

P1010

J2

SUB-D 25_0

13251224112310229218207196185174163152141

J12

HEADER 13_2

P11

P22

P33

P44

P55

P66

P77

P88

P99

P1010

P1111

P1212

P1313

P14 14

P1515

P16 16

P1717

P18 18

P1919

P20 20

P2121

P22 22

P2323

P24 24

P25 25

P2626

J1

HEADER 3

123

U0

16L8

I11

I22

I33

I44

I55

I66

I77

I88

I99

I1011

O119

O2 18

O317

O4 16

O5 15

O614

O7 13

O812

J6HEADER 20

1234567891011121314151617181920

S1

SW PUSHBUTTON

U3

74HCT1284

A11

A22

A33

A44

A57

A68

A79

HD11

DIR10

B120

B2 19

B318

B4 17

Y5 14

Y613

Y7 12

GND 5GND6VCC 15VCC 16

C134.7uF16V

+ C144.7uF16V

+

R11

4.7K

U4

74HCT1284

A11

A22

A33

A44

A57

A68

A79

HD11

DIR10

B120

B2 19

B318

B4 17

Y514

Y6 13

Y712

GND 5GND6VCC 15VCC16

R6

470R

R18 1K

U2

87C52

P3.414 P3.313 P3.212 P3.111 P3.010

P0.2 37P0.138P0.0 39

RST9

X218

X119

VSS20

P1.01

P1.12

P1.23

P1.34

P1.45

P1.56

P1.67

P1.78

P3.717 P3.616 P3.515

VCC40

P2.0 21P2.122P2.2 23P2.3 24P2.425P2.5 26P2.627P2.7 28

P0.3 36

P0.435

P0.5 34

P0.633

P0.7 32

_EA31

ALE 30

_PSEN29

Connectivity and Interoperability Solutions 6


Figure 4-4: Schematic of the daughter board

D12-EVAL-103D 1.1

EPP-SRAM Evaluation Daughter Board

A

2 2Tuesday , July 07, 1998

Title

Size Document Number Rev

Date: Sheet of

VCC

VCC

VCC

VCC

Male

APIC, Philips SemiconductorsDecoupling Capacitors

Chassis

/EPWR/DSTRB

/ASTRB

SD4

SD5

SD6

SD7

SD4SD5SD6SD7

ADR0ADR1ADR2ADR3ADR4ADR5ADR6ADR7ADR8ADR9ADR10ADR11ADR12ADR13ADR14ADR15ADR16ADR17

ADR0ADR1

ADR3ADR2

ADR4ADR5

ADR7ADR6

ADR8ADR9

ADR11ADR10

ADR12

ADR18

/SROE/SRWE

/EPINTR

/EPWAIT

EPUDB2

EPUDB3

EPUDB1

SD0

SD0

SD1

SD1SD2

SD2

SD3

SD3

ADR14ADR15

CNTRINC

SD1SD2SD3

SD5SD6SD7

SD0

/DSTRBINC_ONE

/EPWR/CLK374

SD4

/ASTRB

/DSTRB

/DSTRB/SRWE

/EPWR

/SROE

/ASTRB

/EPWAIT

/RST273

INC_ONE

CLEAR

ADR16ADR17ADR18

ADR13

U8A

74HCT393

A1

CLR2

QA3

QB4

QC5

QD6

U8B

74HCT393

A13

CLR12

QA11

QB10

QC9

QD8

U7A

74HCT393

A1

CLR2

QA3

QB4

QC5

QD6

U7B

74HCT393

A13

CLR12

QA11

QB10

QC9

QD8

C320.1uF

C330.1uF

C310.1uF

U9

KM684000ALG

A012

A111

A210

A39

A48

A57

A66

A75

A827

A926

A1023

A1125

A124

A1328

A143

A1531

A162

CE22

OE24

WE29

D113

D214

D315

D417

D518

D619

D720

D821

VCC32

GND16

A171

A1830

C270.1uF

C280.1uF

C260.1uF

R22

4.7K

U11D

74HCT32

12

1311

U11A

74HCT32

1

23

U12A

74HCT00

1

23

U12B

74HCT00

4

56

U12D 74HCT00

12

1311

U11B

74HCT32

4

56

J13

SUB-D 25_0

13251224112310229218207196185174163152141

U10

74HCT273

D13

D24

D37

D48

D513

D614

D717

D818

CLK11

CLR1

Q12

Q25

Q36

Q49

Q512

Q615

Q716

Q819

U11C

74HCT32

9

108

R23

4.7K

C344.7uF16V

+

R19

4.7K

C294.7uF16V

+ C304.7uF16V

+

R20

4.7K

R21

4.7K

U12C

74HCT00

9

108



4.4 Appendix D: BOM (Bill of Materials)

4.4.1 Main Board’s BOMS/N Item P/N & Description Reference Qty Package Approved Vendors Remark

M.1 PDIUSBD12, Philips USB Interface device with parallel U6 1 DIP28(600 mil) & SO28 PhilipsM.2 PZ5032CSA44, Philips 32 Micro-Cell CPLD U5 1 PLCC44 PhilipsM.3 P87C52UBPN, Philips 8051 compatible Micro-Controller U2 1 DIP40, 600mil PhilipsM.4 74HCT1284D, Philips IEEE1284 buffer U3,U4 2 SOL20, 20-pin plastic PhilipsM.5 ADM222/ADM202 , CMOS RS-232 Driver/Receiver U1 1 SOIC16(ADM202)/SOIC18(A Analog DevicesM.6 16L8-15,PAL device U0 1 DIP20,300 mil Open SourceM.7 6.0 Mhz Crystal, TTL or CMOS Output with 0.01%

Frequency Tolerance, 40-60% Duty CycleX1 1 Thru’ hole ,Low Profile,

Lead’s Pitch =0.3”Open Source

M.8 Push –Button, Normally open S1,S2,S3 3 Thru’ hole Open SourceM.9 Double Pole and Double Thread Switch, DPDT S4 1 Thru’ Hole Open Source

M.10 Green Color LED D1 1 Thru’ Hole, Lead’s Pitch =0.1” Open SourceM.11 Red Color LED D2,D3 2 Thru’ Hole, Lead’s Pitch =0.1” Open SourceM.12 DB 9-pin/Female D-Type/Right angle PCB Mount J3 1 Thru’ Hole Open SourceM.13 DB 25pin/ Female D-Type/Right Angle PCB Mount J2 1 Thru’ Hole Open SourceM.14 RCA Jack for Self Power supply(+5V) J7 1 Thru’ Hole Open SourceM.15 USB B-Type Connector(Upstream) J8 1 Thru’ Hole Open SourceM.16 Single Row, 2-Pin Straight Header, Solder Type J11 1 SIL2, Lead’s Pitch =0.1” Open SourceM.17 Single Row, 3-pin Straight Header, Solder Type J1 1 SIL3, Lead’s Pitch =0.1” Open Source M.18 Single Row,18-pin Straight Header ,Solder Type J9 1 SIL18, Lead’s Pitch =0.1” Open SourceM.19 Single Row, 20-Pin Straight Header, Solder Type J5,J6 2 SIL20, Lead’s Pitch =0.1” Open SourceM.20 Double Row, 10-Pin Straight Header, Solder Type J4 1 DIL10, Lead’s Pitch =0.1” Open SourceM.21 Double Row, 26-Pin Straight Header, Solder Type J12 1 DIL26, Lead’s Pitch =0.1” Open SourceM.22 Ferrite Bead, Multi-layer Chip Bead(10nH) L1,L2 2 1206 Open SourceM.23 18R resistor, 1/10W,+/-1% R7,R8 2 0805 Open SourceM.24 470R resistor, 1/10W,+/-5% R6,R13,R14 3 0805 Open SourceM.25 1.0K resistor, 1/10W,+/-5% R18 1 0805 Open SourceM.26 1.5K resistor, 1/10W,+/-5% R5 1 0805 Open SourceM.27 4.7K resistor, 1/10W,+/-5% R11,R12,R15 3 0805 Open SourceM.28 20K resistor, 1/10W,+/-5% R2 1 0805 Open SourceM.29 1M resistor, 1/10W,+/-5% R9,R10,R16 3 0805 Open SourceM.30 22pF Capacitor, 50V, Multilayer,+/-20% C10 1 0805 Open SourceM.31 68pF Capacitor, 50V,Multilayer, +/-20% C9 1 0805 Open Source



M.32 100pF Capacitor, 50V, Multi-layer, +/-20% C24,C25 2 0805 Open SourceM.33 470pF Capacitor, 50V, Multi-layer, +/-20% C7 1 0805 Open SourceM.34 0.1uF Capacitor, 50V,Multi-layer ,+/-20% C1,C2,C4,C5,C8,C12,C15,C16,

C17,C18,C19,C20,C21,C22,C23,C24,

16 0805 Open Source

M.35 1.0uF Capacitor, 16V, Electrolytic/multi-layer Chip Bead, C11 1 Case “C” Open SourceM.36 4.7uF Capacitor, 16V, +/-20%,Electrolytic/Multilayer C3,C6,C13,C14, 4 Case “C” Open SourceM.37 2-Layer PCB, USB-EPP Main Board, Size 5.3”*4.25” 2 Layers 1 Rectangle ESA

Table 4-10: BOM for main board.

4.4.2 Daughter Board’s BOM S/N Item P/N & Description Reference Qty Package Approved Vendors Remark

D.1 74HCT393, CMOS Dual 4-Bit Ripple Counter U7,U8 2 SOIC14 Open SourceD.2 KM6840000ALG,512K*8Bit SRAM U9 1 32-Pin SOP SamSungD.3 74HCT273 , Octal D-Type Flip-Flop With Reset U10 1 SOIC20 Open SourceD.4 74HCT32,Quad 2-Input OR Gate U11 1 SOIC14 Open SourceD.5 74HCT00,Quad 2-Input NAND Gate U12 1 SOIC14 Open SourceD.6 DB 25pin Male D-Type/Right angle Connector J13 1 Open SourceD.7 4.7K resistor, 1/10W,+/-5% R19,R20,R21,R22,R23 1 0805 Open SourceD.8 0.1uF Capacitor, 50V, Multiu-layer, +/-20% C26,C27,C28,C31,C32,C33 1 0805 Open SourceD.9 4.7uF Capacitor, 16V, Electrolytic or Multi-layer Chip C29,C30,C34 3 Case “C” Open SourceD.10 2-Layer PCB, USB-EPP Daughter Board, Size 1.75” * 2 Layers 1 Rectangle ESA

Table 4-11: BOM for daughter board.

4.5 Appendix E: CPLD VHDL Simulation Waveforms



Figure 4-5: DMA Write-Timing (Reading from EPP and Writing to D12).



Figure 4-6: DMA Read-Timing (Reading from D12 and Writing to EPP)



Figure 4-7: DMA Read-Timing (Reading from D12 and Writing to EPP) with nHOSTDAK inactive during DMA transfer.



Figure 4-8: MCU accessing CPLD and D12 timing.



4.6 Appendix F: CPLD VHDL Source Codes--*************************************************************************---- Project Name :USB-EPP Evaluation Kit-- Chip(CPLD)Name: DMA-EPP Controller-- VHDL Code: EPPDMA.VHD (simplified version for State Machine)-- Target CPLD:PZ5032cs10A44-- Designer: Steven Cheng-- Copy Right: APIC, Philips (Semiconductors) Singapore Pte Ltd-- Last updated:Aug. 17 , 1998-- Version; 1.02--*************************************************************************--library ieee; -- IEEE general Libraryuse ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;--library ASYL; --Philips CPLD library--use ASYL.SL_ARITH.all;--use ASYL.ARITH.all;----------------------------------------------------------------------------entity EPPDMA is port(

CLK : in std_logic; --comman Clock 12MhzRESET: in std_logic; -- high activeDATA: inout std_logic_vector(7 downto 0);-- data busLA: in std_logic_vector(1 downto 0);--latched address busDMARD_WR: in std_logic; -- DMA transfer direction, 1=read from

D12

---D12 Signals -----------D12DREQ: in std_logic; -- D12 DMA requestnD12WR: buffer std_logic; -- D12 WritenD12RD: buffer std_logic; -- D12 ReadnD12DACK: buffer std_logic; -- D12 DMA ACKnD12EOT: out std_logic; -- D12 End of Transfer--SUSPEND: in std_logic; -- Suspend mode

----MCU Signals -----------nMCUWR: in std_logic; -- MCU writenMCURD: in std_logic; -- MCU readALE: in std_logic; -- Address latch EnablenHOSTDAK: in std_logic; -- Host DMA ACK

----EPP Signals

EPPWAIT:in std_logic; -- EPP WaitnDSTROBE: out std_logic -- EPP Data Strobe--nEPPWR: out std_logic; -- EPP Write,);

end EPPDMA;----------------------------------------------------------------------------

architecture behave of EPPDMA is-- LA="00" -> CPLD internal Register Low;-- LA="01" -> CPLD Internal Register High;-- LA="10" -> D12 Data Register;-- LA="11" -> D12 Command Register;

--------State Machine Definition--Trueth Table-- State DELAY1 DELAY0 nD12DACKnDSTROB nD12RD nD12WR-- IDLE 0 0 1 1 1 1-- DMAREAD1 0 0 0 1 0 1-- DMAREAD2 0 1 0 0 0 1

-- DMAWRIT1 0 0 0 0 1 1-- MMAWRIT2 0 1 0 0 1 0

-- DMAEND 0 0 0 1 1 1-- DMAEND1 0 1 0 1 1 1-- DMAEND2 1 0 0 1 1 1-- DMAEND3 1 1 0 1 1 1

----DCOUNT ParametersConstant BITW: integer:= 13; -- Width of CPLD internal Counter-1Constant BITWZERO:std_logic_vector(15 downto (BITW+1)):="00"; --Constant BITWZERO1:std_logic_vector(BITW downto 0):="00000000000011"; -

-Constant BITWZERO2:std_logic_vector(BITW downto 1):="0000000000000"; --

signal DOUT: std_logic_vector (7 downto 0); --Data output--signal DELAY: integer range 0 to 3; --delay cycle for D12 READ

High

signal DIN: std_logic_vector (7 downto 0); --Data Input signal DCOUNT: std_logic_vector (BITW downto 0); --CPLD InternalCounter

signal DMA_ON: std_logic; -- DMA is on Cycle --Aug 8signal RWCLK: std_logic; -- Clock for internal Counter



signal DCZERO: std_logic; -- Counter return to Zerosignal nDSTROB: std_logic; -- EPP Data Strobe

signal DMASTATE: std_logic_vector(5 downto 0); -- State Machine

Constant IDLE: std_logic_vector(5 downto 0):="001111"; --IDLE stateConstant DMAREAD1:std_logic_vector(5 downto 0):="000101"; -- DMA read

state 1Constant DMAREAD2:std_logic_vector(5 downto 0):="010001"; -- DMA read

State 2

Constant DMAWRIT1:std_logic_vector(5 downto 0):="000011"; -- DMA writeState 1

Constant DMAWRIT2:std_logic_vector(5 downto 0):="010010"; -- DMA writeState 2

Constant DMAEND:std_logic_vector(5 downto 0):="000111"; -- Current DMAR/W End

Constant DMAEND1:std_logic_vector(5 downto 0):="010111"; -- Current DMAR/W End



--------------------------------------------------------------------------------

begin

---*****************************************************************************STATE: process (RESET,CLK)begin

if RESET='1' thenDMASTATE<=IDLE;

elsif CLK'event and CLK='1' then-----------------------------------------------

--- State Transition ----- Case DMASTATE is

------IDLE state -------- when IDLE =>

if nHOSTDAK='0' and EPPWAIT='0' then--if D12DREQ='1' and (DCZERO='0' or DCOUNT(0)='1') thenif D12DREQ='1' then

if DMARD_WR='1' thenDMASTATE<=DMAREAD1; --- DMA Read Transfer

elseDMASTATE<=DMAWRIT1; -- DMA write Transfer

end if;end if;

end if;

---DMA read Cycle-----------------------when DMAREAD1 =>

--if EPPWAIT='1' thenDMASTATE<= DMAREAD2; -- Read

--end if;

when DMAREAD2 =>if EPPWAIT='1' then

DMASTATE<= DMAEND; -- Current DMA transfer finishedend if;

-----------------------------------------

---DMA read Cycle-----------------------when DMAWRIT1 =>

DMASTATE<= DMAWRIT2; -- write

when DMAWRIT2 =>if EPPWAIT='1' then

DMASTATE<= DMAEND; -- Current DMA transfer finished

end if;-----------------------------------------

when DMAEND =>DMASTATE<= DMAEND1; -- Current DMA transfer finished

when DMAEND1 =>DMASTATE<= DMAEND2; -- Current DMA transfer finished



when DMAEND2 =>DMASTATE<= DMAEND3; -- Current DMA transfer finished

when DMAEND3 =>if nHOSTDAK='0' and EPPWAIT='0' and D12DREQ ='1'

and (DCZERO ='0' or DCOUNT(0)='1') then

if DMARD_WR='1' then --DMASTATE<= DMAREAD1; -- Continue the Burst read mode

else --DMASTATE<= DMAWRIT1; -- continue the Burst Wrire Mode

end if;

elsif EPPWAIT='0' then

DMASTATE<= IDLE; -- Idle state

end if;

when OTHERS => end case;

end if;

end process STATE;---*****************************************************************************

---Internal Counteroperation***************************************************counter: process(RWCLK,RESET)begin

if RESET='1' thenDCOUNT(BITW downto 0) <= BITWZERO1; -- Init value

elsif RWCLK'event and RWCLK='1' thenif DMA_ON ='1' then -- DMA on Cycle DCOUNT<=DCOUNT-'1'; --after transfer one byte , counter -1

else -- DMA off Cycle

case LA is -- Address inputwhen "00" => -- Address 00

DCOUNT(7 downto 0) <=DIN(7 downto 0); -- Counter Low Byte

when "01" => -- Address 01DCOUNT(BITW downto 8) <=DIN((BITW-8) downto 0);--Counter High

Byte

when others =>

end case;end if;

end if;end process counter;---*****************************************************************************

---*****************************************************************************---*****************************************************************************--Data bus for read/write from/to internal counterDOUT<= DCOUNT(7 downto 0) when LA="00" else

BITWZERO & DCOUNT(BITW downto 8) ;

--- Decoding Logic -----------------------------------------States and D12 control signals and EPP signals -----

nD12DACK<=DMASTATE(3);-- D12 DMA Ack

-- Internal Dstrobe signalnDSTROB<=DMASTATE(2);-- Internal /DSTROBE

-- External Dstrobe signalnDSTROBE<=DMASTATE(2) when DMA_ON='1' else 'Z';

--- D12 read/Write controlnD12RD <=DMASTATE(1) when DMA_ON='1' else nMCURD;--nD12WR <=DMASTATE(0) when DMA_ON='1' else nMCUWR;--

----EPP Write signals -------nEPPWR<= not DMARD_WR when DMA_ON='1' else 'Z' ;



----DMA End of Transfer Signal ----nD12EOT <='0' when nDSTROB='0' and DCZERO='1' and DCOUNT(0)='1' else

'1';

---- Counter decreasement or preser(load) Clock-----RWCLK<='0' when (nDSTROB='0' and nD12DACK='0') or

(nMCUWR='0' and nD12DACK='1') else '1'; --

---Control return to 0/1 control ------ DCZERO <='1' when DCOUNT(BITW downto 1) = BITWZERO2 else '0';

----Data Input/output Bus control ------DIN <= DATA;DATA <= DOUT when nMCURD='0' and ALE='0' and LA(1)='0' else "ZZZZZZZZ";

---DMA_On means that DMA Cycle is carrying on even nHOASTDAK is highDMA_ON <='0' when (nHOSTDAK='1' and nD12DACK='1') else '1';

---------------------------------------------------------------------------end behave;

4.7 Appendix G -

Main Board’s PAL (16L8) EquationsAs the 32 micro-cells CPLD is not enough to fit the following PAL equations, oneadditional PAL device (Lattice or AMD PAL18L8) is used to implement this simplecoding. The related signals (inputs/outputs) are contained in Figure3-4. The equations areas follows:

Name USBEPp;Partno CA0016;Date 06/07/98;Rev 01;Designer Steven Cheng;Company Philips Semiconductors ;Assembly None;Location None;Device g16V8;

/****************************************************************//* *//* USB-EPP Evaluation Board decoding *//* *//****************************************************************//* Allowable Target Device Types : PAL16L8 *//****************************************************************//** Inputs **/Pin 1 = D12DREQ;/* D12 DMA request *//*Pin 2 = DMA_ON;*/Pin 3 = D0; /* Data Bus D0 */Pin 4 = D1; /* Data Bus D1*/Pin 5 = SUSPEND; /* D12 Suspend Mode */Pin 6 = ASTROBE;/* EPP ASTROBE */Pin 7 = HOSTDAK;/* Host DMA ACK */Pin 8 = EPPWR; /* EPP Write */Pin 9 = DSTROBE;/* EPP DSTROBE */Pin 11 = ALE; /* ADdress Latch */

/** Outputs **/pin 12 = D12CS;/* D12 Chip select */Pin 13 = HOSTDREQ; /* Host DMA Request *//*Pin 14 = DSTROBE; EPP nDSTROBE, MCU Control */Pin 15 = LA0; /* Address A0 */Pin 16 = LA1; /* Address A1 */pin 17 = SHDN; /* ADM222 Shut down */Pin 18 = EPPDIR; /* /* EPP 1284 buffer direction control */ Pin 19 = D12A0; /* D12 Address A0*/

/*pin 19 = */

/* Adder-slice circuit - add 2, 1-bit, numbers with carry *//* Perform 4, 1-bit, additions and keep the final carry */

LA0 = (D0 & ALE) # (LA0 & !ALE) ;LA1 = (D1 & ALE) # (LA1 & !ALE) ;HOSTDREQ = D12DREQ;D12A0= LA0 & LA1 & !ALE ;!D12CS = LA1 & !ALE & HOSTDAK;!SHDN= SUSPEND;EPPDIR = (EPPWR & !DSTROBE) #(HOSTDAK & EPPWR & !ASTROBE) ;

Connectivity and Interoperability Solutions Page 25.../INIT /SELECTIN /EPPINIT /PINIT PE /INIT...

Documents

Transcript of Connectivity and Interoperability Solutions Page 25.../INIT /SELECTIN /EPPINIT /PINIT PE /INIT...