CONFIDENTIAL Task 5.2: Demonstrator design, implementation and characterization Objectives: develop...
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Transcript of CONFIDENTIAL Task 5.2: Demonstrator design, implementation and characterization Objectives: develop...
CONFIDENTIAL
Task 5.2: Demonstrator design, implementation and characterization
Objectives: develop and implement demonstrator chips related to the major activities carried on the other work-packages
Activities as described in Technical Annex:
Test-chip activities: – Level shifter circuits, basic circuits implemented with regular layout (UPC)– PV aware and lifetime-critical circuits (TUGI)– Substrate noise (NXP)– PV aware monitors/controls for self-timed logic (LETI)– compensation schemes for critical AMS blocks (IFXA)
Simulation & characterization activities:– variability-tolerant low noise / low emission circuits (TMPO)– Calibrate timing analysis flow (NXP)– Robust parallel computing architectures by design of demonstrator like mic
rocontrollers and realize VHDL model (THL)
1MODERN General MeetingsCatania, Nov. 9 & 10, 2010
CONFIDENTIAL
Task 5.2: Demonstrator design, implementation and characterization
Review
2MODERN General MeetingsCatania, Nov. 9 & 10, 2010
CONFIDENTIAL
Task 5.2: Demonstrator design, implementation and characterization
Purpose of demonstrators (to be aligned during WP5 meeting)
Test-chip activities: – (UPC) demonstrate on-chip sensors, level shifters, prove benefits of
circuits with regular layout, digital and RF M&C? (T4.1, T4.4, T3.3)– (TUGI) develop benchmark circuits and validate aging models (T2.5)– (NXP) verify full-chip substrate analysis (T3.4?)– (LETI) verify AVFS (T3.3 timing errors, WP4control), full demo chip– (IFXA) verify M&C concepts T3.3, provide recovery/aging variations
data T3.3
Simulation & characterization activities:– (TMPO) verify variability tolerant low-noise / low-electromagnetic-
emission delay-insensitive asynchronous circuits WP4 – (NXP) Calibrate timing analysis flow ???– (THL) verify fault tolerant multi-core chip WP4
3MODERN General MeetingsCatania, Nov. 9 & 10, 2010
CONFIDENTIAL
Task 5.2: Demonstrator design, implementation and characterization
Innovative aspects of demonstrators
(to be clarified during WP5 meeting)
Test-chip activities: – (UPC) – (TUGI) – (NXP) – (LETI) – (IFXA) innovative M&C concepts (T3.3), novel aging test and
characterization methods
Simulation & characterization activities:– (TMPO) variability tolerant circuits?– (NXP) – (THL)
4MODERN General MeetingsCatania, Nov. 9 & 10, 2010
CONFIDENTIAL
Task 5.2: Demonstrator design, implementation and characterization Deliverables
Deliverables:
R: Basic concept verification of noise, compensation, test chip architectures (NXP, IFXA) M12 (03/2010) approved
R: Test chip simulation results, topology, implementation and evaluation strategy, VHDL models; IP block design and layout for the different technologies CMOS (digital AMS&RF), SOI, etc. and technology nodes
(TMPO, NXP, IFXA, UPC,THL, LETI, TUGI) M27 (06/2011)
R: test chip characterization (evaluation to show effectiveness of PVT circuitry, of basic processing circuits implemented with regular layouts,), calibration of PV robust analysis flows
(TMPO, UPC, NXP, IFXA, LETI, TUGI) M36 (03/2012)
5MODERN General MeetingsCatania, Nov. 9 & 10, 2010
MODERN. WP5 Status - UPC
MODERN General meetingCatania
November 9th, 2010
UPC in relation with T5.2
Several UPC tasks will produce output susceptible to be a demonstrator chip
T3.3 PV-aware design– Highly tolerant dgital design– monitor & control of RF
T4.1: Variability-aware design– D4.1.2 “Tape-out of prototype on-chip sensors and level shifter
circuits for (self-) adaptive design.”
T4.4: Design of regular architectures for high manufacturability and yield
– D4.4.2 “Tape-out of a chip based on regular transistor arrays.”
T3.3 – Tolerant redundant circuits: Turtle logic
Described in D3.3.1 (M12)– Initially inspired in probabilistic logic
Signal redundancy in all nodes Inherently robust against logic discrepancies in complementary signals
– In sequential circuits, state transition stopped when there is a discrepancy Current status:
– redundant signal sequential architecture already defined– Application example designed at gate level: multiplier 4x4
Next steps:– Gate-level simulation and evaluation (D3.3.2)– Physical design to evaluate area, timing, power (D3.3.3)
T3.3 - PV monitor and tolerance
Purpose: design and implement a RF front-end tolerant to PVT variations, under the constraint of low-power consumption .
RF front-end with a Low Noise Amplifier, Mixers and auxiliary circuitry for PVT variations detection and compensation (bias circuits, detectors, control circuitry, control loops).
Thermal monitoring will be also considered as innovative detection technique of PVT variations, integrating on chip a differential temperature sensor.
Status:– Preliminary block diagram of the proposed
test chip (not indicated possible on-chip sensors for Built In Test (BIT))
THERMAL
COMPENSATION
SUPPLY
COMPENSATION
SUPPLY
COMPENSATION
T4. 1 - Monitor and adaptation
ABB and AVS demonstration to control leakage or delay– Leakage depends both on VDD and VBS– Delay depends especially on VDD
Current status:– Evaluation of type of sensors
In terms of design complexity and parameter yield to improve
Relation/Potential collaboration with LETI– Sensors based on delay– At schematic/circuit only (different target technology)– Upcoming meeting to define collaboration and excahnge
information
T4.4 - VCTA application for variation impact of regularity
Design of Voltage Controlled Delay Line (VCDL) and DLL
T4.4 - Jitter and mismatch
Jitter in DLL dependent on mismatch Sources for mismatch
– Random dopant fluctuations, Interface roughness, etc.
– Lithography interactions between neighboring patterns
Regular design expected to present smaller jitter
T4.4 - Experiment proposal
Design regular (VCTA) and irregular layouts of DLL If size of transistors is large enough, mismatch
dominated by neighborhood effects Design several versions with different transistor
sizing The relative importance of regularity vs random
mismatch will be obtained D4.4.2: Tape-out of chip based on regular transistor
arrays (M30)
Summary UPC
Designs that are well on-track– RF monitoring and compensation (T3.3)– VCTA regular impact experiment (T4.4)
Designs that need extra effort– Digital PV-aware (T4.1)– Turtle logic (T3.3)– At this point in time fully confident they can be part of T5.2
Remarks/Questions– Technology: ST 65nm– Use of CMP reserved budget; which conditions? One chip?
submission date limit?
BACK
CONFIDENTIAL 15MODERN General MeetingsCatania, Nov. 9 & 10, 2010
Motivation & Technology Task 5.2 - TUG
The overall motivation is to verify physical reliability models including process variability reflecting the performance of MOS transistors over lifetime resulting from WP2.
The goal of Task 5.2. is to determine demonstrator circuits sensitive to the observed degradation effect in order to allow the benchmark of different aging model development approaches.
Technology:
The entire work is based on austriamicrosystems AG HVCMOS technology.
CONFIDENTIAL 16MODERN General MeetingsCatania, Nov. 9 & 10, 2010
Status of Work Task 5.2 - TUG
Verification of simple Isub based analytical model
in order to support the validation of possible benchmark circuits by including the models into a reliability simulator.
nC
sub tW
ICP
2
1
Elaborate approaches to incorporate the PV into the models.
Close cooperation with TUV which is working on physical PV aware reliability models based on TCAD and measurement results.
CONFIDENTIAL 17MODERN General MeetingsCatania, Nov. 9 & 10, 2010
Principle of Reliability Simulator Task 5.2 - TUG
The principle of the reliability simulation is to represent the device degradation at different points in time (e.g. after 10 years) by updating specific SPICE parameters.
The SPICE deck is updated via a dynamic link between the analog simulator and the reliability simulator.
CONFIDENTIAL 18MODERN General MeetingsCatania, Nov. 9 & 10, 2010
Outlook Task 5.2 - TUG
Design and fabrication of benchmark structures.
Validation of proposed benchmark cases.
Outstanding deliverables:– D5.2.2 – M27– D5.2.3 – M36
VERIFICATION:BENCHMARK CASES vs. MEASUREMENTS
CASE_1 CASE_2 CASE_3 ……….…. CASE_N
SPECIFYBENCHMARKS
PRIMARYSIMULATION,DESIGN AND
LAYOUT
FABRICATION OF
BENCHMARKSTRUCTURES
DO MEASUREMENTS AGREE WITH THE RESULTS FROM
SIMULATION?
FIND OUT WHY
BENCHMARKCASE
OK
NO YES
STRESS
Benchmark Structures
Benchmark Cases
Rel. Simulator
Hu derivative
Rel. Simulator
TUV analytical
model
MINIMOS-NTReliability
WC models
hierarch
ically structu
red
Structure 1 ☺/X
Structure 2
Structure 2
Structure 4
etc.
BACK
Substrate activities for Modern Task 3.4
Sergei Kapora
29 October 2010
2010
CONFIDENTIAL 20
Neptune 314 for substrate noise studies
8 digital IPswith different isolation approaches
Developed de-embedding schemeto remove contribution of IO coupling
Correlation of de-embedded measurementresults with 3rd-party EDA tool for full-chip
substrate noise analysis
2010
CONFIDENTIAL 21
Neptune 5 test chip specs
Aggressor(IO or digital)
Victim(FM LNA)
isolation isolation
propagation
Control equipmentDigital pattern generator
Spectrum analyzer
Neptune 5
PCB analog pads
Victim 1
Digital pads
Shiftregister 1
Aggressorsettings
anal
ogpa
ds
Dig
ital p
ads
Victim 2
Victim 3
Victim 4
Victim 5 Victim 6 Victim 7
Shiftregister 3
Shiftregister 2
Shiftregister 4
Victimsettings
Spectrum of the output of FM bufferwith and without digital noise present in the system
Current floor plan proposal
2010
CONFIDENTIAL 22
Substrate extraction flow in SOI
Layout Schematic
LVS
QRCQRC Rules
InternalDatabase
Extracted View
Circuit simulation
Substrate Abstract View
SubstrateTech File
LVSRules
Reduction
*functionality in red isadded to the standard flow
Disturbed output of the bandgap due tonoise propagation through the substrate
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