CON-TACT® Planarization Process of Spin-on Dielectrics for Device Fabrication Wu-Sheng Shiha

CON-TACT® Planarization Process of Spin-on Dielectrics for Device Fabrication

Wu-Sheng Shiha, Jiro Yotab, and Ketan Itchhaporiaa aBrewer Science, Inc., 2401 Brewer Drive, Rolla MO 65401, USA

bSkyworks Solutions, Inc., 2427 W. Hillcrest Drive, Newbury Park, CA 91320, USA

Planarization has become a necessity for fabricating devices, large and small. Without planarization, a limited number of layers of interconnects or device structures can be successfully fabricated. CON-TACT® planarization technology has been used to planarize various spin-on dielectric materials to provide both local and global planarity. Materials such as epoxies, anti-reflective coatings, photoresists, spin-on glass, CycloteneTM, polybenzoxazole, and polyimide have been successfully planarized with up to more than 98% topography reduction. Consequently, the overburden variation was reduced. The planarization performance obtained promises great potential for this technology to provide more consistent, more reliable and otherwise improved device performance for more sophisticated device designs with higher yield.

Introduction

Fabricating devices, such as semiconductor, optical, optoelectronic, photonic, microelectromechanical systems (MEMS) devices, involves numerous complex steps and processes, materials, and equipment (1). For most of the devices, multiple layers of structures are fabricated sequentially on the device substrate. Each step, process, material and piece of equipment used needs to be nearly perfect to ensure an economically acceptable final device yield. Among the fabrication processes, the planarization process plays a critical role for successful device fabrication. There are two main planarization schemes, categorized by the material to be planarized: dielectric planarization and metal planarization (2).

Device fabrication typically starts with a flat surface. However, the surface becomes non-planar shortly after the fabrication process is started. As the first layer of structures is fabricated onto the substrate, this layer of topography is introduced onto the substrate surface. Such topography compromises the processing latitude of the subsequent processing step, which could lead to the device failure (2). If the topography is not removed, the topography worsens as additional layers of structures are fabricated atop. Eventually, the topography becomes severe enough that it limits the number of layers of functional and reliable structures that can be fabricated (3). The topography plays an even more profound role for advanced devices that contain multiple layers of sub-micron or finer structures. Therefore, a number of planarization technologies have been developed to reduce or eliminate the topography in device fabrication processes. Such technologies include etch-back processes (4-7), chemical mechanical polishing (CMP) (8-9), spin-coating film transfer and hot pressing (STP) (10-14), press planarization (15-17) and CON-TACT® planarization (18-24). Ideally, both local and global planarization are required on a planarized surface for advanced multilayer device fabrication (25).

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The etch-back process is typically performed by spin coating a thick coating of photoresist (4) or spin-on glass (SOG) (5-7) on top of the topographic surface to be planarized. The photoresist or SOG coating tends to conform to the underlying topographic surface and provides surface smoothing with a reduced topography. The thicker the overcoat (or multilayer coat), the less the surface topography. Subsequently, a plasma etch process is performed to remove the overcoat and to transfer the reduced topography to the underlying material. The plasma etch selectivity (etch rate ratio) between the coated photoresist (or SOG) and the underlying material needs to be nearly 1:1 when both are etched simultaneously. In this method, the resulting surface topography is dependent on the pre-etch surface topography and etch selectivity. Furthermore, the micro-loading effect also needs to be taken into consideration during etching (26). Different chemistries and parameters may be needed during different stages of plasma etching, including when etching the over-coated material only and when etching both the over-coated and underlying materials simultaneously (26). As the device design becomes more complex and the device structures become smaller, a small amount of topography on the surface could cause device failure and result in unfavorable and significant yield loss (2). Therefore, advanced planarization technology is required in order to meet this challenge.

Although it has existed for thousands of years, CMP still was a revolutionary and

innovative planarization technology when it was introduced to semiconductor device fabrication (8-9). In the past decade, CMP has been and continues to be the predominant technique used to planarizing topographic surface for sub-micron silicon-based semiconductor integrated circuit fabrication. There are many designs and approaches for CMP technology which involve different materials, processes, and types of equipment. The interactions between the materials (the materials to be planarized, the slurry, and the polishing pad used), the process, and the equipment design are critical for achieving the desired planarization.

Basically, CMP relies on mechanically polishing the topographic surface against a

polishing pad. During polishing, slurry loaded with abrasive particles along with appropriate additives fills in between the topographic and pad surfaces to mechanically and chemically assist with the removal of the polished surface. Areas of the surface with the high topography experience higher pressure, and therefore more mechanical grinding, during polishing. Therefore, the rate of removal in areas of higher topography is higher compared to the removal rate in the lower areas, and thereby reducing the surface topography. However, the distribution, population, and dimension of the topography on the surface could create a major complication for achieving the planarity of the polished surface. Such a phenomenon is known as “feature density effect” (27). At the end of the CMP process, a certain level of topography exists between the area heavily populated with structures (high feature density area) and the area without or sparsely populated with structures (low feature density area). At this certain stage, longer CMP processing time will not reduce the topography any further. Another challenge for CMP is the occurrence of erosion and dishing when two different materials are polished simultaneously (28-29). Furthermore, the uses of CMP on brittle substrates (such as the compound semiconductors GaAs, InP, etc.) and on devices with large structure sizes and high topography (such as MEMS) have been a technical and economical challenge. Additionally, planarizing polymeric dielectrics, which are used widely in device

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fabrication, with CMP has proven to be challenging (30). Therefore, alternative planarization technologies are needed for various applications.

Another method of planarization technology, STP (spin coating film transfer and hot

pressing), was first proposed and developed by Machida et al. (10-14). In this process, SOG is first coated onto a polytetrafluoroethylene (PTFE) base sheet film. The coated base film is then heated and pressed against the silicon wafer surface containing interconnects (topographic structures) in a vacuum environment. The dielectric is forced to fill gaps between interconnects and maintains the global planarity of the pressed SOG surface on top of the topographic silicon surface. The base film is then peeled off the pressed SOG surface to transfer the dielectric film from the base film to the silicon wafer.

One of the most promising methods to planarize topographic surfaces is press

planarization technology. The concept of press planarization technology was first demonstrated by Prybyla and Taylor (15-17). This technology was further explored for its applicability to a variety of specific applications by Brewer Science, Inc., with its CON-TACT® planarization technology (18-24). The CON-TACT® planarization process utilizes external force to bring an optically flat surface in physical contact with flowable materials. The surface planarity is replicated from that of the optically flat surface to the planarized flowable material surface, which is then hardened and is separated from the pressing surface. This planarization technology is a wafer-scale process that achieves local and global planarity in one process.

CON-TACT® Planarization Technology

In this study, various spin-on dielectrics such as epoxies, anti-refractive coatings, photoresists, spin-on glass (SOG), CycloteneTM (trademark of The Dow Chemical Company; B-staged bisbenzocyclobutene (BCB)), polybenzoxazole and polyimide have been planarized using CON-TACT® technology.

Materials Characterizations

Prior to planarizing these spin-on materials, characterizations are performed in order to understand their flow properties and to identify appropriate planarization conditions. A Cee® 100CB (from Brewer Science, Inc.) was used to spin coat the material with various spin speeds to create a spin curve for identifying appropriate parameters to obtain desired thicknesses. The material flow properties were measured using a TA Instruments AR2000 advanced rheometer. The material viscosities, after solvent removal (if necessary), were measured as the temperature of each material was elevated to understand the temperature dependency of each material’s viscosity. A TA Instruments DSC 2920 modulated differential scanning calorimeter (DSC) was used to determine the glass transition temperatures and melting points of the polymeric dielectric materials. Such information assists with the determination of the planarization processing temperature for different planarization materials. Some of the materials are monomeric or oligomeric, or are low molecular weight materials. They are flowable at room temperature (prior to curing). However, some of the materials must be processed at elevated temperatures in order to provide satisfactory flow properties for planarization.




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The elevated temperature for each material should not exceed the temperature at which the planarization and underlying material properties change. For some materials, such as some polyimides and polybenzoxazoles, residual solvent plays an important role in facilitating the material flow during planarization. The removal of this residual solvent after planarization, could result in the increase of the step height. In some cases, a final curing step after planarization of the polymer may be needed. If the material shrinks during this step, it is inevitable that the step height could increase.

CON-TACT® Planarization Process

The process for CON-TACT® planarization technology is very straightforward and is illustrated in Figure 1. The process starts with a substrate that has a topographic surface as shown in Figure 1(A). A planarization material is applied, typically using a spin coating technique, to the topographic surface to fill the topographic recessed areas, such as trenches and vias. Unless the surface is coated with a very thick coating, as compared to the topographic structure height, the coating will conform to the underlying topographic structures and will still leave significant surface topography, Figure 1(B). This topography could be as severe as that of the original topographic substrate. To remove the topography, an anti-stick optically flat surface is brought into contact with the coated planarization material surface, Figure 1(C). Sufficient pressing pressure at appropriate conditions, such as temperature and tool chamber pressure, is applied to the optically flat object and the substrate to force the planarization material to flow into the recessed areas. Eventually, all the recessed areas are filled with the planarization material, Figure 1(D). Therefore, the planarization material is forced to comply with the planarity of the optically flat object’s surface. The planarization material is hardened (or cured) by either photo-radiation or thermal method. The optically flat surface, with its anti-stick characteristics, is then separated from the hardened planarization material surface, Figure 1(E). The result is that the planarity of the optically flat object’s surface is duplicated on the hardened planarization material surface, which provides the local and global planarity needed for subsequent processing.

In this study, device or topographic wafers were coated with a certain thickness of the

planarization material using the spin-coating method identified in the previous section. These wafers were processed using the CON-TACT® planarization process based on predetermined parameters for each material. These wafers were referred to as “planarized” wafers. For performance comparison, device or topographic wafers were coated with the planarization materials with the identical process used for the “planarized” wafer. These wafers were placed into the planarization chamber to experience the identical processing as the other wafers but excluding the CON-TACT® planarization step. These wafers were referred as “reference” wafers. For the thermal CON-TACT® planarization process, the reference wafers were sometimes referred as “thermal reflowed” wafers. Because both the planarized and the reference wafers experienced almost identical thermal history and process environment, their planarization performance comparison would be more meaningful. Planarization Performance Characterizations




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(A) Start with topographic substrate

(B) Apply planarization material

(C) Apply pressure to planarize the applied flowable planarization material with an optically flat surface under appropriate conditions.

(D) Harden the planarized material either by photo-radiation or

thermal method.

(E) Separate the optically flat object from planarized material and leaves an optically flat surface on the planarized material surface.

Figure 1. A representative process scheme of CON-TACT® planarization technology.

The original device topographic and processed wafers were characterized for surface

step height (topography) with a Dektak® 8 stylus profiler and a Wyko NT3300 optical profiler, both from Veeco. A NanoSpec 6100 (Nanometrics Incorporated) film analysis system having a 25-µm measuring laser beam diameter was used to measure the film

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thicknesses and overburden (film thickness on top of a topographic structure). A Leo model 1560 (from Leo) scanning electron microscope (SEM) and an FEI model 820 (from FEI) dual beam focused ion beam scanning electron microscope (FIB/SEM) were used to provide top-down and cross-section views of the processed wafer characterizations.

CON-TACT® Planarization Performance

Planarization performance can be primarily evaluated by how effective the topography is reduced. The topography prior to and after planarization of each material is evaluated. The percentage of topography reduction (or planarization improvement) is expressed as Degree of Planarization (DOP, or % planarization) and can be calculated as following (31).

DOP (% planarization) = (1 – (T'/T)) x 100 [1]

where T' is the step height over a topographic structure after planarization, and T is the initial topographic structure step height prior to planarization, as illustrated in Figure 2. A perfect planarization has a DOP of 100%, where T' equals 0 and the topography over the topographic structure is eliminated after planarization.

Figure 2. A diagram of the components related to the degree of planarization.

Surface planarity is the primary factor for determining the planarization performance. However, thickness uniformity of the planarized film is also critical for successful subsequent processing. A planarized film can be very planar but it may exhibit a wedge-like shape caused by an improper planarization process. Therefore, film thickness non-uniformity also needs to be characterized. Typically, the within-die non-uniformity (WIDNU) and the within-wafer non-uniformity (WIWNU) characterizations are performed to evaluate the thickness non-uniformity. The definitions of and methods for determining these thickness non-uniformities are given and discussed elsewhere (32).

CON-TACT® planarization performance was evaluated using 6-inch SKW 1-1

dielectric oxide CMP test wafers (purchased from SKW Associates, Inc.) that have line feature densities ranging from 0% to 96% within a 12 mm x 12 mm die (33). The line structures have a step height of about 0.9 to 1.0 µm and a fixed pitch width of 250 µm.

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The feature density is defined as the line width divided by the pitch width. A layout of the die is shown in Figure 3.

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(B) Figure 3. SKW 1-1 dielectric oxide CMP test wafer (A) stack structure and (B) die floor plan with various feature density sub-cells (33, used by permission).

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Photo CON-TACT® Planarization Processing

A photocurable novolac epoxy material was spin-coated onto the test wafer to a thickness of approximately 1.5 µm. The coated wafer was placed into the CON-TACT® planarization chamber with predetermined parameters for planarization. The wafer was planarized, and the planarized epoxy material was cured using UV radiation. As a reference, another wafer was prepared using identical spin coating parameters and cured without undergoing the planarization step. Surface step heights on various density areas were measured and shown in Figure 4. It is evident that with an approximately 1.5-µm thick coating, a step height of about 200 Å or less was achieved on the planarized wafer, regardless of the feature density. These results indicate that a DOP of 98% or greater was accomplished with CON-TACT® planarization technology and that the feature density variation has a very minimal impact, if any, on the post-planarization step height. On the other hand, the reference wafer still has a step height of nearly 10,000 Å (1.0 µm), which is the original step height of the test wafer. These results show that application of a 1.5-µm thick novolac epoxy film alone is not sufficient to significantly reduce the 1.0-µm topographic line structures with 250-µm pitch.

Figure 4. Step Height measurements on various feature density areas of a photocurable novolac epoxy coated reference wafer (♦) and a photocurable novolac epoxy coated wafer planarized using the CON-TACT® planarization process ( ).

Film thicknesses within a die and within a wafer were measured using a Nanospec

6100 (Nanometrics Incorporated). The WIDNU and WIWNU were calculated using the measured film thickness. A WIDNU of less than 3% was constantly achieved. In some instances, less than 1% WIDNU was observed. The WIWNU study indicated that 3% thickness non-uniformity across the wafer was consistently achieved. Figure 5 shows the film thickness map across a planarized wafer with a WIWNU of about 1.6%. With optimized planarization parameters, a WIDNU of less than 1.5% and WIWNU of less than 2% can be achieved.

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Figure 5. A normalized film thickness map across a 6-inch SKW 1-1 test wafer using a film of about 1.5 µm of photocurable novolac epoxy and planarized using CON-TACT® planarization. WIWNU is about 1.6%. The film thickness indicated is normalized by the average thickness. Thermal CON-TACT® Planarization Processing

The planarization performance of CON-TACT® planarization was also evaluated using a thermal planarization process. CycloteneTM was used to planarize the 6-inch SKW 1-1 test wafers. The planarization process utilized the material flow property within different temperature ranges. The coated CycloteneTM material (~1.5-µm thick) was planarized at elevated temperature and hardened at low temperature. Even though the material has a very good thermal reflow planarization property, the 1.5-µm thick CycloteneTM alone was not able to provide acceptable planarity across various feature density areas within a die (Figure 6). With CON-TACT® planarization, the step height was reduced from almost 10,000 Å (1.0 µm) for the reference wafer to about 300 Å or less. These results correspond to a step height reduction of over 97%, or a DOP of 97% or greater. It is also evident that feature density has a very minimal effect on the post-planarization step height. These results show that the planarization performance for both photoradiation-based and thermal processing are consistent and comparable to each other.

Lithography Application

Lithography processes are critical in defining the structures for device fabrication. Advanced lithography technologies, such as photolithography and imprint lithography, have being prone to device failure caused by surface topography. Such topography could

1.02-1.04 1.00-1.02 0.98-1.00 0.96-0.98




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Figure 6. Step height measurements on various feature density areas of a planarized CycloteneTM-coated reference wafer (♦) and a CycloteneTM-coated wafer planarized using the CON-TACT® planarization process. be created during the many fabrication process steps. It could also be intentionally generated as part of the fabrication process, such as the dual damascene (DD) process (34). The presence of topography will consume the photolithography process depth of focus (DOF) budget. In addition, the thicknesses of the photo-imaging layers, anti-reflective coating, and photoresist vary over different topography structure areas, which create another form of feature density effect. Such thickness bias not only creates tremendous complications for the photolithography process, but it also poses great challenges for subsequent processing. Therefore, various planarization techniques were developed to reduce the topography and the thickness bias, including planarizing the anti-reflective coating, with CON-TACT® process (20), CMP (35), and multilayer coating approaches (36-42).

Advanced photolithography processes require thin layers of an anti-reflective coating and a photoresist to be coated onto the substrate surface (36-37). However, the thin anti-reflective coating and photoresist layers tend to conform to the underlying topography, similar to Figure 1(B), and are not sufficient to provide the planarity needed for photolithography. With appropriate conditions, CON-TACT® planarization has successfully planarized such topography (20). Films of 193-nm bottom anti-reflective coating (BARC) with different thicknesses, 0.1 µm and 0.25 µm, were coated onto wafers of various diameters and feature densities of 1.0-µm deep vias. Cross-section SEM images showed that although the 0.25-µm vias in the isolated feature density areas were fully filled, the vias in the dense feature density areas were not fully filled with BARC, as shown in Figures 7(A) and 8(A). Upon the application of the appropriate thermal CON-TACT® planarization process, all the vias in isolated and dense feature density areas were fully filled with BARC without any voids or bubbles, as shown in Figures

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Figure 7. SEM photos of the ~0.1-µm BARC coating on isolated (left) and dense (right) 0.25-µm via areas for (A) a reference wafer and (B) a planarized wafer (20).

Figure 8. SEM photos of the ~0.27-µm BARC coating on isolated (left) and dense (right) 0.25-µm via areas for (A) a reference wafer and (B) a planarized wafer (20). 7(B) and 8(B). Figure 7 clearly shows that the planarization process has successfully forced the BARC material to flow from isolated areas to dense areas to fill the vias. As shown in Figure 8(A), the BARC thickness on the isolated area was about 0.27-µm, while the isolated areas were not fully filled, which represents a film thickness bias of greater

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than 0.27-µm for the reference wafer. However, the planarized wafer showed a film thickness bias of about 0.04 µm, as shown in Figure 8(B). The BARC thickness bias was significantly reduced from greater than 0.27 µm to about 0.04 µm.

The photolithography process was performed on the reference and planarized wafers with the designed baking temperature and time using a 193-nm BARC having a thickness of ~0.1-µm. These wafers were then coated with Arch Chemical GAR8105G1 193-nm photoresist. An ASML PAS5500/1100 193-nm exposure tool was used to image the photoresist using a standard photolithography process. SEM characterization revealed that it was possible to image 100-nm line structures across via areas only on the planarized wafer, as shown in Figure 9.

Figure 9. SEM photos of 100-nm lines patterned on a 0.22-µm via area on (A) a spin-coated BARC (reference) wafer and (B) a planarized BARC wafer that has undergone a post-planarization bake (20). Photoresist Planarization

Photoresist has been used to spin coat and planarize topographic surfaces (4).

However, such a technique provides limited planarization performance, especially for large and high topographic structures for MEMS, waveguides, and other applications.

For this study, a wafer with a group of trenches that were ~15 µm deep 250 µm wide

with 100-µm spaces (Figure 10) was coated with ~15 µm of SU-8 (purchased from Microchem) and planarized with a thermal CON-TACT® planarization process. For comparison, another wafer was prepared by coating with the same thickness of SU-8 and thermally reflowing with identical thermal history as that of the planarized one, without undergoing the planarization step. Surface topography characterization, as shown in Figure 11, indicates that the thermal reflow process only reduced the topography to about 11 µm. However, the planarized wafer has topography of less than 1 µm. Part of this 1.0-µm topography was the result of the thermal expansion and shrinking that occurred during the thermal processing. The evaporation of the residual solvent from the planarized coating could also increase the topography. Considering the size, topography, and total dimension (3775 µm x 5240 µm, Figure 10) of the group of trenches and the 1X thickness of the coated material, this level of planarization performance cannot be delivered with traditional photoresist planarization process. Another test on a cross-structure (consisting of two 390 µm x 1400 µm trenches with ~15-µm topography) using

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SU-8 at a thickness of ~15 µm showed a surface topography of ~0.25 µm after planarization, as opposed to ~15-µm topography after thermal reflow (reference).

Figure 10. The layout and dimension of a group of trench structures used for the photoresist planarization process. The topography of these test structures is about 15 µm.

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Figure 11. Step height surface scans of the ~15-µm original topographic trench structures, the thermal reflowed ~15-µm reference wafer coated with SU-8, and the ~15-µm wafer coated with SU-8 and planarized.

The CON-TACT® planarization process has also been used to planarize topographic

structures using a ~3-µm film of Shipley S1818 photoresist for MEMS device fabrication (24), and the results were compared with CMP process performance. The device surface has various sizes of structures with ~2-µm deep topography. Some rectangular well

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structures were as large as 500 µm x 350 µm. After CON-TACT® planarization, the topography was reduced from 2 µm to about 0.04 µm. The planarized photoresist was then etched to the substrate surface and the wells and trenches remained filled with photoresist. Subsequently, membranes were deposited and defined on top of the structures. The remaining photoresist was stripped to create membrane bridges across the well/trench structures. No obvious sagging of the membranes fabricated with CON-TACT® planarization process was observed. Additionally, no scratches were found on the surface. In comparison, as much as 1.5 µm of sagging was found on the membrane fabricated with CMP. It was believed that dishing during CMP caused the membrane to sag. In addition to sagging, CMP produced polishing scratches on the surface. It is evident that CON-TACT® planarization process delivered a significantly better planarization performance than CMP for such an application. SOG planarization for STI Application

Spin-on glass (SOG) has been used as planarization material as well as an interlayer

dielectric (ILD). However, the characteristics of SOG limit the thickness that can be deposited onto the substrate surface, thus limiting its planarization capability. ENSEMBLETM CP (The Dow Chemical Company), a spin-on silicon-containing dielectric coating specially formulated for the CON-TACT® planarization process, has been planarized using the CON-TACT® process for shallow trench isolation (STI) applications (22-23).

The planarization process was conducted on SKW 3-2 STI test wafers (purchased

from SKW Associates) and 64M STI DRAM wafers (purchased from Praesagus). These wafers have about 0.5-µm (5000 Å) topography with various sizes and feature density areas. A spin recipe that produces a ~0.5-µm thick ENSEMBLETM coating on a blank silicon wafer was used to coat these test wafers for planarization with predetermined conditions. Obtained from a Veeco Wyko NT3300 optical profiler, Figure 12 shows 500-µm lines with 500-µm spaces were planarized with the CON-TACT® process, with a remaining step height of about 500 Å. These results indicate that with appropriate conditions, the spin-on dielectric ENSEMBLETM CP dielectric was forced to flow a relatively long distance to fill the space between the lines. The contour maps and surface profiles were obtained from the reference and planarized 64M STI DRAM wafers using a Veeco Wyko NT3300 optical profiler. These results revealed that the step height, when measured from the same locations, was reduced from about 2500 Å for the reference wafer to about 290 Å for the planarized wafer. A topography reduction of about 94% was achieved, as compared to the original wafer topography. The much more planar surface provides a much better starting surface for the subsequent processing. If desired, the surface can be either etched or polished by CMP to transfer the surface planarity to the underlying layer (22-23). Spin-on Polymeric Dielectric Planarization for GaAs Applications

Precursors for organic polymers and polymers themselves, such as CycloteneTM,

polybenzoxazole, and polyimides, have been widely used as spin-on dielectrics for device fabrication, for instance, for ILDs in compound semiconductor devices and for




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packaging. Once coated, a final high-temperature curing process is normally needed. Some of the polymer precursors possess some planarization capability. However, their planarization capability is limited when their thicknesses are relatively similar to the height of the topography to be coated, especially for those structures having large feature sizes. To achieve the desired planarity, thicker coatings or multilayer coatings are needed. Alternatively, planarization processes can be used to provide the planarity needed. However, it is known that it is extremely challenging to planarize polymeric materials with CMP (30), for technical and sometimes for economical reasons. Therefore, an alternative planarization technology, CON-TACT® planarization process, has been applied to planarize such materials.

Figure 12. A surface profile from 500-µm lines with 500-µm spaces on a SKW 3-2 wafer planarized with ENSEMBLETM CP dielectric material. A step height of about 500 Å remains after planarization.

CycloteneTM Planarization. A 4-inch GaAs heterojunction bipolar transistor (HBT) device wafer with various and significant topographies was coated with CycloteneTM using a spin coating process to obtain about 1.7-µm thick coating on a blank 4-inch silicon wafer. The GaAs HBT device wafer had topography ranging from 1.0 µm to 2.4 µm and structure sizes ranging from a few micrometers to over 100 µm.

The coated wafer was planarized with predetermined parameters based on the

characteristics of the coated material. Although the spin-coating process provided local planarity as well as that of the planarized wafer, as seen in the FIB/SEM cross-section images on the bond pad next to the die street (Figure 13), spin-coating was not able to achieve a good global planarity. The step height measurements across the die from the original, reference, and planarized wafers are shown in Figure 14. The reference wafer

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has topography of 0.65 µm (6,500 Å) with a curved surface on top of the bond pads. While local planarity (within a few tens of microns) is obtained on this reference wafer, global planarity (across the die) is not obtained. In contrast, the planarized wafer has topography of only 0.07 µm (700 Å) with a flat surface on top of the bond pads. Both local and global planarity were achieved simultaneously. This small residual step height could be caused by the thermal shrinkage and residual solvent evaporation after being planarized at an evaluated temperature. Compared to the original wafer, a step height reduction of about 97% was achieved with the planarization process. The curved top surface on top of the large structures after reflow indicated that the material does have good flow property. However, the structures were too large for the ~1.7-µm thick CycloteneTM coating to planarize. Such a curved top surface could not only negatively impact the subsequent processing performance, but it also could cause undesirable electrical characteristics if metal is to be deposited on top, such as when building the interconnects or devices such as capacitors and inductors.

(A) (B) Figure 13. FIB cross-section photos of the (A) reference and (B) planarized wafer on the bond pad next to the die street. Good local planarity is observed in both cases.

Figure 14. Step height surface scans of the original GaAs HBT device die and the device die of the reference wafer and the planarized wafer that were coated with 1.7-µm CycloteneTM.

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Another major finding is the overburden thickness variation on top of the large structures. The average overburden thickness was about 0.7 µm and 1.0 µm for the planarized and reference wafers, respectively. The overburden thickness variation measured on the reference wafer was much larger than that measured on the planarized wafer. The within-die overburden variation measured on the top of the bond pads from the reference wafer was about 1,800 Å with a standard deviation of about 360 Å. For the planarized wafer, they are 400 Å and 120 Å, respectively. In some cases, less than 200 Å of overburden variation with a standard deviation of less than 50 Å was achieved within the die on the planarized wafer. These results show that an evident reduction of overburden variation has been achieved with CON-TACT® planarization technology on GaAs HBT wafers. The step height surface scans, Figure 14, have clearly supported this finding.

On the same device wafer, test die with an open area of about 1150-µm wide was

characterized, as shown in Figure 15. It showed that CON-TACT® process planarized this open area to about 0.15-µm (1,500 Å) topography as oppose to more than 1.0-µm (10,000 Å) topography obtained from the reference wafer. This finding indicated that the material was forced to flow to fill such a large, open recessed area.

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Figure 15. Step height surface scans of an open test die area on the original GaAs HBT device wafer, the thermally reflowed 1.7-µm CycloteneTM (reference) wafer, and the planarized wafer.

The wafer planarized using the CON-TACT® process provides a 97% step height

reduction (or 97% of DOP, compare to the original device step height), a globally and locally planar surface, and a much tighter overburden thickness variation as opposed to the spin-coated and thermally reflowed (reference) wafer. Such improvement will simplify the subsequent processing and ensure a better final yield.

Polybenzoxazole Planarization. A photosensitive polybenzoxazole was coated onto the 4-inch GaAs HBT device wafer to a thickness of about 8 µm. Even with such a thick coating on top of the 2.4-µm topographic surface, a step height of about 1.0 µm, after thermal reflow, remained on the wafer surface (Figure 16). It is clear that, with thermal




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reflow process only, this photosensitive polybenzoxazole material cannot provide a planarization capability as good as that for CycloteneTM. However, when planarized with the CON-TACT® process, the step height decreased to about 0.05 µm (500 Å) (Figure 16). A DOP of about 98% was achieved, and true local and global planarization was accomplished. However, it was observed that the spin-coated film cracked over a period of time, as did the planarized one. It was further observed that an additional 125°C bake for 120 seconds remedied the cracking problem. However, the additional baking process increased the step height on the planarized wafer to about 0.24 µm. The increase of step height was expected due to residual solvent evaporation. Furthermore, it was necessary to have some residual solvent to facilitate material flow during planarization, to avoid having to use extreme planarization parameters, due to the characteristics of the polybenzoxazole material. The baking process removed the residual solvent, which resulted in the increase in step height. The step height surface scan also indicated that the overburden variation for the planarized wafer is much less than that of the thermally reflowed (reference) wafer.

Figure 16. Surface step height scans of the original GaAs HBT device die, the thermal reflowed (reference, after 125ºC bake) polybenzoxazole coated wafer, the planarized wafer, and the wafer baked at 125ºC after planarization.

Polyimide Planarization. Brewer Science T-PolyimTM T20020 transparent polyimide

was applied with a spin coating process to achieve a film having a thickness of ~3.5-µm onto a 4-inch blank silicon wafer and onto a 4-inch GaAs HBT device wafer and planarized using CON-TACT® planarization technology with predetermined parameters. As shown in Figure 17, the topography (step height) was reduced from about 1.35µm (13,500 Å) on the reference wafer to about 0.35 µm (3,500 Å) on the planarized wafer, after undergoing a required 100ºC post-planarization bake for 120 seconds to remove the residual solvent. These results show a greater than 80% reduction of topography with CON-TACT® planarization technology as compared to that of the original device wafer. Similar to what was found in the CycloteneTM results, the reference wafer has curved surfaces on top of the bond pad structures while the planarized wafer has flat surface. The WID overburden also was measured. The WID overburden variation is shown in Figure 18. It is evident that 90% reduction of overburden variation was achieved with

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this planarization technology. Consequently, the subsequent processes can significantly benefit from the planar surface and the much smaller overburden variation.

It is understood that, once planarized, an additional curing process might be required for some of the planarization materials and the additional curing is likely to increase the step height due to shrinkage. However, with a well-reduced starting step height and much smaller overburden variation, it is expected that the cured planarized wafer will have much smaller step height and overburden variation than those of the cured thermal reflowed wafer.

Figure 17. Cross-die step heights measured from the original device wafer, the reflowed reference wafer coated with ~3.5-µm thick of T20020, and the planarized wafer coated with ~3.5-µm thick of T20020, both after a 100ºC bake.

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Figure 18. WID overburden variations measured from the reference and planarized wafers with about 3.5-µm overburden thickness.

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Conclusion

A wide variety of spin-on dielectric materials have been successfully planarized using CON-TACT® planarization technology. A high DOP, up to greater than 98%, with very little or no feature density dependency has been accomplished with various materials. These results are difficult to achieve using other planarization technologies. Both local and global planarization can be achieved simultaneously. As much as greater than 90% overburden variation has been reduced using this planarization technology. Such improvements can have broad and positive impacts on a number of technologies and processes, such as lithography, ILDs, STI, etc., that are critical for a wide range of device fabrication.

Acknowledgments

This research was partially funded by the U.S. Government under Advanced Technology Program #70NANB1H3019 awarded by the National Institute of Standards and Technology (NIST) and by the U.S. Department of Defense Missile Defense Agency under contract number Contract No. DASG60-03-C-0013. The authors would like to thank all the CON-TACT® technology development team members of Brewer Science, Inc., for their assistance. Ms. Mariya Nagatkina’s and Mr. John Thompson’s assistance in performing photolithography tests and SEM characterizations are greatly appreciated. The assistance of Ms. Lynne Mills of The Dow Chemical Company, who provided the ENSEMBLETM CP material, is appreciated. David Tuunanen and Bud Johnson of Skyworks Solutions Inc. provided FIB/SEM characterization services, and their help is acknowledged as well.

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CON-TACT® Planarization Process of Spin-on Dielectrics for Device Fabrication Wu-Sheng Shiha

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