Solution Deposition Planarization of Long-Length Flexible ...Solution Deposition Planarization of...

AIMCAL Fall Technical Conference, October 17-20, 2010

Solution Deposition Planarization of

Long-Length Flexible Substrates

Chris Sheehan and Vladimir Matias

Superconductivity Technology Center, MS T004

Materials Physics and Applications Division

Los Alamos National Laboratory

Los Alamos, New Mexico 87545


Presentation Outline

Motivation

SDP

Our Application

Performance

Summary

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Applications and Planarization Methods

Electronic Applications: printed circuits, integrated circuits,

displays, LEDs and sensors

Advanced Energy Applications: photovoltaics, batteries and

high temperature superconducting coated conductors (HTSCC)

Smooth substrates are critical for

increasingly sophisticated devices

Planarization Methods:

Coating: polymer solutions, PML, SOG

Removal: Electropolishing, mechanical polishing and CMP

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Substrate electropolishing was a key enabler for long-

length development by providing smooth tapes P a g e 1

Q U E S A N T S P M R E P O R TN o v 3 0 , 2 0 0 5 (W e d n e s d a y ) 2 :5 1 P M

LANL Electropolishing

Process developed at LANL

Clean smooth tapes in 100’s meter lengths

Hastelloy C-276 substrate

RMS roughness ≤ 1.0 nm on 5 x 5 µm scale

Transferred to industry (km lengths)

5 µm

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Solution Deposition Planarization provides an alternative

technology for preparing smooth substrates

Metal tape is sheathed in a benign oxide coating

Metal alloy tape

Yttrium oxide SDP coating

Solution deposition

Planarization (SDP) uses one or

more coatings of an amorphous

oxide by Chemical Solution

Deposition (CSD) to planarize

the surface

For a meniscus-type solution

coating, such as dip-coating of

the substrate, surface tension of

the liquid forces a smooth

surface on the coating

Multiple coats of SDP can

reduce roughness down to any

desired value, as low as 0.5 nm

RMS

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SDP also reduces the environmental impact as

compared to electropolishing

Electropolishing (EP) uses

tens of gallons of acids per

km of polished tape

Nickel contaminated acid

electrolyte is waste after

polishing and needs to be

disposed of

In SDP almost all the starting

material is utilized

SDP uses 100x less material

than EP (even less waste

generated)

Smaller footprint than EP and

less energy use

6


TEM Cross sectional analysis shows

planarization of the unpolished metal tape

g = (200)

BF

WB

YBCO superconducting layer

SDP-YO

Transmission electron microscope (TEM) images

Unpolished metal tape

IBAD layer

SDP-YO

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TEM section shows that SDP overcoat is effective

in blocking out defects in substrate

Porosity

Particulate

Note sharp interfaces in the compositional profiles

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At LANL we use a reel-to-reel setup and

a loop coater for SDP

• SDP by dip coating

• Implemented a

continuous loop 5 meter

long tape pieces

• Loop coater allows

much shorter deposition

times

Feed Reel Pick-up reel

Encoder Heater

Bath

Encapsulation

Gas inlet

DIP COATING

SOLUTION BATH

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In 2010 LANL built a scaled-up system for SDP

Carefully designed deposition system

for better control of process parameters

and better repeatability

Longer and wider tape capability (100

meter lengths) and process automation

Higher throughput by doing several

SDP coatings in series

Relatively low-cost design

(parts & machining < $70K)

NEW SYSTEM

PREVIOUS SYSTEM

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New system has improved process capabilities

Double containment bath enclosure

Continuous solution flow with

continuous filtering (≤ 1 µm)

In-line tape cleaning with solvents

before deposition

3 SDP coating baths, 3 different

reservoirs and 6 heaters (for

bi-directional coating) with

temperature control

Coating of up to 10-cm wide webs

No tape contact before conversion

Automated process for complex

combination of coatingsDRAIN

SOLUTION

IN

TAPE

BATH

HEATERS

COATING

BATHS

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Planarization as a function of shrinkage and

coating thickness

RMS roughness as a function of number of coats

5 µm5 µm

Initial substrate

RMS roughness

No. of passes required

for final 1–2 nm RMS

3 – 4 nm 3 – 4

20 – 30 nm 10 – 15

UNPOLISHED

20 nm

PLANARIZED

1.1 nm

Formula for residual roughess following an

SDP coat:

R0 * (1- t1/t0)n = Rn

s=1-t1/t0, s is the shrinkage

For R0 = 30 nm and shrinkage of 85%

need about 15 layers to attain 2 nm roughness

12


By using multi-molarity SDP coatings we were able

to achieve less than 1 nm RMS roughness

Unpolished RMS (5x5 µm): 26 nm

After15-20 SDP coatings (5x5 µm): 0.5 nm

Rq = 0.56 nm

Ra = 0.45 nm

Rq = 25.6 nm

Ra = 20.5 nm

UNPOLISHED

SUBSTRATE

0.4 M coats

0.08 M coats

s =.89

13


HTSCC Applications

• Transmission lines

• Electric motors

• Generators

• Energy storage

• Magnets

• Fault current limiters

14


High-Temperature Superconducting (HTS) wires

conduct large amounts of electricity with 100%

efficiency when cooled with liquid nitrogen

The thin HTS tapes on the right of this image carry as much power as

all the copper shown on the left and with no loss.

15


High-Temperature Superconducting cables are

being installed in the nation’s electricity grid

There are several Department of Energy

sponsored Advanced Cable projects:

• Albany, NY, Cable, 34.5 kV 350 m

• Columbus, OH, Cable, 13.2 kV 200 m

• Long Island Cable, 138 kV 600 m

• New Orleans Cable, 13.8 kV 1.8 km

• Hydra Cable, Manhattan, NYC, 300 m

Albany Columbus

Long Island

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HTS Wire production is presently in transition from

1st generation to 2nd generation wire

• Two American companies are at the forefront of 2G HTS Wire production worldwide

• American Superconductor

• 1st Generation BSCCO/Ag Plant (>5000 km/yr)

• Switched to 2nd Generation Pilot Production in 2006

• Superpower

• Pilot Production of 2nd Generation HTS Wire

• Lengths of 100’s m produced (and over 1 km)

2G HTS wire, known as

Coated Conductor, presents an

opportunity of lower cost and

better performance in a

magnetic field compared with

1G wire.

Cost needs to be less than

$50/kA•m for broad acceptance

of superconducting power

technology.

Presently costs for 2G wire are

about $400/kA•m.

First Generation HTS Wire:

BSCCO 2223 filaments in Ag

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IBAD provides a single-crystal-like template for

supercoducting coatings in long lengths

Superconductor crystalline structure

must be highly aligned (less than

5° mosaic spreads) for the

superconductors to carry high

currents

The crystalline-aligned template is

achieved with an ion-beam assisted

deposition of an oxide coating

HOWEVER, for the best quality

template smoothest starting

surfaces are required (roughness

less than 2 nm)

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Solution Deposition Planarization eliminates

three steps in present CC manufacturing

Current Manufacturing Process

for HTS CC

Simplified SDP Process

for HTS CC

Polished, expensive

metal substrate

Superconductor

Barrier layer

Bed layer

IBAD

Unpolished, inexpensive

metal substrate

Superconductor

SDP

IBAD

SDP combines electropolishing, barrier and bed layer deposition

into one process step

Additionally it broadens the range of substrates that can be used

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Multi-molarity coatings result in improvements

for MgO grain alignment

• mechanically polished

0.08 M SDP

0.4 M SDP

Low molarity finishing coat helps

achieve low in-plane textureOut-of-plane texture follows a ‘universal’

dependence on roughness

0.4 M + 0.08 M SDP

• mechanically polished

0.08 M SDP

0.4 M SDP

0.4 M + 0.08 M SDP

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High critical current, Jc, achieved by Reactive Co-

Evaporation of YBa2Cu3O7 (YBCO) on IBAD/SDP

YBCO (superconducting layer) deposited by

LANL RCE on MgO template grown on

SDP Y-Al-O

Y-Al-O retains amorphous structure after

YBCO deposition

YBCO deposited on 30 nm MgO

MgO texture: Df = 4.6°, DW = 1.5°

1.0 µm YBCO film-50 0 50 100 150 200 250 300 350

Inte

nsity

Phi (degrees)

YBCO pole figure

Jc = 4.1 MA/cm2,

75 K, self field

YBCO

Unpolished

metal tape

SDP

Df = 2.4°, DW = 0.9°

IBAD+epi MgO

(Y,Al)2O3

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Superconducting critical currents on IBAD/SDP

templates compare well with the best YBCO films

YBCO critical currents depend

on the superconducting film

thickness

Figure on the right shows a

plot of the best undoped

YBCO samples grown by

pulsed laser deposition (PLD)

on single crystal substrates

The red dot shows a YBCO

film grown on IBAD template

on an SDP prepared substrate

PLD data from Foltyn et al., Nature Materials 6, 631 (2007)

YBCO on IBAD/SDP

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YBCO

YBCO

SDP allows for ‘Stacked’ Coated Conductor layer

structure with multiple SDP/IBAD/HTS layers

SDP allows for stacks on both sides of

the metal tape

SDP deposited on top of YBCO

Demonstrated roughness improvement

from > 100 nm (Ag on YBCO) to < 2 nm

by SDP

Second IBAD layer deposited on top of

second SDP; Df of MgO is 8°

Preliminary demonstration with a total

of 680 A (in 2 YBCO layers stacked)

Can potentially extend the Ic and Je

several fold

YBCO 2nd IBAD MgO

Ag

METAL TAPE

SDP/IBAD

YBCO

YBCO

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SDP process transferred from LANL to

SuperPower and STI

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Solution Deposition Planarization stands to

revolutionize superconducting wire

SDP enables lower cost substrates to be

used, such as stainless steels

SDP simplifies the layer architecture, by

combining 3 processing steps

SDP minimizes toxic wastes, by

eliminating use of acids used in

electropolishing

SDP enables creating a stack of HTS

layers for much higher power density in

superconducting wire

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Acknowledgements

Paul Clem, Jon Ihlefeld and Cynthia Edney from

Sandia National Laboratories

Yehyun Jung, Terry Holesinger, Matthew Feldmann,

E. John Rowley, and Paul Dowden of Los Alamos

National Laboratory

This work was supported by the Department of

Energy Office of Electricity Delivery and Energy

Reliability.

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