Computer Security Conference 15 APR 2010

FPGAs In The Classroom:Practice and Experience

William M. Jones, Ph.D.

Department of Computer ScienceCoastal Carolina University

What is an FPGA?

Where are FPGAs Found?

PrototypingHPCNICsGPUsDSP

And in CSCC Room 122!

Why?

Digital LogicArchitecture

CompilerDesign &

Implementation

AssemblyProgramming

CommonTarget

Computing Platform???

Altera DE2 Development and Education Board

Assembly Programming(CSCI 210 and 310)

Computer Architecture(CSCI 310)

Compilers(CSCI 450)

+Security

(CSCI 210 and 385)

FPGA Course Mappings

Digital LogicCombinational (CSCI 210)Sequential (CSCI 310)

OperatingSystemsCSCI 410

EmbeddedSystems

CSCI 4xx?

Digital Logic Design (Traditional)

Pencil and paper– Important pedagogical approach– Testing on quizzes and exams

Use of breadboards– Hands-on– Tedious– Prone to error

7400 series logic gates– Voltage polarity– Difficult to debug

Digital Logic Design (Innovative)

Pencil and paper– Still important

Schematic capture– Draw circuit diagram– Easily modifiable

Digital Logic (and more) IDE– Debugging capability

Testing in lab environment– Access to prototype boards

IDE and Tools

Trace Program Execution

CSCI 210 – Computer Organization

HW01 – Intro to logic gates, learn to use the IDE HW02 – Intro to logic gates, lights and switches HW03 – 1-bit Full Adder (from TT to implementation) HW04 – 4-bit 2’s complement ripple carry add/sub HW05 – Intro to NIOSII Processor, I/O, running sum HW06 – Binary encoding of instructions, addr. modes HW07 – Functions, loops, IF stmts., I/O with SSDs HW08 – Call stack management, param. passing HW09 – Buffer overflow, overwrite RA on call stack

Let’s Take a Look at Actual Student WorkCSCI 210 Fall 2009, Spring 2010

CSCI 210 – HW02 – Intro to Gates

Courtesy of Ruben Villao

CSCI 210 – HW04 – Full Add/Sub

Courtesy of Ruben Villao

A

B

C

A + (-) B = C

CSCI 210 – HW07 – NIOSII w/ SSDs

I/O w/ SSDs and switches

Courtesy of Dorian Sovic

NIOSII Embedded Processor32-bit RISC

CSCI 210 – HW07 – Assembly Code

Dorian Sovic

CSCI 210 – HW09 – Stack Exploitation

Foo’s saved RA

A[0]

A[7]

A[1]. . .Provide student w/

uncommented code.

They identify problem and exploit it.

CSCI 310 – Computer Architecture

HW01 – Multiplexer design (from TT to Kmap to impl) HW02 – 1-bit Full Adder (from TT to implementation) HW03 – 4-bit ripple carry adder HW04 – State machine design, 3-bit up/down counter HW05 – State machine design, serial data stream HW06 – MM:SS digital clock, (from TT to impl) HW07 – Intro to NIOSII Processor, I/O, running sum HW08 – Function calls, I/O HW09 – Functions, I/O, bit shifting/masking, stack Implemented Fall 2009

CSCI 210 – HW05 – State Machines

Courtesy of James Bettke

CSCI 210 – HW05 – State Machines

CLK

D

PRN

CLRN

Q

QN

DFF2

inst

CLK

D

PRN

CLRN

Q

QN

DFF2

inst1

VCCKEY[0] INPUT BCD TO 7SEG

LTN

B

C

D

RBIN

BIN

A

OB

OC

OE

OD

OF

OG

OA

RBON

7447

inst9

HEX0[0]OUTPUT

HEX0[1]OUTPUT

HEX0[2]OUTPUT

HEX0[3]OUTPUT

HEX0[4]OUTPUT

HEX0[5]OUTPUT

HEX0[6]OUTPUT

AND2

inst10

AND2

inst11AND2

inst12

OR2

inst14

AND2

inst13AND2

inst15

OR2

inst16

VCC

VCCSW[0]INPUT

PIN_N25

PIN_AF10

PIN_AB12

PIN_AC12

PIN_AD11

PIN_AE11

PIN_V14

PIN_V13

PIN_G26

LEDG[0]OUTPUT

1-Hot EncodingA = A+ = X’A + X’B + X’C + X’DB = B+ = XAC = C+ = XBY = D = D+ = XC + XD

Courtesy of James Bettke

CSCI 310 – HW06 -- MM:SS Digital Clock

4-bit counter (state transition diagram)Glue logic, frequency dividers

Courtesy of Yosi Benzera

CSCI 310 – HW09 – Shifting/Masking

Get some dataDrive SSDs w/ software

Stack managementShifting MaskingLook up tables

Courtesy of Yosi Benzera

Looking Towards Next Year

Refine course objectives to delineate 210/310– Hardware Description Language (VHDL)– ALU– Simple CPU

Improve / create new security modules for placement in CSCI 385

Create interrupt (C-based) lab for CSCI 410– Push button

Create assembler lab for CSCI 450

A Simple ALU (Digital Logic/Comp. Arch.)

ALU Specifications

ALU Part 1

ALU Part 2

ALU Part 3

So What Do You Need? An FPGA Development Board/Kit

– Xilinx– Altera– $150 - $500 ($275 each)

IDE– ISE– Quartus– University programs / freely available

Host Computer– PC– Laptop– USB

Digital Signal Processing, Video, Networking, Embedded Systems

Thank you!

Questions?

http://ww2.coastal.edu/wjones

After talk comments on the next slide …

After-talk thoughts ….

Attendees were asked if this focus on assembly and hardware is relevant to computer security.

Responses were varied– Some thought it was paramount– Some thought it was not particularly relevant– Others suggested it depended on what type of job

you ultimately got