1 MSc - Microprocessors Dr. Konstantinos Tatas [email protected].
ACOE201 – Computer Architecture I – Laboratory Exercises Background and Introduction to FPGAs...
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Transcript of ACOE201 – Computer Architecture I – Laboratory Exercises Background and Introduction to FPGAs...
![Page 1: ACOE201 – Computer Architecture I – Laboratory Exercises Background and Introduction to FPGAs Dr. Konstantinos Tatas com.tk@fit.ac.cy .](https://reader035.fdocuments.in/reader035/viewer/2022062516/56649dc05503460f94ab4247/html5/thumbnails/1.jpg)
ACOE201 – Computer Architecture I – Laboratory Exercises Background and
Introduction to FPGAsDr. Konstantinos Tatas
[email protected]://staff.fit.ac.cy/com.tk
![Page 2: ACOE201 – Computer Architecture I – Laboratory Exercises Background and Introduction to FPGAs Dr. Konstantinos Tatas com.tk@fit.ac.cy .](https://reader035.fdocuments.in/reader035/viewer/2022062516/56649dc05503460f94ab4247/html5/thumbnails/2.jpg)
ACOE201 Laboratory Structure and Objectives
• Small group experiments lasting approximately two periods
• Lab report • Design and implementation of a simple CPU• Hardware: Xilinx Spartan-3E Starter Kit• Software: Xilinx ISE• Objectives:
– Develop practical digital design skills– Reinforce Computer Architecture concepts by
designing and verifying a simple CPU
![Page 3: ACOE201 – Computer Architecture I – Laboratory Exercises Background and Introduction to FPGAs Dr. Konstantinos Tatas com.tk@fit.ac.cy .](https://reader035.fdocuments.in/reader035/viewer/2022062516/56649dc05503460f94ab4247/html5/thumbnails/3.jpg)
Xilinx Spartan-3E Starter Kit
FPGA
switchesbuttons LEDs
![Page 4: ACOE201 – Computer Architecture I – Laboratory Exercises Background and Introduction to FPGAs Dr. Konstantinos Tatas com.tk@fit.ac.cy .](https://reader035.fdocuments.in/reader035/viewer/2022062516/56649dc05503460f94ab4247/html5/thumbnails/4.jpg)
FPGA Principles
• A Field-Programmable Gate Array (FPGA) is an integrated circuit that can be configured by the user to emulate any digital circuit as long as there are enough resources
• An FPGA can be seen as an array of Configurable Logic Blocks (CLBs) connected through programmable interconnect (Switch Boxes)
![Page 5: ACOE201 – Computer Architecture I – Laboratory Exercises Background and Introduction to FPGAs Dr. Konstantinos Tatas com.tk@fit.ac.cy .](https://reader035.fdocuments.in/reader035/viewer/2022062516/56649dc05503460f94ab4247/html5/thumbnails/5.jpg)
FPGA structure
CLB SB
SB SB
CLB
SB
CLB SB CLBConfigurable Logic Blocks
Interconnection Network
I/O Signals (Pins)
![Page 6: ACOE201 – Computer Architecture I – Laboratory Exercises Background and Introduction to FPGAs Dr. Konstantinos Tatas com.tk@fit.ac.cy .](https://reader035.fdocuments.in/reader035/viewer/2022062516/56649dc05503460f94ab4247/html5/thumbnails/6.jpg)
Simplified CLB Structure
CLB SB
SB SB
CLB
SB
CLB SB CLBConfigurable Logic Blocks
Interconnection Network
I/O Signals (Pins)
Look-Up Table (LUT)
Q
QSET
CLR
D
MUX
![Page 7: ACOE201 – Computer Architecture I – Laboratory Exercises Background and Introduction to FPGAs Dr. Konstantinos Tatas com.tk@fit.ac.cy .](https://reader035.fdocuments.in/reader035/viewer/2022062516/56649dc05503460f94ab4247/html5/thumbnails/7.jpg)
Example: 4-input AND gateA
B
C
D
O
A B C D O
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 0
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 1
Q
QSET
CLR
D
MUXA
B
C
D
0000000000000001
Configuration bits
O
0
![Page 8: ACOE201 – Computer Architecture I – Laboratory Exercises Background and Introduction to FPGAs Dr. Konstantinos Tatas com.tk@fit.ac.cy .](https://reader035.fdocuments.in/reader035/viewer/2022062516/56649dc05503460f94ab4247/html5/thumbnails/8.jpg)
Example 2: Find the configuration bits for the following circuit
Q
QSET
CLR
D2-to-1 MUX
A0
A1
S
Clock
Q
QSET
CLR
D
MUXA0
A1
S
Configuration bits
A0 A1 S
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
![Page 9: ACOE201 – Computer Architecture I – Laboratory Exercises Background and Introduction to FPGAs Dr. Konstantinos Tatas com.tk@fit.ac.cy .](https://reader035.fdocuments.in/reader035/viewer/2022062516/56649dc05503460f94ab4247/html5/thumbnails/9.jpg)
Interconnection Network
CLB SB
SB SB
CLB
SB
CLB SB CLBConfigurable Logic Blocks
Interconnection Network
I/O Signals (Pins)
Configuration bits 1
0
0
00
0
![Page 10: ACOE201 – Computer Architecture I – Laboratory Exercises Background and Introduction to FPGAs Dr. Konstantinos Tatas com.tk@fit.ac.cy .](https://reader035.fdocuments.in/reader035/viewer/2022062516/56649dc05503460f94ab4247/html5/thumbnails/10.jpg)
Example 3• Determine the configuration bits for the following circuit
implementation in a 2x2 FPGA, with I/O constraints as shown in the following figure. Assume 2-input LUTs in each CLB.
CLB0 SB0
SB1 SB2
CLB1
SB3
CLB2 SB4 CLB3
Input1
Input2
OutputInput3
Q
QSET
CLR
DInput1Input2
Input3
Output
![Page 11: ACOE201 – Computer Architecture I – Laboratory Exercises Background and Introduction to FPGAs Dr. Konstantinos Tatas com.tk@fit.ac.cy .](https://reader035.fdocuments.in/reader035/viewer/2022062516/56649dc05503460f94ab4247/html5/thumbnails/11.jpg)
CLBs required
Q
QSET
CLR
DInput1Input2
Input3
Output
CLB 1 CLB 2
Q
QSET
CLR
D
MUX
Input1
Input2
0
0
0
1
Configuration bits
O
1 Q
QSET
CLR
D
MUX
O
Input3
0
1
1
0
Configuration bits
Output
0
![Page 12: ACOE201 – Computer Architecture I – Laboratory Exercises Background and Introduction to FPGAs Dr. Konstantinos Tatas com.tk@fit.ac.cy .](https://reader035.fdocuments.in/reader035/viewer/2022062516/56649dc05503460f94ab4247/html5/thumbnails/12.jpg)
Placement: Select CLBs
CLB0 SB0
SB1 SB2
CLB1
SB3
CLB2 SB4 CLB3
Input1
Input2
OutputInput3
![Page 13: ACOE201 – Computer Architecture I – Laboratory Exercises Background and Introduction to FPGAs Dr. Konstantinos Tatas com.tk@fit.ac.cy .](https://reader035.fdocuments.in/reader035/viewer/2022062516/56649dc05503460f94ab4247/html5/thumbnails/13.jpg)
Routing: Select path
CLB0 SB0
SB1 SB2
CLB1
SB3
CLB2 SB4 CLB3
Input1
Input2
OutputInput3
Configuration bits
SB1
1
0
0
00
0
Configuration bits
SB4
0
0
0
01
0
![Page 14: ACOE201 – Computer Architecture I – Laboratory Exercises Background and Introduction to FPGAs Dr. Konstantinos Tatas com.tk@fit.ac.cy .](https://reader035.fdocuments.in/reader035/viewer/2022062516/56649dc05503460f94ab4247/html5/thumbnails/14.jpg)
Configuration Bitstream
• The configuration bitstream must include ALL CLBs and SBs, even unused ones
• CLB0: 00011• CLB1: 01100• CLB2: XXXXX• CLB3: ?????• SB0: 000000• SB1: 000010• SB2: 000000• SB3: 000000• SB4: 000001
![Page 15: ACOE201 – Computer Architecture I – Laboratory Exercises Background and Introduction to FPGAs Dr. Konstantinos Tatas com.tk@fit.ac.cy .](https://reader035.fdocuments.in/reader035/viewer/2022062516/56649dc05503460f94ab4247/html5/thumbnails/15.jpg)
Realistic FPGA CLB: Xilinx
![Page 16: ACOE201 – Computer Architecture I – Laboratory Exercises Background and Introduction to FPGAs Dr. Konstantinos Tatas com.tk@fit.ac.cy .](https://reader035.fdocuments.in/reader035/viewer/2022062516/56649dc05503460f94ab4247/html5/thumbnails/16.jpg)
FPGA EDA Tools
• Must provide a design environment based on digital design concepts and components (gates, flip-flops, MUXs, etc.)
• Must hide the complexities of placement, routing and bitstream generation from the user. Manual placement, routing and bitstream generation is infeasible for practical FPGA array sizes and circuit complexities.