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CPU 8085/88USER MANUAL

IEEE 696 / 8-100

DUAL CPU16 BIT 8088 - 8 BIT 8085

CLOCK RATE8 TO 8 MHz

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( cimDUPro™ 01""0' ®®@)ffi(j)OO~_ Iii ELECTRONICS -11 J81

Table of Contents

How To Get Your CPU 8085/88 to Run inUnder 5 Minutes Without Reading the ManualAbout the CPU 8085/88Technical overview.Switch settings and option selection8085 only operationExtended address optionsI/O wait state selectionProcessor initialization after swap optionsJump-on-resetKWRITE EnablePower-on-jump enablePower-on-jump addressMemory manager/swap port addreas2 MHz or 5 MHz operationUsing the memory managerSwapping processorsUser notes . . . . .Logic diagramCircuit descriptionProcessor and bus interface circuitryProcessor swap circuitryMemory manager circuitryPower-on-jump circuitryParts list .Component layout8085 timing8088 timingCustomer service/limited warranty information.

J44555556666677

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1214IS1616171.1.20

----------------------- DISCLAIMER ------------------------Godbout Electronics makes no representations or warrantieswith respect to the contents hereof and specificallydisclaims any implied warranties of merchantability orfitness for any particular purpose. Further, GodboutElectronics reserves the right to revise this publicationand to make any changes from time to time in the contenthereof without obligation of Godbout Electronics to notifyany person of such revision or changes.

-----------------------------------------------------------This manual was proofread with tne aid of SpellGuard™which was provided by ISA, Menlo Park, CA 94025.

2 CPU 8085/88' COMPUPRO PRODUCT· GODBOUT El.ECTRONICS • BOX 2355 OAKLAND AIRPORT. CA 94014

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Dip switch 2 is located between U25 andU26 and is used to set the power-an-jumpaddress. If you don't need power-an-jump. youshould have set Dip Switch I. position 8 toOFF. and you can skip this section.

1 ADDR 8 O. to match addr.bit 8.

2 ADDR 9 O. to match addr.bit 9.

3 ADOR 10 O. to match addr.bit 10.

4 ADDR 11 OK to match addr.bit 11.

S ADOR 12 O. to match addr.bit 12.

6 ADDR D O. to match addr.bit 13.

7 ADDR 14 O. to match addr.bit 14.

8 ADDR 15 O. to match addr.bit 15.

Dip switch 3 is used to set the I/O portthat is used by the Memory Manager and swappingprocessors. The Compupro 'standard' is portaddress PO hex. and here's how to set it:

DIP Switch 3

SWITCH POSITION LABELED HOW TO SET IT

HOW TO GET YOUR CPU 8085/88TO RUN IN UNDER 5 MINUTES

WITHOUT READING THE MANUAL

This s@ction 18 for those of you who are80 anxious to see if your new CPU board worksthat you can't wait long enough to read the.anual. This section will tell you how to setthe switches up 80 that the CPU 8085/88 willlook .oat like Jour older CPU board.

R SDOIICLY UCOllllDD nut TOO .BUY ~

"lAD tIl M.A._VALli If. after reading andfulliving the directioDa in this sectioD. yoursy.telll doesoOt work, DON'T CALLIl! READ THEMANUAL FIRSTlll

8085 ONLY

If your CPU 8085/88 was factory assembled.or you are u8iog a version that contains bothCPUs. don't read this section. Skip to thenext section. This section 18 for those of youwho purchased aD 8085 only version, UNKIT.

You will need to 108ta11 two jumpers, J3aod J4. (If you followed the assemblyinstructions carefully, you should have alreadyinstslled them.) J3 is located above and tothe right of U17 and J4 is located above and tothe right of U23.

USe a piece of component lead for thejumpers and leave about a 1/4 inch loop abovethe board ao that they may be easily cut whenyou want to add an 8088.

SWITCH POSITION

DIP Switch 2

LABELED HOW TO SET IT

SWITCH SETTINGS

Dip switch 1 is located between U6 and U7.It is used to select various operational modesof the CPO 808S/88.

DIP Switch 1

-----------------------------------------------1 ADDR 0 OFF2 ADDR 1 ON3 ADDR 2 OFF4 ADDR 3 OFFS ADDR 4 OFF6 ADDR 5 OFF7 ADDR 6 OFF8 ADDR 7 OFF

1 lA3 OM2 lAC 1M3 lOW O.4 5RS ons 8RS on6 JOR O.7 NW OFF 1£ you have

a front panel.O. otherwise.• 8 POJ DB 1£ you need

power-an-jump.OFF otherwise.

SWITCH POSITION LABELED BOW TO SET ITSwitch 4 is located in the upper right

hand corner of the board and is the largeswitch with the red paddle. It 1s used toselect either 2 or 5 Mhz operation for the8085.

TURN THIS SWITCH SO THAT THE PADDLE IS INTHE LEPT-KOST POSITION. This will select 2 Khzoperation. which is a good place to start.

If you have a IKSAI-type front panel. plugthe cable into J2. J2 is a 16 pin socketlocated in the upper risht hand corner of theboard. You 101111 also want to turn position 7of Dip Switch 1 (KW). OFF. You 101111 also wantto install a jumper at location J6.

5/81 3

ABOUT CPU 8085/88

Congratulations on your purchase of theCPU 8085/88 - an advanced processor boarddesigned specifically for full electrical andmechanical compatibility with the IEEE 5-100bus standard. The 5-100 bus Is theprofessional level choice for commercial,industrial and scientific: applications. Thisbus provides for ready expansion andmodification 8S the state of the art improves.We believe that this board, with the rest ofthe CoapuPro family, Is one of the best boardsavailable for that bus.

Features such as 6 Mhz operation. 24 bitsof extended addressing, power-on jump, and theability to have 16 bit power in an 5-100 systemat a reasonable price. make the CPU 8085/88another proud member of the CoapaPro family.

Thank you for chooaing a CoapuProproduct •••• welcome to the world of 16 bitpower!

TECHNICAL OVERVIEW

The CPU 8085/88 Dual Processor board wasspecifically designed to make it easy for the5-100 Bus user to get into the world of 16 bitmicros, while at the same time preservingcompatibility with existing hardware andsoftware.

We accomplished this goal by choosing theIntel 8088 16 bit CPU, (an 8 bit bus version ofthe 8086), and the 8085A 8 bit CPU. The 8085provides both hardware and softwarecompatibility with the current crop of 5-100peripherals, and the 8088 provides for greatlyenhanced software capability while maintainingan 8 bit external bus for hardwarecompatibility.

The user may switch back and forth betweenthe two processors with a simple softwarecommand. For example, this allows the user tolet the 8085 run his currently available (andfamiliar) disk operating system while lettingthe 8088 run the more advanced applicationssoftware. One processor would then "call" theother to handle the task most suited to it.

This environment is also extremelyeffective when trying to develop new softwarefor the 8088. One may use tools available thatrun under the 8085 (such as CP/M andMicrosoft's 8086/88 Macro Cross-Assembler thatruns under CP/M) to write the new code and thensimply switch over to the 8088 to try it out.PROK's need not be burned and erased andsystems pulled apart to transfer the code tothe 8088 system.

Both processors currently run at 5 Mhzwhich maximizes bus throughput. A switch isprovided to slow the 8085 down to 2 Mhz forsoftware dependent timing loops that want torun at that speed and are not easily changed.Intel says that an 8 Khz 8088 and faster 8085'sare on the way, and this board was designedwith the faster chips in mind. By merelychanging a crystal you may upgrade the board touse a faster processor when they become

available. Current state of the art in UART's(used in serial I/O boards) is barely able tocope with this 5 Khz bus rate, so a s .. itch isprovided on the CPU 8085/88 to add one waitstate to every I/O cycle.

Power-on-jump circuitry is prOVided thatallo.. s the CPU to begin its execution at any256 byte boundary (within the lower 64K). Aswitch is prOVided to disable this feature. Aswitch is also provided to allow the power-on­jump circuitry to be active at power-on only,or to work at power-on and every time a RESEToccurs (jump-on-reset).

The 8085 can directly address 64K bytes of ~memory, but our built-in Memory Kanager schemeallows access to the full 16 megabytesavailable per the IEEE 5-100 standard. The8088 can directly address 1 megabyte, but ourMemory Manager is smart enough to kno ....hichprocessor is in control. Thus the 8088 usesonly the upper four bits of the Memory Managerso it too can access the 16 megabyte addressspace. This will be described in greaterdetail later.

The CPU 8085/88 rigidly adheres to theIEEE 5-100 standard to insure compatibilitywith future 5-100 components, but should alsowork quite well with most .. ell designed pre­IEEE hardware. For example, provision is madeto use the IH5AI front panel even though itdoesn't exactly fit into the new standard.

Many long hours of thought and revisionwent into this product and we at Compupro areconfident that it will provide years of solidservice. We sincerely hope that you will enjoyit.

•4 CPU 80SS188. COMPUPRO PRODUCT. GODBOUT elECTRONICS. BOX 2355 OAKLAND AIRPORT. CA 94614

SWITCH SETTINGS & OPTION SELECTION

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8085 ONLY OPERAnON

If you purchased the 8085-only version ofthis board you will need to install twojumpers. If you have the assembled and testedor esc versions. these jumpers are installedfor you already.

One Is labeled J3 and is located above andslightly to the right of U17. The other 1slabeled J4 and is located above and slightly tothe right of U23.

Use a small piece of wire. such as thatleft over from a component lead. Be sure andleave enough of a loop (about 1/4 inch) 80 thatit may be easily cut when upgrading to the8088. Solder the jumpers on the solder side ofthe board and trim off the excess leads.

If you are providing your own 8088 and8284, do not install J3 and J4!

Switch 1

Switch 51 Is located between U6 and U7 andis used to select the various options andoperational modes of the CPU 8085/88.

EXTENDED ADDRESS OPTION

The first two positions of 51 are used tocontrol how the upper 8 address bits (AI6-23)respond to certain system operations.

Switch position 1 is labeled XA3 and isused to control whether or not A16-23 will betri-stated when ADSBL* is asserted on the S-100Bus. ADSBL* is used to tri-state the systemaddress bus, usually during a DMA.

Newer DMA devices that meet the IEEE 5-100specs are required to provide the full 24 bitaddress to the bus during a DMA, but most ofthe older devices do not.

H you have a device that provides all 24address bits then turn switch position 1 ON.Otherwise turn switch position 1 OFF.

Switch position 2 is labeled XAC and isused to control whether or not the extendedaddress bits (A16-23) are cleared when RESET*is asserted on the S-100 Bus.

The extended address register will alwaysbe cleared on a power-up. but after yourprogram sets its value you may not want it tobe cleared (set to 0) each time a RESET occurs.

If you desire the bits to be cleared onR.ESET* then turn switch position 2 ON. If youwant to leave the register unchanged after aRESET* then turn switch position 2 OFF.

I/O WAIT STATE SELECTION

Switch position S3 is labeled lOW and isused to control whether or not a wait statewill be inserted into every I/D cycle.

This is particularly useful when runningat 5 Mhz and beyond. Older design I/a boardsmay have trouble running at 5 Mhz, especiallythose with VARTs. To deal with this problemthe CPO 8085/88 allows automatic insertion ofone wait state to each I/O cycle.

To allow wait state generation turn sWitchposition 3 ON. To inhibit automatic wait stategeneration turn switch position 3 OFF.

PROCESSOR INITIALIZATIONAFTER SWAP OPTIONS

The CPO 8085/88 contains circuitry thathandles orderly change-overs between the 8085and the 8088. Part of this circuitrydetermines what state the respective processorwill be in when it comes "on line".

One mode of operation will cause a RESETto be issued to the processor as it comes online. This will cause the 8085 to go through apower-on-jump sequence (if enabled) or to beginexecution at address 0000 hex. The 8088 willbegin execution at FFFFO hex.

OtherWise, when each processor comes online it will begin its execution at the placewhere it went off line. In other words. itjust picks up where it left off.

If you desire the 8085 to always be resetwhen it comes on line then turn switch position4 ON (labeled 5as for 8085-Reset-on-Swap). Ifyou want the 8085 to resume operations in placewhen coming on line. then turn switch position4 OFF.

If you desire the 8088 to always be resetwhen it comes on line then turn switch position5 ON (labeled 8as for 8088-Reset-Qn-Swap). Ifyou want the 8088 to resume operations in p13cewhen coming on line. then turn SWitch position5 OFF.

NOTE: When both processors come on linethe first time they w111 go through theirnormal power-up sequence regardless of thesettings of these two switches.

IMPORTANT ROTE: When using the CPU 8085/88 withDMA devices, the 5RS and 8RS switches MUST bein the OFF position.

5/81 5

Switch 2

DIP SWITCH 3

Memory Manager!Processor Swap Port Adcress

ON "1"OFF "0"

A.A9

Al0AllA12A13A14A15

1234,,7

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SWitch Podtion

For example, if you want to jump to EOOOyou would turn switch positions 1 through 5 OFFand switch positions 6 through 8 ON.

Dip switch 2 is located between U25 andU26 and it is used to set the address that theCPU 8085/88 will jump to on power-on 1£enabled.

The CPO 8085/88 can jump to any 256 bytepage boundary in the lower 64K of addressspace. Switch 2 is set to correspond to thebit pattern of AS-IS of the page you -want tojump to. When a switch is ON it represents a"one" and conversely when a swi tch is OFF itrepresents a "zero".

DIP SWITCH 2

pOWER-aN-JUMP ADDRESS

Dip switch) is located between U)) andU)4 and is used to set the address of the I/Oport that is used to control the memory manager(output) and to swap processors back and forth(input).

One port address is used by the CPU8085/88 and it is determined by setting thepositions of dip switch 3 to correspond to thelower 8 address bits (AO-7) of the desired portaddress.

When a switch is turned ON it represents a"zero" and conversely when a switch is turnedOFF it represents a "one". Note that this isthe opposite of switch 2.

Switch position 6 1s labeled JOI. and 1sused to determine whether or not the 8085 willjump on reset or only on power on. If youdesire a jump sequence to occur for resets thenturn switch position 6 ON. If you want thejump to occur at power on only then turn switchposition 6 OFF.

The CPO 8085/88 contains a "power-on-jump"circuit that allows the 8085 to begin itsexecution at any 256 byte page boundary. Inthe strictest sense of the definition, a power­on-jump circuit should only be active at poweron. But sometimes it is convenient to performthe jump each time a RESET. occurs. We haveprOVided this option for you.

pOWER-aN-JUMP ENABLE

JUMP-aN-RESET

MWRITE ENABLE

Switch position 7 is labeled XV and 18used to determine if the CPU 8085/88 willgenerate the S-100 signal HWRITE.

The IEEE S-100 standard states that HWRITEshall be generated only in one place in a givensystem. Some systems, notably those with frontpanels (ie:IMSAI 8080). have circuitry thatgenerate MWRITE. This circuitry is not easilydisabled. Some systems do not have an MWRITEgenerator, so it is up to the CPU to provideMWRITE to the bus.

The important point here is that you only-want~ MWRITE generator in your system. Ifyour current system has an HWRITE generator init. you -will -want to turn switch position 7OFF. If your current system has no MWRITEgenerator in it (or if you are about to removeyour old CPU card that generated it) you willwant to turn switch position 7 ON.

To summarize. turning switch position 7 ONwill allo'-' the CPU 8085/88 to generate MWRITEand turning switch position 7 OFF -will inhibitgeneration of MWRITE by the CPU 8085/8&

Switch 3Switch position S is labeled POJ and is

used to enable or disable the power-on-jumpfeature of the CPU 8085/88.

If you desire to have the po-wer-on-jumpfeature active then turn switch position 8 ON.If you don't want the power-on-jump feature tobe active then turn switch position 8 OFF.

If the power-on-jump feature is notutilized then the 8085 -will begin its executionat 0000 hex, which is its normal mode ofoperation.

Switch Po_Hiott

1234,,7

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Addu.. ill

AOAlA2AJ ONM OFFASA6A7

- "0""1" •

6 CPU 8085/88· COMPUPRO PRODUCT· GODBOUT elECTRONICS. BOX 2355 OAKLAND AIRPORT, CA 946,.

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The Olatandard" port addresa ia 7D he:t.Any software that ia provided b, eoapupro willasauae that this switch is set for port PD. Toset the switch for port FD turn switcb position2 ON and all other switch positions OF!'.

2 OR 5 MHz OPERATION

Switch 4

Switch 4 is uaed to select whether the8085 will run at 2 Mhz or 5 Mhz. In ao.e olders,ateaa. witb slower .eaory. it ••y beneceasary to run at 2 Mhz. So.e oldergeneration hardware will not operate correctlyor reliably at 5 Mhz (such as the IMSAI frontpanel). Also so.e software bas tiaing loopsthat depend on a 2 Mhz processor. If poasiblethese loops should be .odified. but some areundocumented aaking thea hard to find andtherefore change. If this ia the case. youwill probably want to run at 2 Mhz.

Switch 4 is located at the upper rightband corner of tbe board and is the largepaddle switch with the red handle.

Putting the switch in the left-aoatposition will cause tbe 8085 to run at 2 Mhz.Putting Switch 4 in the right-aost positionwill cause the 8085 to run at 5 Khz.

This switch is not designed to be changedwhile running. It may work while running. butyour program may also bo.b. We aake noguarantees!

Note that this switch affects the 8085only. The 8088 always runa at 5 Mhz.

These CPU speeds apply to the standardboard. Your particular board may havedifferent crystala inatalled for faateroperation.

IMSAI FRONT PANEL USAGE

If you are using an IHSAI type frontpanel. you will need to install ju.per J6. J6is located at the lower left-hand corner of theboard. If you are not using an 1MSAl typefront panel. do not install J6.

Note that installing J6 will cause the CPU8085/18 to no longer aeet the IEEE S-100apecification. so be aware.

RESET OPTION JUMPER

The way the CPO 1015/88 ia shipped fromthe factory. both CPUs will be reset whenever aPOe* or USET* occurs (usually at power-on andevery ti.e the I.eaet pushbutton is pressed).You aay desire the 8088 to not be reset when a

front panel reset occurs. but only at power-on.If this ia the case. you will need to changebow J7 is jumpered. J7 is located between U16and U17 and consists of three pads labeled A. !and C. As the board is shipped. there is asmall trace connecting pads A and ! on theaolder side of the board. Using an )(ACTOknife. carefully cut this small trace takingcare not to damage any adjacent traces. Theninstall a jumper connecting pads Band C. ThisviII cause the 8088 to be reset only at power­on and the Reset button will have no effect.

The normal mode of operation would be toleave pads A and! connected so that bothprocessors are reset together.

USING MEMORY MANAGER

The Compupro Hemory Manager scheme worksas follows:

A standard 8 bit microprocessor (such asthe 8085) can only directly add res a 64K bytesof memory. That takes a 16 bit address bus.But the new IEEE S-100 standard provides for 24bits of sddress bus which allows addressing of16 megabytes. The problem is how to allow aprocessor with only 16 bits of address toappear to have 24 bits.

What we have done is to take an eight bitoutput port and latch sny dsta byte that iswritten to it. This latched information isthen buffered and placed on the upper 8 addresslines on the 5-100 bus (A16-23). Now an 8 bitprocessor has sccess to 16 megabytes instead ofi t8 usual 64K bytes.

Those that are familiar with bank selectschemes will sppreciste that this is quitesimilar, but instead of having the portduplicated on every memory board. it appears inonly one place in the system. The biggestadvantage that this has over bank selectschemes is that the physical memory bosrds arestandardized because of the IEEE definedaddress lines.

So when using the 8085 one just writes an8 bit word out to the output port that isselected by the setting of Dip Switch 3 andthen by the beginning of the next cycle thataddress will sppesr on A16-23.

But things are a bit different when usingthe 8088. The 8088 has 20 address bits so itcan directly address 1 aegabyte of memory. TheMemory Manager is smart enough to know if the8088 is in control of the bua. If the 8088 isin control. only the upper four bits of thememory manager port are used and the lower fourcome direct from the 8088. In other terms. AD­19 come froa the 8088 and A20-23 come from theMeaory Manager latch.

As with the 8085. the 8088 will write a

5/81 7

full byte to the port. but only the upper fourbits will ever see the bus. The full byte islatched, however, and all eight bits willappear on the bus when the 8085 comes back. online.

You may have the 8088 in one mode and the8085 in the other or both the same. See theOption Selection section of this manual (DipSwitch I, locations 4 and 5) to determine how __to select the modes you deaire.

Note that if you elect the RESET mode forthe 8085 and the power-an-jump is enabled, the8085 will do a power-on-jump sequence each timeit comes on line.

Since the command to swap processors is anIN instruction, and the purpose is not reallyto read any information from the input port, FFhex will be returned in the A register. Thismeans that any previous contents will be lost.So if the contents of the A register areimportant to you, be sure to store it somewherefirst ( a PUSH instruction would be the mostlikely) •

The last obvious consideration is that oneprocessor should generally not modify theexecution or stack areas of the otherprocessor. This requires careful planning onthe part of the programmer.

The complete software picture wouldrequire an entire book in itself and aaybe

~someone out there would like to write one, butthis manual viII not attempt to delve into itany further.

All eight bits will always be cleared (setto 0) on power up. See the Option Selectionsection of this manual for aore optionsconcerning the Memory Manager. (Dip Switch I,positions I and 2, and Dip Switch 3.)

SWAPPING PROCESSORS

On power-up, the 8085 will always be incontrol of the bus and the 8088 will be asleep,juSt as if it was never turned on. To changeover to the 8088, and to subsequently changeback and forth, all that need be done is asimple INPUT instruction from the ProcessorSwap Port.

This port is shared with the memorymanager port in that they share the sameaddress space. Hence they are both set withdip switch 3. The memory manager uses theoutput side, and the swap function uses theinput side. The "standard" port address is PDhex. See the Option Selection section of thismanual to find out how to set this address.

When the 8088 comes on line for the firsttime, it will go through its normalinitialization sequence, which is that it willbegin to execute code at address YFFFO (OFFPFOif you take the Memory Manager into account).After that first time it comes on line thereare two optional ways for it to come on linethereafter.

One is just like the first, in that aRESET will be issued to the 8088 before anyexecution can ensue. This will cause it toagain begin to execute code at FFFFO.

The other mode is one where the 8088 just"sleeps" in place until it is reawakened, whenit picks up where it left off as if nothing hadhappened.

Either mode can be useful depending on theapplication. The RESET mode may be useful in adevelopment atmosphere, but the sleep mode maybe more practical in a real-time environment.

The 8085 can work in just the same way asthe 8088. It will either do a normal power-ansequence (where it executes at 0000) or it cando a power-an-jump if enabled, when the systemis powered up.

After the 8088 gains control, by the 8085doing an IN to the processor swap port, youhave the same options for when it comes back online as you do with the 8088.

The following is an example of a typicalprogram flow using both processors, assumesleep mode for both:

Co.puter Paver. UpSOliS doe•.• po....er-oo-ju.pPrOllr•• belto. to executeTi.e to .w.p praceaeoraLoad 1D object .odule for 11088Set up juap to 8088 code at FFn'O bex,...b .l resaterDo _ DI fro. port PO blU:(all. board b.rdvare put. 808S to .leep

aDd vu.ea up 8088)8088 IlOV DD 11Ae8088 beli.D.a uecutiou at FFn'O be..z.Juap to object aodulePerfora t.aalr.Ti.e to ......p praceaaor.

(te: meed .oaetb111l1 froa dialr.)Put info to be p..aed io tAM

(ie: taalr. ialo: drh'e nuabe.r, _ctoretc. )

Puab A relhterDa _ U froa port PO bu:S08S baclr. DO linePop A reshterPerfora ta.akPuab .l reliaterDo _ III froa port PO bexS088 bac:k DO liDeetc:.

-

8 CPU 8085/88· COMPUPRO PRODUCT. GODBOUT ELECTRONICS· BOX 2355 OAKLAND AIRPORT. CA "4614

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NOTES

5/81 9

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5/81 11

CIRCUIT DESCRIPTION

The CPO 8085/88 contains four basicsections of circuitry. They are: The Processorand Bus Interface Circuitry, the Processor SwapCircuitry, the Memory Hanager Circuitry and thePower-an-Jump Circuitry. We will discuss eachsection individually.

The processor and 5-100 Bus interfacecircuitry performs the necessary primitivefunctions such as prOViding clocks to the CPUs,signal buffering and timing conversion to fitthe 5-100 IEEE standard. Some signals are"synthesized" for the 5-100 bus since neitherCPU generates those signals directly.

The 8085 has a built-in clock generatorwhich the CPO 8085/88 takes advantage of whenrunning at 5 Mhz. A crystal that is two timesthe desired frequency is hooked across theappropriate pins. In this case the crystal isX3 and is 10 Mhz which gives us the desired 5Mhz operating frequency.

But in-between the crystal and the 8085 isa 5POT switch, 54. 54 allows either thecrystal to be hooked up directly to the CPU orallows insertion of a 4 Mhz clock signal (moreabout that signal later). This causes the CPUto run at 2 Mhz.

The 8088 requires a completely differentclock circuit. It requires a clock frequencythree times the desired operating frequency andit must have a 63/33 % duty cycle. For this weuse the Intel 8284 IC, a clock generatordesigned specifically for the 8088/86. The ISMhz crystal, X2 is hooked up to the 8284 whichthen provides the necessary division by threeand the proper duty cycle. No provision hasbeen made, other than by changing the crystal,to alter the 8088's operating frequency.

The 5-100 bus requires a 2 Mhz clocksignal on pin 49 regardless of the operatingfrequency of the processor. This is prOVidedby an oscillator comprised of three sections ofU8 and Xl, a 4 Mhz crystal. The 4 Mhz outputof the oscillator is used above to run the 8085at 2 Mhz. The 4 Mhz signal is also divided bya flip-flop to 2 Mhz, is buffered and goes outto the bus.

Both processors have a bi-directional databus. Both are tied together (one is alwaystri-stated). The resultant data bus isbuffered by U37 and then goes out onto the DObus. U37 can be tri-stated by the DOD5B*signal on the 5-100 Bus. The 01 bus isbuffered by U38 and U38's outputs are tied tothe internal data bus. Those outputs areenabled by the DBIN signal, but will bedisabled by the POJ* signal or the RUN line onthe 5-100 bus. RUN is used by 1MSAl-type front

panels to force data into the CPU over the 16pin cable (J2) so the 01 buffer should be ­turned off. A pull-up resistor is prOVided onthe RUN line so that systems not utilizing thisline will still work. Note that RUN is nolonger a specified signal on the 5-100 Bus.

Both the 8085 and the 8088 put the lower 8address bits on the data bus during the firstpart of the cycle. The ALE signal from bothprocessors is used to latch this information.Both ALE signals are ORed by a section of U23to generate the 5YSALE signal. We now have acommon ALE signal for the whole card that willrepresent the 8085 ALE when it is in controland the 8088 ALE when it is in control.

The data bus is tied to the inputs of of035, a 74L5373 transparent latch. The latchcontrol is hooked to the SYSALE signal. Thislatches the address information from the databus. The outputs of 035 become AD-A7 on the 5­100 Bus.

A8-IS fro~ both processors are tiedtogether (one is always tri-stated) and arebuffered by U36 and go out onto the 5-100 bus.Both U35 and U36 may be tri-stated by the ADSB*signal.

The 8085 has three lines; SO, 51, andIO/M* from which all of the possible states ofoperation (status) may be decoded. The 8088has three similar lines; 550, 10/M* and DT/R*.The code on the two sets of lines is completelydifferent. All the lines from the 80B8 aretri-stated during a HOLD, but 50 and 51 fromthe 8085 are not. Two sections of U40 allowthese two signals to be tri-stated, beingcontrolled by the HLDA signal from the 8085.

The two sets of three lines may now betied together. These are fed into a bipolarPROM, U30, that decodes the signals into the 5­100 status signals. But the codes on the twolines are different. The CPU 8085/88 has asignal called 8/5* that is high when the 8088is in control and low when the 8085 is incontrol. This signal is used to select betweentwo sets of data inside the PROM so that thethree lines are decoded differently dependingon which processor is driving the lines.

The status signals are buffered by U39 andthen go out to the 5-100 bus. The outputs ofU39 may be tri-stated by the 5D5B* signal.

The processor control signals on the 5-100Bus, p5YNC and the like, are the most difficultto synthesize, so we will discuss each signalseparately.

The signal p5YNC is used to signify the •beginning of each machine cycle. The SYSALEsignal occurs at the beginning of each machine

12 CPU 8085/88· COMPUPRO PRODUCT. GODBOUT ELECTRONICS. BOX 2355 OAKLAND AIRPORT, CA 9"'6''''

•

cycle so it makes sense to use that for pSYNC.It cannot be used directly because it does nothave the proper relationship to the bus clock.

SYSALE sets a flip-flop by clocking in a"1" as it rises. The output of the flip-flopis connected to the D input of another flip­flop. The second flip-flop is clocked by thesystem clock so that after the next rising edgeof the clock its output will go high. This isthe pSYNC signal.

When the inverting output of the secondflop goes low it clears the first flip-flopwhich makes the D input to flop 2 go low. Onthe next rising edge of the system clock thislow will be clocked out ending the pSYNCsignal.

The first flip-flop is needed because ALEis not guaranteed to be stable during thatfirst rising edge of the clock.

The signal pSTVAL* goes low to signifythat the address and status bus are stable andcontain valid information. This signal isgenerated by NANDing pSYNC with inverted systemclock.

The signal pDBIN is used to signify thatthe CPU wants to read data on the DI bus. Itis the read strobe for the S-100 bus. The S­100 bus specification states that pDBIN shouldgo high during a memory read, input orinterrupt acknowledge cycle.

The RD"" signals from the CPUs will go lowfor a memory or t/O cycle, but not for aninterrupt acknowledge cycle. The INTA* signalgoes low for interrupt acknowledge cycles.

So to synthesize the pDBIN signal theINTA* signals from both CPUs are tied together,as are the RD* signals. (As with the data bus.only one is ever active). The composite RD""and INTA"" signals go into the inputs of a NANDgate which prOVides inversion and an ORfunction at the same time. So either RD"" orINTA"" can cause pDBIN. -

The output of this gate is the DBIN signalused on-board. but occurs too early to meet theS-100 Bus spec. Therefore the DBIN signal isgated by the inversion of pSYNC so that pDBINcannot start until pSYNC is low. The resultantsignal is inverted and becomes pDBIN.

The signal pWR* is used to signify thatvalid data is on the DO bus to be written intoa memory or I/O device. It is the generalizedwrite strobe for the S-100 bus.

Both WR* lines from the CPUs are tiedtogether (one is always tri-stated). Thesignal direction is OK for the S-100 bus. butthe timing is not. The S-100 Bus spec statesthat data must be valid before the leading edgeof the write strobe and after the trailing edgeof the write strobe.

The 8085 and 8088 guarantee data to bevalid after the trailing edge, but not beforethe leading edge. Therefore we must delay theleading edge of pWR*. Delaying pWR"" until thenext positive clock edge will meet the timingrequirements nicely, so we do just that.

The write strobe is presentedsimultaneously to one input of an OR gate andthe D input of a flip-flop. The clock input tothe flip-flop is the system clock which hasbeen clocking in a high from the inactive writestrobe. so the output of the flop will be high.The output of the flop is connected to theother input of the OR gate.

So when the write strobe is inactive(high), both inputs to the OR gate will be highmaking the output high. When the write strobegoes low, one input to the OR gate will go lowbut the output will remain high. After thenext rising edge of the clock the output of theflip-flop will go low making the other input tothe OR gate low. The two lows will cause theoutput of the OR gate to go low making our pWR""signal. When the write strobe returns high, sowill the output of the OR gate ending pWR"" atthe right time.

The pHLDA signal is used to signify thatthe processor has relinquished the bus toanother temporary master. usually a DHA device.The generation of this signal will be coveredunder the section concerning the processor swapcircuitry.

All of these signals are buffered by U27and go out to the S-100 Bus. U27 may be tri­stated by assertion of the CDSB* signal.

The two RDY signals on the 5-100 Bus areused to extend the current bus cycle for slowmemory. single stepping etc. They are ANDedtogether along with the on-board I/O wait stategenerator. The resultant output is thenconnected directly to the 8085 RDY input. butis synchronized to the clock by a flip-flop forthe 8088. The output of the flip-flop goes tothe ready input of the 8284 and then to the8088 itself. The flip-flop is necessarybecause of a timing idiosyncracy in the 8284.

The on-board wait state generator is aflip-flop whose D input is an extended ALEderived from the pSYNC generator. This isclocked in and out by the system clock, causingooe wait state to be generated. The CLR inputto the flip-flop is tied to the IO/M line fromboth processors which is low during memorycycles. This will cause the flip-flop to beinactive during memory cycles so that waitstates will only be generated during I/Ocycles.

The output of the flip-flop isconnected/disconnected from the ROY circuits bya dip switch.

5/81 13

The interrupt lines. NMI* and pINT* areinverted and then gated by some AND gates thatare turned on and off by the 8/5* line and itsinversion. This logic is used to ateer theinterrupt inputs to the processor currently online.

The MWRT signal is the memory write strobefor the S-lOO bus and is generated by NORingpWR* and the atatus line sOUTo MWRT aay bedisconnected from the bus by a dip switch.MWRT is buffered by a section of 031.

The power-on-clear circuitry i. used toinitialize on board logic and also to generatethe POC* signal for the S-lOO Bus. Tri-statebuffers are enabled by the POe* signal to 8lsodrive RESET* and SLVCLB.* low at power-on. perthe S-lOO bus spec.

A simple Be time coostaot is foraed by 1.15and C9 vhich is buffered by a section of U40acting as a schmitt trigger.

This completes the description of theProcessor and Bus Interface Circuitry. Next veviII describe how the Processor Svap Circuitryoperates.

PROCESSOR SWAP CIRCUITRY

It is the job of the processor svapcircuitry to handle the orderly change-overbetween the two CPUs on the CPO 8085/8&

The basic theory is this: One processor is"put to sleep" by pulling its BOLD line high.This line is oormally used for OMA. We are toldby the CPU that it has gone to sleep(relinquished the bus by tri-stating itsoutputs and suspending all internal operations)by the HLDA line that is active high.

What the processor swsp circuitry does isto alternatively make the BOLD line to eachprocessor high and low to control which one ison line. Since the HOLD line is also normallyused for DMA. some logic must be provided tosteer the pHOLO* line from the S-lOO bus to theprocessor on line. and to arbitrate between ahold from the bus and an internal hold.

There must also be a "command" signal thattells the circuitry to change processors. Thisis done by decoding an I/O port and making acommand pulse each time an access is done.This port address is shared with the MemoryManager circuitry (described later).

At power-on. the signal 85BOLD from theoutput of flip-flop 010 viII be low. and theaignal 88BOLO from the output of flip-flop U9vill be hilh. This means that the 8085 viIIcome up runninl and the 8088 viII be held. Alsoa ailnal named 8/S* will be low signifying thatthe 808S is in control. This aignal orilinatesfrom flip-flop OS.

The I/O port is decoded by the 2SLS2S21eilht bit comparator. 034. The output of U34is inverted and applied to one input of 03. athree input NAND late. The other two inputsare tied to pDBIN and siNP. When all threesignala are high the output of 03 will go low.This is inverted and used to clock a flip-flop.U2. The flip-flop's D input is tied highmaking the non-inverting output of the flop gohigh. The non-inverting output is tied,tbrough tvo inverters for delay. to the clearinput of the flop. So after two gate delaystbe flip-flop will be cleared. This produces ashort pulse at ita outputs. This signal iscalled PORTPULSE*. and is the swap commandpulse we need.

When PORTPULSE* occurs. it sets the outputof UlOa to a one. Assuming there is no DMArequest from the bus PHOLO (an internsl boardiaveraion of the .bus pBOLD*) viII be low. Thisallows the high from OlOa to pass through theOR gate 023, presenting a high to the D inputof OlOb. On the next positive transition ofthe 80SS clock. the output of OlOb (85HOLD)viII go high. This causes a hold request to beissued to the 8085.

When the BOSS is done with the currentcycle or cycles it will raise its BLDA line.5HLDA. This indicates that the 8085 outputsare tri-stated and internal operations havebeen suspended. When 5HLDA rises it will clocka low out of flip-flop U9a. This lov will passthrouah OR gate U23 and appear at the D inputto 09b. After the next rising edge of the 8088clock. tbe output of D9b (S8HOLD) will go low.This will allow the 8088 to begin operations.

On the next occurrence of PORTPULSE* thewhole process will be reversed.

PORTPULSE* viII also clock D4b which isset up as a divide by two toggle. U4b's outputwill be low at power-on. This output is tiedto the 0 input of USa. The output of USa(8/S*) will also be low at power-on. The clockinput of 058 will be clocked by either SHLDA orBHLDA going low. signifying a processor comingon line.

So vhen PORTPULSE* occurs U4b will changestates. and when a processor comes on line thestate of U4b viII be clocked through USa.changing the state of the 8/S. line. This letsthe on-board circuitry 1t.now which processor isin control.

The aignal that clocks OSa (a1gnifyin& aCPO co_ing out of a hold atate) also clocksU4.. 04a then produces a pulse calledBOLDOVEll*. The aignal that clocks USa and U4aia inverted (which aeans it nov signifies a CPUgoing into the hold atate) and used to clockUl2b. The D input of Ol2b is the PBOLD signal

•14 CPU 8085/88' COMPUPRO PRODUCT. GODBOUT elECTRONICS. BOX 2355 OAKLANO AIRPORT. CA 84814

which will be low if there is no bus OMArequest.

The output of U12b is BHLOA, which afterbeing buffered becomes pHLOA on the S-100 Bus.So if there is no bus hold request (PHOLD low),when U12b is clocked. BHLDA will remain low.This is exactly what we want - ve don't wantthe bus to see the internal hold operations.

But if PHOLO is high. BHLDA will go high.When the HOLDOVER* pulse occurs. at the end ofthe DKA. 012b will be reset causing BHLOA toreturn low.

Some arbitration is needed to hold off ahold request from the S-100 Bus during aprocessor swap. This is accomplished withflip-flop U2b and a NOR gate 014.

The pHOLD* signal from the S-100 Bus goesto one input of the NOR gate. The other inputcomes from the output of U2b. This output isnormally low, allowing the pHOLD* signalthrough the gate (with inversion). The outputof the gate becomes PHOLO. When PORTPULSE*occurs, a high will appear at the output of U2bwhich will inhibit pHOLO* from going throughthe NOR gate. The HOLOOVER* pulse will clearU2b allowing pHOLO* through the gate again.

PHOLO is allowed to ripple through thesections of U9 and U10 because of OR gate U23.This allows the hold request to get to theprocessors, unless it is held off by thepreviously discussed circuitry.

When the processor changes, so must thesystem clock. This is accomplished with aflip-flop. U12a, and some tri-state buffersfrom U24.

The flip-flop is constantly being clockedby the current system clock. The non-invertingoutput is hooked to the .tri-state control ofone section of U24 (U24b) and the invertingoutput is hooked to the tri-state control ofanother section of U24, U24a. The D input tothe flop is hooked to the 8/5* line.

The input to U24b is the clock from the8085 and the input to U24a is the clock fromthe 8088. Since the tri-state inputs areconnected to opposite outputs of U12a, only onesection of U24 will be turned on at a time.

When 8/5* changes, the change viII bereflected in the outputs of U12a which willturn on the appropriate section of U24 allowingthe correct clock to become the system clock.

The last section of the processor swapcircuitry concerns the Reset-On-Swap option.This circuit allows a RESET to be issued to theprocessor that is just coming on line.

U7 is a 74LS221 dual one-shot. A one-shote produces a pulse of a fixed duration inresponse to an edge-triggered input. Theduration of the pulse is set by a resistor andcapacitor.

The resistors and capacitors in this caseare R3 and 4. and C5 and C6. Their values willproduce a pulse of about two microseconds.

The trigger inputs are the HLOA signalsfrom the CPUs. The trigger inputs of U7 areset up to trigger on the negative going edge.So, for example, when 5HLDA falls (signifyingthat the 8085 is about to come on line) a 2microsecond pulse will be issued from U7. Thispulse goes to the 8085 reset input which causesthe processor to reset.

The outputs of U7 Illay beconnected/disconnected from operation by meansof a dip switch.

This completes the section on theprocessor swap circuitry. Next we will explainthe Memory Hanager.

MEMORY MANAGER CIRCUITRY

The function of the memory manager is moreclearly defined in the section entitled U5INGTHE MEMORY MANAGER. Please refer to thatsection for an explanation of what the memorymanager's functions are. Here we will onlyexplain how the circuitry works.

As explained in the previous section, thememory manager's port address decoder is sharedwith the processor swap port. The processorswap port uses the 'input' side. while thememory manager uses the 'output' side.

The output is decoded by the signal frolllU34, sOUT and the inversion of pWR*. Thesethree signals are connected to the inputs of athree input NAND gate, U3. The output of U3will go low when all three inputs are high,signifying an output to the selected port. Theoutput will return high at the end of theoutput cycle. but data will still be valid.

. This positive going edge is used to latchdata from the data bus into U28, a 74LS273octal latch. The upper four outputs of thelatch go to U33. a 74LS373 octal transparentlatch. The lower four outputs of U28 go tohalf the inputs of U29, a 74L5157 quad twoinput. multiplexer.

The control input to the multiplexer isthe 8/5* line. When 815* is low. signifyingthat the 8085 is in control, the four outputsof U28 pass through the multiplexer to theother four inputs of U33. But when the 8088 isin control (815* high), the four outputs of themultiplexer no longer repreaent the outputs ofU28, but instead represent A16-19 from the8088.

SYSALE is used to latch the outputs fromU28 and U29 into U33. The outputs of U33become the S-100 extended address bits A16-23.SYSALE is needed because the 8088 only puts

5fS 1 15

OTHER ELECnICAL COMPONENTS

Parts List

INTEGRATED CIRCUITS (NOTE: the follOWingparts may have letter suffixes and prefixesalong with the key nu.bers given belo"'.

ADDITIONAL COMPONENTS FOR 8088 OPTION

-

o

(U20)(U19)

(X2)(C8)

(SI-3)(S4)

(XI)(X3)

(Cl-4,9)(C5,6)

(C7)

(R13)

(R5,6)(R8)

(R 14)(R1,3,4)

(R2,7,9-12,16,15)

NANDNOR

quad 2 inputquad 2 inputhel: inverterhel: inverter D.C.quad 2 input ANDtriple 3 input NANDquad 2 input ORdual 0 f l1p-f lop

low profile sockets8 position DIP switchespaddle 8",i tchheat sinkssets 6-32 hardwarecard ejectorsset user's manuals

74LSOO74LS0274LS0474LS0574LS0874LSIO74LS3274L574

Circuit Board

crystal. 4 Khzcrystal, 2 time••0.5 treq.39mfd, lOY tantalum capacitor.001mfd disc capacitor.Olmfd disc capacitorbypass. di8c capacitor270 ohm resistor390 ohm resistor1K ohm resistor2.7K ohm resistor4.7K ohm resistorSIP resistor networks

(U11,16)(U 14)

(U8,13,15,32)(U25)

(Ul,6,17)(U3)

(U23)(U2.4.5,9,lO12,18,21,22)

74LS125 quad tri-state driver (U24.31)74L5157 quad 2 input HUX (U29)74LS221 dual one shot (U7)74LS240 octal inv. bus driver (U26)74LS244 octal bus driver (U36-39)74LS273 octal latch (U28)74LS367 hex bus driver (U27,40)74LS373 octal trn.prnt latch (U33,35)25LS2521 octal comparator (U34)G165 32x8 bipolar PROM (U30)8085A-2 5 Khz microprocessor (U41)7805 5 volt regul.tor (U42,43)

8088 5 Khz 16 bit MPU8284 clock leneratorcrystal, 3 tim•• e088 tnq.lOpfd disc capacitor

0(1)

0(1)0(1)0(1)00)

MECHANICAL COMPONENTS

0(42)0(3)0(1)0(2)o (2)0(2)o (1)

0(1)

0(1)0(5)0(2)o (1)o (34)o (1)

0(2)0(1)

0(1)o (J)0(8)

o (2)o (l)0(4)0(1)

0(3)0(1)o (l)

0(')

0(2)0(1)0(1)o (I)

o (4)0(1)

0(2)0(2)0(1)o (1)

o (1)0(2)

This completes the description of thememory manager circuit. Next ve will discussthe operation of the pover-on-jump circuit.

POWER-ON-JUMP CIRCUITRY

The output of U16 (POJ·), can be disabledby a dip svitch, which will cause the power-on­jump circuitry to be inactive.

The power-on-jump circuitry will activateafter a POC·, and if desired, after eachRESET.. This option is a180 set with 8 dipswitch.

This completes the circuit description ofthe CPO 8085/88.

address info on the A16-19 lines during thefirst part of the cycle (as it does with thedata/address lines). It also ensures that theaddress on the bus changes at the first part ofthe next cycle. instead of the last part of thecurrent cycle.

U28 will be cleared at power-on. It mayalso be cleared by each successive bus RESET·depending on the position of a dip switch.

The outputs of U33 will be tri-stated by aPOC·, RESET. or ADS!.. ADSa· can be ignnred bythe memory manager by setting a dip-SWitch.

The power-on-jump circuitry used in theCPU 8085/88 is designed to allow the 8085 tobegin execution of a program at some addressother than 0000. It does this by forcing ajump op-code (C3 hex) followed by a byte ofzeroes and then an eight bit value thatcontains the starting address of the page youvant to jump to.

At power-on, flip-flop USb is cleared,setting its non-inverting output high. Thisoutput is connected to one input of NAND gateU16. The other input to U16 is connected toORIN. Yhen both signals are high, the output(POJ.) will go low. This will enable the octalbuffer U26 a~~ disable the normal 01 driver,U38.

At address O. a C3 hex will be presentedto the inputs of U26 and thus to the 8085. C3is the 'jump' op-code. At address I, a byte ofzeroes will be presented to the inputs of U26.At address 2, the setting of dip switch 2 willbe presented to the inputs of U26. The settingof dip switch 2 should correspond to the upperbyte of the desired memory address.

Finally. at the next address, US willclock its non-inverting output low, causing U26to be tri-stated and the normal 01 buffer to bere-enabled. This allows the next byte to beread from the bus, and normal execution ensues.

16 CPU 8085/88' COIt4PUPRO PRODUCT. GODBOUT elECTRONICS' BOX 2355 OAKLAND AIRPORT, CA 946,..

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o

110

Component Layout

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II P~RIOD •II PULSE WIDTH RICK

II PULSE WIDTH LOW

DELAT ~ HICK TO pSYNC HIGH: DELAT IIHICH TO psnrc LOW

pSYIlC PULSE WIDTH HICK.

pSTVUI LOW PRIOR TO II RICH

DOllING ,SYNC.

pSTVAL* PULSE WIDTH LOWDELAT pSYNC IIICII TO pSTV,u* LOW

ADDRESSES STAaL! PRIOR TO pSTVAL*LOW Dl/IIUIC ,SYNC HIGH

STATUS STAaL! PRIOR TO pSTVAL LOW

DURING ,STNC KIGII ••••••

pOBIH PULSE WIDTH RIGH •DZLA Y pSTVAV LOW TO pDIIK RIGII

DELAT pOliK LOW TO ,SYNC RrCH

HOLD TIKE POil. "DDUSSES • STATUS APTER

pDIIK LOW •••••

DELAY pSTVAL* LOW TO DATA VALID

pllRa PULSE WIDTH LOW

DI!.LA'f pSTVAL* LOW TO pllRa LOW

DELAY pllR' HICH TO ,SYMC KIGHS!TUP TIRE DO VALID TO pWilI LOI/.

HOLD TIKE ADDRESSES PROK pllRa HICH

MOLD TIME STATUS 'ROM pllRa HIGH.

IlOLD T1KE DO nOM pWR. HIGH.

DELAY pllR. LOW TO KWIl.T HIGH; pllR.

HIGH TO KllII.T LOW • •

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I.ii I

•

8088.5mlut~ • 200 ns

30

200 166 2000

65 0.4tCT

110 O.4tCT

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260 O.9tC!

140 30

320 0100 O.ltC!

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140 0.2tC!

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10

20 10

180 0.1tCt

180 70

200 40

120 0

120 50

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, rUtOD •••••

, PULSE VlurB HIGB

• POLSI Vltml LOW

OIU't • BlCB 1'0 ,SftC BlCB: DnAY •

RICK TO pSflIC LOW • • • •

pSflIC POLS! \IUIt8 RIGB • • •

pSTV.l1.* LOW ,,1.101. TO • IlCB

IlUIIl'C ,S!Me • • • •• •

,StVAL' PULSI WIDTB LOW

DILAT ,STIle BlGB TO ,ST'll' LOll

ADDUSSIS STULl PlIOI. TO pSTVAL*

LOll CUURC ,SYIIC BIGII •••••

'UTUS STABLE nIDI. TO ,STVA!. LOW

DUUG ,S!MC BIGll

pD1l1'I PULSI I/tIl'r8 8tCll • • • • •

DlUt pstVAL* LOW TO pOUM B1C~1I

DIUt pDUll LOll TO ,StllC HIGH

IIOLD TIM.! 1'01. ADllU5SIS , STATUS AlTD

pOll' LOll • • ••••••••

DIU.! ,STVU.'" LOW TO Ilo\U 'ALIo

,W' PULSI IIIDTB LOW • • • • •

DILlY pSTVAL* LOW TO ,11I.* LOW •

DIUt ,11I.* 11GB TO pSYltC BICIl

SETUP TlK! DO VALID TO ,WI LOW

IIOLD TIK! ADDIl.!SSIS noN ,Wl* HIGH

HOLD tIKI STATUS noM pill" KICK.

BOLD TIM! DO PIlOt( ,WI KIGH.

DILAT pill' LOW TO """T lIca; ,Wl'

IllCK to HIlI! LOW • •

'CT

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"'"<ii,iiiiitlOUt

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,n-<CTL

'OS,

-...

CUSTOMER SERVICE INFORMATIONOur paramount concern is that you be satisfied with any Godbout

CompuPro product. 11 this product fails to operate property it may bereturned to us, see warranty Information below.

If you have any Questions about assembly, performance. specifica­tions or need further information feel free to write us at

P.O. Box 2355, Oakland Airport, CA 94614.

When writing, please be as specific as possible concernmg the natureof your query. We maintain a 24 hour a day phone. for taking orders,(415) 562-0636. If you have problems or questions which cannot behandled by mail, this number can be used to connect you with our tech­nical people ONLY during normal business hours (10am-Spm PacificTime). Unfortunately, we cannot return calls, or accept collect calls.

LIMITED WARRANTY INFORMATION

Godbout Electronics will repair or replace, at our option, any partsfound to be defective in either materials or workmanship for a period of 1year from date of invoice. Defective p::lrts must be returned for replace­ment.

If a defective part or design error causes a Godbout Electronics pro­duct to operate Improperly during the 1 year warranty period, we willservice It free (original owner only) If delivered and shipped at owner'sexpense to Godbout Electronics If improper operation is due to an erroror errors on the part of the purchaser, there may be a repair charge.Purchaser will be notified if this charge exceeds $50.00.

We are not responsible for damage caused by use of solder intendedfor purposes other than electrOnlc equipment construction. failure tofollow printed instructions, misuse or abuse. unauthorized modifica­tions, use of our products in applications other than those intended byGodbout Electronics, theft, fire. or accidents

Return to purchaser of a fully functioning unit meeting all advertisedspecifications in effect as of date of purchase is considered to be com­plete fulfillment of all warranty obligations assumed by GodboutElectronics This warranty covers only products marketed by GodboutElectronics and does not cover other equipment used in conjunctionwith said products We are not responsible for incidental or consequen­tial damages.

Prices and specifications are subject to change without notice, owingto the volatile nature and pricing structure of the electronics industry

"CPU 8085/88" is a t.rademark of W.J. Godbout..

"TRI-STATE" is a t.rademark of National Semiconductor Corp.

Content.s of t.hisrights reserved.review if source

booklet. Copyright. 1981We encourage quot.ationis credited.

by Godbout. Elect.ronics. Allfor the purposes of product

Printed in U.S.A.

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20 CPU 8085/88· COMPUPRO PRODUCT' GODBOUT ELECTRONICS' BOX 2355 OAKLAND AIRPORT. CA 9"'614