COMP541 More on Verilog; Debouncing switches
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COMP541COMP541
More on Verilog;More on Verilog;Debouncing switchesDebouncing switches
Montek SinghMontek Singh
Feb 15, 2012Feb 15, 2012
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First TopicFirst Topic More Verilog…More Verilog…
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HierarchyHierarchy AlwaysAlways make your make your
design modulardesign modular easier to read and debugeasier to read and debug easier to reuseeasier to reuse
before you write even one before you write even one line of Verilog…line of Verilog…
……draw a picturedraw a picture– black boxesblack boxes– boxes within boxesboxes within boxes
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module inv(input a,module inv(input a,
output y);output y);
assign y = ~a;assign y = ~a;
endmoduleendmodule
module and3(input a, b, module and3(input a, b, c, output y);c, output y);
assign y = a & b & c;assign y = a & b & c;
endmoduleendmodule
module nand3(input a, b, c output y); wire n1; // internal signal
and3 andgate(a, b, c, n1); // instance of and3 inv inverter(n1, y); // instance of inverterendmodule
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Internal VariablesInternal Variables Internals = those that are not inputs/outputsInternals = those that are not inputs/outputs
declare them as declare them as wirewire or or regregdepending on whether they are combinational or state depending on whether they are combinational or state
holdingholding
p
g s
un1_cout cout
cout
s
cin
ba
module fulladder(input a, b, cin, output s, cout); wire p, g; // internal
assign p = a ^ b; assign g = a & b; assign s = p ^ cin; assign cout = g | (p & cin);endmodule
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Bitwise Operators (we have used)Bitwise Operators (we have used)module gates(input [3:0] a, b,
output [3:0] y1, y2, y3, y4, y5);
assign y1 = a & b; // AND
assign y2 = a | b; // OR
assign y3 = a ^ b; // XOR
assign y4 = ~(a & b); // NAND
assign y5 = ~(a | b); // NOR
endmodule
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CommentsComments
// single line comment
/*…*/ multiline comment
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Reduction Operators (&)Reduction Operators (&)module and8(input [7:0] a, module and8(input [7:0] a,
output y);output y);
assign y = &a;assign y = &a;
// &a is much easier to write than// &a is much easier to write than
// assign y = a[7] & a[6] & a[5] & a[4] &// assign y = a[7] & a[6] & a[5] & a[4] &
// a[3] & a[2] & a[1] & a[0];// a[3] & a[2] & a[1] & a[0];
endmoduleendmodule
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Reduction Operators (|, ~|, ~&, ^, ~^, Reduction Operators (|, ~|, ~&, ^, ~^, ^~)^~) Several others (see online reference)Several others (see online reference)
| = OR all the bits together| = OR all the bits together ~| = NOR all the bits together~| = NOR all the bits together ~& = NAND all the bits together~& = NAND all the bits together ^ = XOR all the bits together^ = XOR all the bits together ~^, ^~ = XNOR all the bits together~^, ^~ = XNOR all the bits together
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Operator PrecedenceOperator Precedence
~ NOT
*, /, % mult, div, mod
+, - add,sub
<<, >> shift
<<<, >>> arithmetic shift
<, <=, >, >= comparison
==, != equal, not equal
&, ~& AND, NAND
^, ~^ XOR, XNOR
|, ~| OR, XOR
?: ternary operator
Highest
Lowest
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NumbersNumbers Format: Format: N’BvalueN’Bvalue
N = number of bits, B = baseN = number of bits, B = base N’B is optional but recommended (default is decimal)N’B is optional but recommended (default is decimal) whenever in doubt, specify the # of bitswhenever in doubt, specify the # of bits
Number # Bits Base Decimal Equivalent
Value Stored
3’b101 3 binary 5 101
’b11 unsized binary 3 00…0011
8’b11 8 binary 3 00000011
8’b1010_1011 8 binary 171 10101011
3’d6 3 decimal 6 110
6’o42 6 octal 34 100010
8’hAB 8 hexadecimal 171 10101011
42 Unsized decimal 42 00…0101010
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Bit Manipulations: splitting bits Bit Manipulations: splitting bits offoff
module mux2_8(input [7:0] d0, d1,module mux2_8(input [7:0] d0, d1,
input s,input s,
output [7:0] y);output [7:0] y);
mux2 lsbmux(d0[3:0], d1[3:0], s, y[3:0]);mux2 lsbmux(d0[3:0], d1[3:0], s, y[3:0]);
mux2 msbmux(d0[7:4], d1[7:4], s, y[7:4]);mux2 msbmux(d0[7:4], d1[7:4], s, y[7:4]);
endmoduleendmodule
mux2
lsbmux
mux2
msbmux
y[7:0][7:0]
s
d1[7:0] [7:0]
d0[7:0] [7:0]
s[3:0] d0[3:0][3:0] d1[3:0]
[3:0]y[3:0]
s[7:4] d0[3:0][7:4] d1[3:0]
[7:4]y[3:0]
Synthesis:
Verilog:
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Bit Manipulations: packing bitsBit Manipulations: packing bitsassign y = {a[2:1], {3{b[0]}}, a[0], 6’b100_010};
// if y is a 12-bit signal, the above statement produces:
y = a[2] a[1] b[0] b[0] b[0] a[0] 1 0 0 0 1 0
// underscores (_) are used for formatting only to make it easier to read. Verilog ignores them.
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Debouncing switchesDebouncing switches
What is switch bounce?What is switch bounce?
Let’s solve it in class!Let’s solve it in class!
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Switch bounceSwitch bounce Switches bounce or “chatter”Switches bounce or “chatter”
each press/release can bounce hundreds of times!each press/release can bounce hundreds of times!
Let’s design a chatter-free switch for Friday’s Let’s design a chatter-free switch for Friday’s lab!lab!
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Lab Preview: Buttons and Lab Preview: Buttons and DebouncingDebouncing Mechanical switches Mechanical switches
“bounce”“bounce” vibrations cause them to go to vibrations cause them to go to
1 and 0 a number of times1 and 0 a number of timescalled “chatter”called “chatter”
hundredshundreds of times! of times!
We want to do 2 things:We want to do 2 things: ““DebounceDebounce””: : Any ideas?Any ideas? Synchronize with clockSynchronize with clock
i.e., only need to look at it at the i.e., only need to look at it at the next +ve edge of clocknext +ve edge of clock
Ideas?Ideas?
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