COMP541 Hierarchical Design & Verilog
-
Upload
bert-monroe -
Category
Documents
-
view
30 -
download
1
description
Transcript of COMP541 Hierarchical Design & Verilog
1
COMP541COMP541
Hierarchical Design & Hierarchical Design & VerilogVerilog
Montek SinghMontek Singh
Jan 28, 2010Jan 28, 2010
TopicsTopics Hierarchical DesignHierarchical Design Verilog PrimerVerilog Primer
2
Design HierarchyDesign Hierarchy Just like with large program, to design a large Just like with large program, to design a large
chip need hierarchychip need hierarchy Divide and ConquerDivide and Conquer
To create, test, and also to understandTo create, test, and also to understand
BlockBlock is equivalent to object is equivalent to object
3
ExampleExample 9-input odd func (parity for byte)9-input odd func (parity for byte) Block for schematic is box with labelsBlock for schematic is box with labels
4
Design Broken Into ModulesDesign Broken Into ModulesUse 3-input odd functionsUse 3-input odd functions
5
Each Module uses XOREach Module uses XOR
6
Use NAND to Implement XORUse NAND to Implement XOR In case there’s no XOR, for exampleIn case there’s no XOR, for example
7
Design HierarchyDesign Hierarchy
8
9
Components in DesignComponents in Design RHS shows what must be designedRHS shows what must be designed
10
Reuse is CommonReuse is Common Certainly forced because of availability of parts (chips)Certainly forced because of availability of parts (chips) Also the design cycle was very longAlso the design cycle was very long Now more flexibility with programmable logicNow more flexibility with programmable logic
But still reuse from libraries or intellectual property (IP)But still reuse from libraries or intellectual property (IP) Example: buy a PCI designExample: buy a PCI design Open source, see Open source, see www.opencores.org
Note the many logic blocks available in Xilinx libraryNote the many logic blocks available in Xilinx library
11
Flow of CAD SystemFlow of CAD System
NetlistNetlist is is description of description of connectionsconnections
Generic Gates
Replaces Generic Gates
with ones available in Technology
Library
12
Technology MappingTechnology Mapping Full customFull custom
Pixel-Planes chips (machines in lobby)Pixel-Planes chips (machines in lobby) Memories, CPUs, etcMemories, CPUs, etc
Standard cellStandard cell Library of cellsLibrary of cells Engineer determined interconnectionEngineer determined interconnection
Gate arraysGate arrays Small circuits with interconnectSmall circuits with interconnect
13
Hierarchy Example – 4-bit Hierarchy Example – 4-bit EqualityEquality Input: 2 vectors A(3:0) and B(3:0)Input: 2 vectors A(3:0) and B(3:0) Output: One bit, E, which is 1 if A and B are Output: One bit, E, which is 1 if A and B are
bitwise equal, 0 otherwisebitwise equal, 0 otherwise
14
DesignDesign Hierarchical design seems a good approachHierarchical design seems a good approach One module/bitOne module/bit Final module for EFinal module for E
15
Design for MX moduleDesign for MX module Logic function isLogic function is
I’d call this “not E”…I’d call this “not E”… Can implement asCan implement as
i i i i iE AB AB
16
Design for ME moduleDesign for ME module Final E is 1 only if all intermediate values are 0Final E is 1 only if all intermediate values are 0 SoSo
And a design isAnd a design is
0 1 2 3E E E E E
17
Hierarchical VerilogHierarchical Verilog We already saw example of We already saw example of instantiationinstantiation when when
we used AND and OR gateswe used AND and OR gates
Just use module name and an identifier for the Just use module name and an identifier for the particular instanceparticular instance
Vector of Wires (Bus)Vector of Wires (Bus) Denotes a set of wiresDenotes a set of wires
input [1:0] S;input [1:0] S;
Syntax is [a: b] where a is high-orderSyntax is [a: b] where a is high-order So this could be “[0:1] S”So this could be “[0:1] S” Order will matter when we make assignments with Order will matter when we make assignments with
values bigger than one bitvalues bigger than one bit Or when we connect sets of wiresOr when we connect sets of wires
NOTE: THIS IS NOT AN ARRAY!NOTE: THIS IS NOT AN ARRAY!
18
19
MXMX
module mx(A, B, E);module mx(A, B, E);input A, B;input A, B;output E;output E;
assign E = (~A & B) | (A & ~B);assign E = (~A & B) | (A & ~B);
endmoduleendmodule
20
MEME
module me(E, Ei);module me(E, Ei);input [3:0] Ei;input [3:0] Ei;output E;output E;
assign E = ~(Ei[0] | Ei[1] | Ei[2] | Ei[3]);assign E = ~(Ei[0] | Ei[1] | Ei[2] | Ei[3]);
endmoduleendmodule
21
Top LevelTop Levelmodule top(A, B, E);module top(A, B, E);
input [3:0] A;input [3:0] A;input [3:0] B;input [3:0] B;output E;output E;
wire [3:0] Ei;wire [3:0] Ei;
mx m0(A[0], B[0], Ei[0]);mx m0(A[0], B[0], Ei[0]);mx m1(A[1], B[1], Ei[1]);mx m1(A[1], B[1], Ei[1]);mx m2(A[2], B[2], Ei[2]);mx m2(A[2], B[2], Ei[2]);mx m3(A[3], B[3], Ei[3]);mx m3(A[3], B[3], Ei[3]);
me me0(E, Ei);me me0(E, Ei);
endmoduleendmodule
22
Integrated CircuitIntegrated Circuit Known as IC or chipKnown as IC or chip Silicon containing circuitSilicon containing circuit
Later in semester we’ll examine design and Later in semester we’ll examine design and constructionconstruction
Maybe processesMaybe processes
Packaged in ceramic or plasticPackaged in ceramic or plastic From 4-6 pins to hundredsFrom 4-6 pins to hundreds
Pins wired to pads on chipPins wired to pads on chip
BondingBonding
23
24
Levels of IntegrationLevels of Integration SSISSI
Individual gatesIndividual gates MSIMSI
Things like counters, single-block adders, etc.Things like counters, single-block adders, etc. Like stuff we’ll be doing nextLike stuff we’ll be doing next
LSILSI VLSIVLSI
Larger circuits, like the FPGA, Pentium, etc.Larger circuits, like the FPGA, Pentium, etc.
25
Logic FamiliesLogic Families RTL, DTL earliestRTL, DTL earliest TTL was used 70s, 80sTTL was used 70s, 80s
Still available and used occasionallyStill available and used occasionally 7400 series logic, refined over generations7400 series logic, refined over generations
CMOSCMOS Was low speed, low noiseWas low speed, low noise Now fast and is most commonNow fast and is most common
BiCMOS and GaAsBiCMOS and GaAs SpeedSpeed
26
CatalogsCatalogs Catalog pages describe chipsCatalog pages describe chips Look atLook at
http://focus.ti.com/lit/ds/scas014c/scas014c.pdf
SpecificationsSpecifications PinoutsPinouts Packages/DimensionsPackages/Dimensions Electrical characteristicsElectrical characteristics
Electrical CharacteristicsElectrical Characteristics Fan inFan in
max number of inputs to a gatemax number of inputs to a gate
Fan outFan out how many standard loads it can drive (load usually 1)how many standard loads it can drive (load usually 1)
VoltageVoltage often 1V, 1.2V, 1.5V, 1.8V, 3.3V or 5V are commonoften 1V, 1.2V, 1.5V, 1.8V, 3.3V or 5V are common
Noise marginNoise margin how much electrical noise it can toleratehow much electrical noise it can tolerate
Power dissipationPower dissipation how much power chip needshow much power chip needs
TTL highTTL highSome CMOS low (but look at heat sink on a Pentium)Some CMOS low (but look at heat sink on a Pentium)
Propagation delay – already talked about itPropagation delay – already talked about it 27
Change Topics toChange Topics to VerilogVerilog
First a couple of syntax stylesFirst a couple of syntax styles Help you program more efficientlyHelp you program more efficiently
Verilog test programsVerilog test programs
28
29
Constants in VerilogConstants in Verilog SyntaxSyntax
[size][‘radix]constant[size][‘radix]constant Radix can be d, b, h, or o (default d)Radix can be d, b, h, or o (default d) ExamplesExamples
assign Y = 10;assign Y = 10; // Decimal 10// Decimal 10assign Y = ’b10;assign Y = ’b10; // Binary 10, decimal 2// Binary 10, decimal 2assign Y = ’h10;assign Y = ’h10; // Hex 10, decimal 16// Hex 10, decimal 16assign Y = 8’b0100_0011 // Underline ignoredassign Y = 8’b0100_0011 // Underline ignored
Binary values can be 0, 1, or xBinary values can be 0, 1, or x
30
Conditional AssignmentConditional Assignment Equality testEquality test
S == 2'b00S == 2'b00
AssignmentAssignment
assign Y = (S == 2'b00)? 1’b0: 1’b1;assign Y = (S == 2'b00)? 1’b0: 1’b1;
If true, assign 0 to YIf true, assign 0 to Y If false, assign 1 to YIf false, assign 1 to Y
31
4-to-1 Mux Truth Table-ish4-to-1 Mux Truth Table-ishmodule mux_4_to_1_dataflow(S, D, Y);module mux_4_to_1_dataflow(S, D, Y); input [1:0] S;input [1:0] S; input [3:0] D;input [3:0] D; output Y;output Y;
assign Y = (S == 2'b00) ? D[0] :assign Y = (S == 2'b00) ? D[0] : (S == 2'b01) ? D[1] :(S == 2'b01) ? D[1] : (S == 2'b10) ? D[2] :(S == 2'b10) ? D[2] : (S == 2'b11) ? D[3] : 1'bx ;(S == 2'b11) ? D[3] : 1'bx ;endmoduleendmodule
32
Verilog for Decision TreeVerilog for Decision Treemodule mux_4_to_1_binary_decision(S, D, Y);module mux_4_to_1_binary_decision(S, D, Y); input [1:0] S;input [1:0] S; input [3:0] D;input [3:0] D; output Y;output Y;
assign Y = S[1] ? (S[0] ? D[3] : D[2]) :assign Y = S[1] ? (S[0] ? D[3] : D[2]) : (S[0] ? D[1] : D[0]) ;(S[0] ? D[1] : D[0]) ;
endmoduleendmodule
33
Binary DecisionsBinary Decisions If S[1] == 1, branch one wayIf S[1] == 1, branch one way assign Y = S[1] ? (S[0] ? D[3] : D[2])assign Y = S[1] ? (S[0] ? D[3] : D[2])
and decide Y = either D[2] or D[3] based on S[0]and decide Y = either D[2] or D[3] based on S[0] ElseElse : (S[0] ? D[1] : D[0]) ;: (S[0] ? D[1] : D[0]) ;
decide Y is either D[2] or D[3] based on S[0]decide Y is either D[2] or D[3] based on S[0] Notice that conditional test is for ‘1’ condition Notice that conditional test is for ‘1’ condition
like in Clike in C
34
Instance Port NamesInstance Port Names ModuleModule module modp(output C, input A);module modp(output C, input A);
Ports referenced asPorts referenced as
modp i_name(conC, conA)modp i_name(conC, conA)
Also asAlso as modp i_name(.A(conA), .C(conC));modp i_name(.A(conA), .C(conC));
35
ParameterParameter Can set constantCan set constant
Like #defineLike #define
parameter SIZE = 16;parameter SIZE = 16;
36
Verilog for SimulationVerilog for Simulation Code more convenient than the GUI testbenchCode more convenient than the GUI testbench
Also more complex conditionsAlso more complex conditions Can test for expected resultCan test for expected result
37
ISEISE Make Verilog Test FixtureMake Verilog Test Fixture Will create a wrapper (a module)Will create a wrapper (a module)
Instantiating your circuitInstantiating your circuit It’ll be called UUT (unit under test)It’ll be called UUT (unit under test)
You then add your test codeYou then add your test code Example on next slidesExample on next slides
38
Module and Instance UUTModule and Instance UUTmodule syn_adder_for_example_v_tf();module syn_adder_for_example_v_tf();
// DATE: 21:22:20 01/25/2004 // DATE: 21:22:20 01/25/2004 // ...Bunch of comments...// ...Bunch of comments...
......// Instantiate the UUT// Instantiate the UUT syn_adder uut (syn_adder uut ( .B(B), .B(B), .A(A), .A(A), .C0(C0), .C0(C0), .S(S), .S(S), .C4(C4).C4(C4) ););
......endmoduleendmodule
39
RegReg It will create storage for the inputs to the UUTIt will create storage for the inputs to the UUT
// Inputs// Inputs reg [3:0] B;reg [3:0] B; reg [3:0] A;reg [3:0] A; reg C0;reg C0; We’ll talk more about We’ll talk more about regreg next class next class
40
Wires for OutputsWires for Outputs That specify bus sizesThat specify bus sizes
// Outputs// Outputs
wire [3:0] S;wire [3:0] S;
wire C4;wire C4;
41
Begin/EndBegin/End Verilog uses begin and end for blockVerilog uses begin and end for block instead of curly bracesinstead of curly braces
42
InitialInitial Initial statement runs when simulation beginsInitial statement runs when simulation begins
initial initial beginbegin
B = 0;B = 0; A = 0;A = 0; C0 = 0;C0 = 0; endend
43
Procedural assignmentProcedural assignment Why no “assign”?Why no “assign”? Because it’s not a continuous assignmentBecause it’s not a continuous assignment Explain more next class when we look at Explain more next class when we look at
storage/clockingstorage/clocking
44
Initialize in Default Test FileInitialize in Default Test File There’s one in ISE generated file, but don’t think There’s one in ISE generated file, but don’t think auto_initauto_init is defined is defined
// Initialize Inputs// Initialize Inputs `ifdef auto_init`ifdef auto_init
initial begininitial begin B = 0;B = 0; A = 0;A = 0; C0 = 0;C0 = 0; endend
`endif`endif
45
What to Add?What to Add? Need to make simulation time passNeed to make simulation time pass Use # command for skipping timeUse # command for skipping time Example (note no semicolon after #50)Example (note no semicolon after #50)
initial initial
beginbegin
B = 0;B = 0;
#50 B = 1;#50 B = 1;
endend
46
ForFor Can use Can use forfor loop in initial statement block loop in initial statement block
initialinitial beginbegin for(i=0; i < 5; i = i + 1)for(i=0; i < 5; i = i + 1) beginbegin
#50 B = i;#50 B = i;endend
endend
47
IntegersIntegers Can declare for loop control variablesCan declare for loop control variables
Will not synthesize, as far as I knowWill not synthesize, as far as I know
integer i;integer i;
integer j;integer j;
Can copy to input regsCan copy to input regs There may be problems with negative valuesThere may be problems with negative values
48
There are alsoThere are also WhileWhile RepeatRepeat ForeverForever
49
TimescaleTimescale Need to tell simulator what time scale to useNeed to tell simulator what time scale to use Place at top of test fixturePlace at top of test fixture
`timescale 1ns/10ps`timescale 1ns/10ps
50
System TasksSystem Tasks Tasks for the simulatorTasks for the simulator $stop – end the simulation$stop – end the simulation $display – like C printf$display – like C printf $monitor – prints when arguments change $monitor – prints when arguments change
(example next)(example next) $time – Provides value of simulated time$time – Provides value of simulated time
51
MonitorMonitor// set up monitoring// set up monitoring
initialinitial
begin begin $monitor($time, " A=%b ,B=%b\n", A, B);$monitor($time, " A=%b ,B=%b\n", A, B);
endend
// These statements conduct the actual test// These statements conduct the actual test
initialinitialbeginbegin
Code...Code... endend
NextNext Sequential CircuitsSequential Circuits We’ll put off the study of arithmetic circuitsWe’ll put off the study of arithmetic circuits
52