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COMP541COMP541

Memories II:Memories II:DRAMsDRAMs

Montek SinghMontek Singh

Mar 21, 2012Mar 21, 2012

TopicsTopics Last class:Last class:

Read-Only Memories (ROMs)Read-Only Memories (ROMs) StaticStatic Random-Access Memory (SRAM) Random-Access Memory (SRAM)

Today:Today: DynamicDynamic Random-Access Memory (DRAM) Random-Access Memory (DRAM)

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Dynamic RAMDynamic RAM Very “light-weight” bit-level memoryVery “light-weight” bit-level memory

a single a single capacitorcapacitor holds charge (= value) holds charge (= value)no charge = no charge = ‘‘00’’

a single transistor acts as gatea single transistor acts as gateWrite: connect switch & add charge to store a Write: connect switch & add charge to store a ‘‘11’’……… … then disconnect switchthen disconnect switchRead: read by connecting switchRead: read by connecting switch

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DRAM Bit CellDRAM Bit Cell Very lightweightVery lightweight

contrast with SRAMcontrast with SRAM DRAM cell consists of DRAM cell consists of oneone transistor and transistor and oneone

capacitor!capacitor! SRAM cell has at least 6 transistorsSRAM cell has at least 6 transistors

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wordline

bitline bitlinewordline

bitline

DRAM bit cell: SRAM bit cell:

Hydraulic Analogy: WritingHydraulic Analogy: Writing

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StorageFull (1)

Empty (0)Pump fills tank to 1

value

Pump drains tank to 0 value

Hydraulic Analogy: ReadingHydraulic Analogy: Reading

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Tank had a 1 value – raises

water level

Outside water begins at

intermediate level (black wavy line)

Tank had a 0 value – lowers

water level

DRAM CharacteristicsDRAM Characteristics Destructive ReadDestructive Read

When cell is read, charge is (partially) removedWhen cell is read, charge is (partially) removed Must be restored after each read!Must be restored after each read!

RefreshRefresh Also, thereAlso, there’’s steady leakages steady leakage Charge must be restored periodicallyCharge must be restored periodically

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DRAM Logical DiagramDRAM Logical Diagram

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Core memory storageControl circuitry

DRAM Read SignalingDRAM Read Signaling Since DRAM is often on a separate chipSince DRAM is often on a separate chip

number of pins available can be a limitationnumber of pins available can be a limitation lower pin count by using same pins for row and lower pin count by using same pins for row and

column addressescolumn addresses

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Delay until data

available

DRAM Write SignalingDRAM Write Signaling

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DRAM RefreshDRAM Refresh Many strategiesMany strategies

refresh circuits on chiprefresh circuits on chip here a simple row counter: reads and writes backhere a simple row counter: reads and writes back

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Refresh TimingRefresh Timing Say, need to refresh every 64msSay, need to refresh every 64ms Distributed refreshDistributed refresh

Spread refresh out evenly over 64msSpread refresh out evenly over 64ms Say on a 4Mx4 DRAM, refresh window for row Say on a 4Mx4 DRAM, refresh window for row

64ms/4096=15.6 us64ms/4096=15.6 us Total time spent is 0.25ms, but spreadTotal time spent is 0.25ms, but spread

Burst refreshBurst refresh Same 0.25ms, but all at onceSame 0.25ms, but all at once May not be good in a computer systemMay not be good in a computer system

Refresh takes low % of total timeRefresh takes low % of total time

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Bidirectional LinesBidirectional Lines Another optimization for reducing pins:Another optimization for reducing pins:

Many chips have one set of data pinsMany chips have one set of data pinssame pins used as data input for write operationssame pins used as data input for write operationssame pins used as data output for read operationssame pins used as data output for read operationsotherwise float them (i.e., tri-state)otherwise float them (i.e., tri-state)

Makes sense because donMakes sense because don’’t need both read/write data t need both read/write data at onceat once

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Synchronous DRAM (SDRAM)Synchronous DRAM (SDRAM) Has a clockHas a clock Common type in PCs late-90sCommon type in PCs late-90s

Typical DRAMs still synchronousTypical DRAMs still synchronous

Multiple Multiple banksbanks PipelinedPipelined

Start read in one bank after anotherStart read in one bank after another Come back and read the resulting values one after Come back and read the resulting values one after

anotheranother

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Modes of DRAM operationModes of DRAM operation DRAMs optimized to read & write entire blocksDRAMs optimized to read & write entire blocks

or at least a few consecutive locationsor at least a few consecutive locations

Several different modesSeveral different modes normal/basic modenormal/basic mode Nibble or Burst ModeNibble or Burst Mode Fast Page ModeFast Page Mode Extended Data Out (EDO) ModeExtended Data Out (EDO) Mode

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Basic Mode of OperationBasic Mode of Operation

Slowest modeSlowest mode Uses only single row and column addressUses only single row and column address Row access is slow (60-70ns) compared to column access (5-10ns)Row access is slow (60-70ns) compared to column access (5-10ns) Leads to three techniques for DRAM speed improvementLeads to three techniques for DRAM speed improvement

Getting more bits outGetting more bits out of DRAM on one access given timing of DRAM on one access given timing constraintsconstraints

PipeliningPipelining the various operations to minimize total time the various operations to minimize total time Segmenting the dataSegmenting the data in such a way that some operations are in such a way that some operations are

eliminated for a given set of accesseseliminated for a given set of accesses16

Row ColumnAddress

RAS

CAS

DataData

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Nibble (or Burst) ModeNibble (or Burst) Mode

Several consecutive columns are accessedSeveral consecutive columns are accessed Only first column address is explicitly specifiedOnly first column address is explicitly specified Rest are internally generated using a counterRest are internally generated using a counter

RAS ---- ---- ---- ---- ---- ---- ---- ---- ----CAS CAS CAS CAS

RA CAD1 D2 D3 D4

RAS ---- ---- ---- ---- ---- ---- ---- ---- ----CAS CAS CAS CAS

RA CAD1 D2 D3 D4

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Fast Page ModeFast Page Mode

Accesses arbitrary columns within same rowAccesses arbitrary columns within same row Static column mode is similarStatic column mode is similar

RAS ---- ---- ---- ---- ---- ---- ---- ---- ----CAS CAS CAS CAS

RA CA1 CA2 CA3 CA4D1 D2 D3 D4

RAS ---- ---- ---- ---- ---- ---- ---- ---- ----CAS CAS CAS CAS

RA CA1 CA2 CA3 CA4D1 D2 D3 D4

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EDO ModeEDO Mode

Arbitrary column addressesArbitrary column addresses PipelinedPipelined EDO = Extended Data OutEDO = Extended Data Out Has other modes like Has other modes like ““burst EDOburst EDO””, which allows , which allows

reading of a fixed number of bytes starting with each reading of a fixed number of bytes starting with each specified column addressspecified column address

RAS ---- ---- ---- ---- ---- ---- ---- ---- ----CAS CAS CAS CAS CAS CAS CAS

RA CA1 CA2 CA3 CA4 CA5 CA6 CA7D1 D2 D3 D4 D5 D6

RAS ---- ---- ---- ---- ---- ---- ---- ---- ----CAS CAS CAS CAS CAS CAS CAS

RA CA1 CA2 CA3 CA4 CA5 CA6 CA7D1 D2 D3 D4 D5 D6

DDR DRAMDDR DRAM Double Data Rate (DDR) SDRAMDouble Data Rate (DDR) SDRAM

Transfers data on both edges of the clockTransfers data on both edges of the clock Currently popularCurrently popular You get two memory accesses per clock cycle!You get two memory accesses per clock cycle!

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RAMBUS DRAM (RDRAM)RAMBUS DRAM (RDRAM) Another attempt to alleviate pinout limitsAnother attempt to alleviate pinout limits Many (16-32) banks per chipMany (16-32) banks per chip Made to be read/written in packetsMade to be read/written in packets Up to 1200MHz bus speedsUp to 1200MHz bus speeds

XDR – 8 bits per clock, 16-bit wide bus, 6.4GBXDR – 8 bits per clock, 16-bit wide bus, 6.4GB But DDR doing very well alsoBut DDR doing very well also

Quite expensiveQuite expensive almost disappeared from consumer PCsalmost disappeared from consumer PCs still present in servers and specialized chipsstill present in servers and specialized chips

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DRAM ControllersDRAM Controllers Very common to have a separate chip/module Very common to have a separate chip/module

that controls memorythat controls memory Handles banksHandles banks Handles refreshHandles refresh

Multiplexes column and row addressesMultiplexes column and row addresses RAS and CAS timingRAS and CAS timing

Called “Northbridge” on PC chip setCalled “Northbridge” on PC chip set

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ConclusionsConclusions RAMs with different characteristicsRAMs with different characteristics

For different purposesFor different purposes

Static RAMStatic RAM Simple to use, small, expensiveSimple to use, small, expensive Fast, used for cacheFast, used for cache

Dynamic RAMDynamic RAM Complex to interface, largest, cheapComplex to interface, largest, cheap Needs periodic refreshNeeds periodic refresh

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LinksLinks Ram Guides (not very technical)Ram Guides (not very technical)

http://arstechnica.com/paedia/storage.html

Your Nexys 3 board manualYour Nexys 3 board manual

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