Common Public Radio Interface - IEEE...
Transcript of Common Public Radio Interface - IEEE...
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Common Public Radio Interface
CPRI overview Input requirements for CPRI
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Some history
• Industrial cooperation jointly created by 5 parties: – Ericsson, – Huawei, – NEC, – Nortel Networks, – Siemens Mobile
• Provide a framework to facilitate Radio Equipment products development for mobile telecommunications systems
• CPRI specification V1.0 published in 2003
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CPRI Basic System Architecture
• Based on a Radio Base Station architecture dividing the Radio Base Station into a radio part and a control part
• CPRI specification defines the Radio Base Station internal interface between these two parts
• Simple • Flexible
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CPRI Basic System Architecture
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Radio Equipment (RE) Radio Equipment Control (REC)
Layer 1
Layer 2
Control & Mgmt
User Plane Sync
SAP CM
Air Interface Network Interface
Common Public Radio Interface
Layer 1
Layer 2
Control & Mgmt
User Plane Sync
Radio Base Station System
CPRI link
SAP S SAP IQ SAP CM SAP S SAP IQ
Master port Slave port
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CPRI Protocol Stack
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Time Division Multiplexing
User PlaneControl &
ManagementPlane
ElectricalTransmission
OpticalTransmission
IQData
Ethernet
HD
LC
L1 Inband Protocol
Vendor Specific
Layer 1
Layer 2
SYNC
Well defined in CPRI • UMTS ; CPRI V1 and V2 • Wimax ; CPRI V3 • LTE; CPRI V4 •GSM; CPRI V5
Fully specified in CPRI
Informative only, except clock rate
Level of specification
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CPRI Main Characteristics
• Bit synchronous interface • Symmetrical serial data link between REC and RE • Steady data stream, ”Always one” • Time Division Multiplexing (TDM) of Antenna
data streams in form of In-phase (I) and Quadrature (Q) Samples
• Embedded Ethernet or HDLC streams (C&M plane data)
• BER=10-12
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CPRI Frame Structure
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CPRI Basic Frame
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B=0: AB=1: B… C
DEFGHABCDEFGHA
BYT
E #Z
.X.0
BYT
E #
Z.X.
1
timeY = 0
Y = 1
B=(T-1) : H BYT
E #Z
.X.(T
/8-1
)ABCDEFG
Y = (T/8-1)
IQData block
1Control Word 15 * T bits
1 chip = 1/3.84MHz
W = 1 2 3 4 5 6 7 8 9 10 11 12 13 14 150
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CPRI Control Word usage
• 1/16 of the available CPRI bandwidth – Synchronization and Timing – Fast and/or Slow C&M channel – Low level link control (LOS/LOF/…) – Vendor Specific – Fast Real Time Control
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CPRI Transport Capacity allocation
• « static » allocation of the IQ data block resource
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CPRI Line Bit Rate Options and User-Plane Transport Capacity
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Line bit rate Line Coding Transport Capacity (#WCDMA AxC)
Transport Capacity (# 20 MHz LTE AxC)
614.4 Mbit/s 8B/10B 4 -- 1228.8 Mbit/s 8B/10B 8 1 2457.6 Mbit/s 8B/10B 16 2 3072.0 Mbit/s 8B/10B 20 2 4915.2 Mbit/s 8B/10B 32 4 6144.0 Mbit/s 8B/10B 40 5 8110.08 Mbit/s 64B/66B 64 8 9830.4 Mbit/s 8B/10B 64 8 10137.6 Mbit/s 64B/66B 80 10 12165.12 Mbit/s 64B/66B 96 12
Each 20MHz LTE AxC stream requires ~1Gbps!
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C&M-Plane Transport
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Line bit rate Maximum Slow C&M Bitrate [Mbit/s]
Maximum Fast C&M Bitrate [Mbit/s]
614.4 Mbit/s 0.48 21.12 1228.8 Mbit/s 0.96 42.24 2457.6 Mbit/s 1.92 84.48 3072.0 Mbit/s 2.4 105.6 4915.2 Mbit/s 3.84 168.96 6144.0 Mbit/s 4.8 211.2 >=8110.08 Mbit/s 7.68 337.92
CPRI Slow C&M channel transported in CW of second CPRI basic frame of each Hyperframe
CPRI fast C&M channel transported in CWs of Basic frame with number p, p+1,..,63,64+p…127, 128+p…191, p+192,…,255 (p-pointer configurable from 16 … 63)
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Synchronization and Timing
• Slave port side recovers the clock signal from the incoming serial bit stream (slave port “locked” to master port clock).
• Sync Control Word marks the start of a Hyperframe • Time information (BFN, HFN) is obtained from
specific control words • Cable Delay calibration process delivers one-way
delay values (T12 and T34 respectively) (assumes symmetrical cable delay values)
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CPRI Delays
• Single hop configuration
• Multi hop configuration
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REC RE
T12R1 R2
R4 R3T34
Toffset
T2a
Ta3
Ra
T14
REC Toffset
T12(1)R1
R4 T34(1)
T14(1)
T12(2)
T34(2)
RE
R2
R3
T2a
Ta3
Ra
mas
ter p
ort
slav
e po
rt
networkingREToffset(1)
RB2
RB3
RB1
RB4
TBdelayDL(1)
mas
ter p
ort
slav
e po
rt
TBdelayUL(1)
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CPRI documents
• CPRI specification – section 4 : defines mandatory and optional parts
of the CPRI specification – Annex A: Specification details
• Informative and normative sections – Scrambling (Normative) – 64B/66B line coding (Normative) – Delay Calibration Example (Informative) – Electrical Physical Layer Specification (Informative) – Networking (Informative) – E-UTRA /GSM sampling rates (Informative)
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CPRI documents
• CPRI specification – Annex B: Input Requirements for the CPRI
Specification (Informative) – Used for the development of the CPRI
specification – Requirements to be met by the CPRI
specification and used as a baseline for future enhancements of the CPRI specification
– Does not specify the requirements on a CPRI compliant device
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CPRI documents
• Protocol Implementation Conformance Statement (PICS) – Lists of CPRI capabilities and options implemented – Interoperability – Implementation, test and verification
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Relation between “input requirements” and “interface specification”
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Section 7. Annex B Input Requirements
for CPRI specification (Informative)
Section 4. Interface
Specification
Radio standards e.g. 3GPP
System design constraints
(circuit switched assumption)
CPRI Specification v6.1
PICS
CPRI compliant module(s)
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Input Requirements for CPRI
• Timing and Synchronization relevant excerpt: – Max. Frequency Error contribution: 0.002ppm – Max. Bit Error Ratio: 10-12
– Link delay accuracy: ±TC/32 – Max. round trip delay (excl. cable): 5µs
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Input Requirements for CPRI
• R-17, R-18, R-18A: Frequency Synchronization – Requirement were written to provide a clean clock
reference for the RE, the total frequency error budget being 50 ppb for RNC -> BASE Station -> Radio Equipment.
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Input Requirements for CPRI
• R-19, R-20 R-21, R-21A: Delay accuracy – These requirements are driven by 3GPP
specifications
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Feature Timing accuracy Source
UTRA-FDD Tx Diversity UTRA-FDD MIMO
+/- 32.5 ns 3GPP TS 25.104
E-UTRA TDD +/- 1.5us 3GPP TS 36.133
E-UTRA Tx Diversity E-UTRA MIMO
+/- 32.5 ns 3GPP TS 36.104
E-UTRA Intra-band contiguous Carrier Aggregation
+/- 65 ns 3GPP TS 36.104
UTRA RTT +/- 130 ns 3GPP TS 25.133
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Input Requirements for CPRI
• R-26: Maximum Delay – In order to have maximum signal processing time,
the transport latency of the antenna data shall be minimized
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Input Requirements for CPRI
• R-27: Bit Error Ratio – This requirement is to define signal quality
transport, the reason is to avoid FEC for this rate to minimize delay and cost
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Thank You
Time for questions
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