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Command, Control and Interfacing to a Massively Parallel...
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Command, Control and Interfacing to a Massively Parallel Biologically Inspired Computer System ⋆ James Cameron Patterson APT group, School of Computer Science The University of Manchester, Manchester, U.K. [email protected] Advisor: Dr. Aphrodite Galata. Supervisors: Prof. Steve Furber and Dr. Jim Garside. Abstract. This paper describes the progress made during 2nd year of a PhD programme at the University of Manchester, and details future planned work in order to submit a thesis for examination at the end of the 3rd year. 1 Introduction and Research Aims SpiNNaker is a Application Specific Integrated Circuit (ASIC) (fig.1) designed with the goal of efficiently modelling massively parallel artificial neural networks in real time [2]. Multiple SpiNNaker chips may be attached to one another to scale the neural network (fig.2), and a fully configured system supports up to 65,536 chips. As SpiNNaker chip cores are general purpose ARM processors they are easily programmable to support multiple neuronal and synaptic models. Central to the performance of such a multi-chip machine is the interconnection of the system. The research comprising this PhD considers two key aspects of this connectivity: – Management - to monitor and control the system in real-time detecting where connectivity and processing ‘hot-spots’ occur. – Input/Output - to permit scalable interaction in real-time via sensors and actuators. 2 Research Contributions to Date 2.1 1st Year Summary Research was performed into the utilisation of SNMP (Simple Network Manage- ment Protocol) and MIB (Management Information Base) in large-scale network- attached computer systems, and to imaging of neural networks (predominantly of the brain, in-vivo). ⋆ This report has been produced for the 2nd year interview as part of the PhD pro- gramme. (14:45 on 25/Aug/2010, with Prof. Mendes and Dr. Fernandes)
Transcript of Command, Control and Interfacing to a Massively Parallel...
Command, Control and Interfacing to a
Massively Parallel Biologically Inspired
Computer System⋆
James Cameron Patterson
APT group, School of Computer ScienceThe University of Manchester, Manchester, U.K.
Advisor: Dr. Aphrodite Galata. Supervisors: Prof. Steve Furber and Dr. Jim Garside.
Abstract. This paper describes the progress made during 2nd year ofa PhD programme at the University of Manchester, and details futureplanned work in order to submit a thesis for examination at the end ofthe 3rd year.
1 Introduction and Research Aims
SpiNNaker is a Application Specific Integrated Circuit (ASIC) (fig.1) designedwith the goal of efficiently modelling massively parallel artificial neural networksin real time [2]. Multiple SpiNNaker chips may be attached to one another toscale the neural network (fig.2), and a fully configured system supports up to65,536 chips. As SpiNNaker chip cores are general purpose ARM processors theyare easily programmable to support multiple neuronal and synaptic models.Central to the performance of such a multi-chip machine is the interconnectionof the system. The research comprising this PhD considers two key aspects ofthis connectivity:
– Management - to monitor and control the system in real-time detectingwhere connectivity and processing ‘hot-spots’ occur.
– Input/Output - to permit scalable interaction in real-time via sensors andactuators.
2 Research Contributions to Date
2.1 1st Year Summary
Research was performed into the utilisation of SNMP (Simple Network Manage-ment Protocol) and MIB (Management Information Base) in large-scale network-attached computer systems, and to imaging of neural networks (predominantlyof the brain, in-vivo).
⋆ This report has been produced for the 2nd year interview as part of the PhD pro-gramme. (14:45 on 25/Aug/2010, with Prof. Mendes and Dr. Fernandes)
2 Cameron Patterson, 2nd year report
(a) Simplified schematic diagram ofthe SpiNNaker architecture.
(b) Physical die layout of the SpiN-Naker test chip.
Fig. 1. Schematic and plot of the SpiNNaker two core test chip.
More detail of this 1st year research can be found in its long report1, and thiswork should be applicable for inclusion into the final thesis as background re-search. Contributions were also made to development of the SpiNNaker testchip, with a novel communications packet format, testing and validation includ-ing identification of chip bugs before fabrication.
Fig. 2. Multi-chip SpiNNaker system, shown connected as a torus. A SpiNNaker ma-chine may scale up to 65,536 chips.
1 http://intranet.cs.man.ac.uk/apt/people/cpatterson/1styearlong.pdf
Cameron Patterson, 2nd year report 3
2.2 2nd Year Summary
BootROM work. Research was performed to determine the root-cause of test-chip BootROM failures, prompting a role of researching the redesign of theSpiNNaker2 BootROM, including leading the strategy and design reviews forthis component. Implementation, testing and validation of the new BootROMhas been carried out using the test chip and transistor level model of the SpiN-Naker2 design, including test environment optimisation (fig.3).During this work a critical data-transfer fault was identified early, helping di-agnose the root-cause and feeding back to the technology partner ensuring itdid not impact the chip production critical-path. In addition requirements wereproduced for the management functionality of the SpiNNaker2 chip.
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Fig. 3. Graph detailing TLM simulation times, optimisation (500 to 2hrs) was achievedby using only a relevant subset of cores (3) and TCM test sizes (16+16 Bytes).
Other Research. Led the team getting the first Neural application running onSpiNNaker, an important milestone for the project. The video2 demonstratingthis neural network was cited by a New Scientist article on SpiNNaker [4].Participated in the Telluride Neuromorphic Cognition Engineering Workshop3
interfacing real sensors and actuators with SpiNNaker into a closed-loop system.The SpiNNaker neural network was fed from a spiking artifical retina, and drovespiking outputs to control the motors of a robot (fig.4) - with successful resultsin tasks of taking direction from gestures4 and line-following5.
2 http://www.youtube.com/watch?v=PcS8oxVQkEs3 https://neuromorphs.net/nm/wiki/2010/rob10/SpiNNaker (self-signed site)4 http://www.youtube.com/watch?v=kOXbakin3kI5 http://www.youtube.com/watch?v=ZQ7FdQ_VJNg
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(a) Architecture of the closed-loop SpiNNakersystem. Solid lines represent native spike paths.
(b) View of the robot / retinaon a plain background line.
Fig. 4. Schematic and photograph of the Telluride robot with mounted artificial retina
2.3 Publications
To date there are three submitted and accepted papers with myself as an author:21st Async Forum [5], IJCNN 2010 [3] and ACM Computer Frontiers 2010 [6].An additional paper is also currently under consideration for ICONIP 2010 [1].Further publication submissions are expected as detailed in the Future Planssection below, as well as collaboratively with the SpiNNaker team.
3 Future Plans
The following sections summarise planned work until completion of year 3 ofthe PhD programme. A GANNT chart has been provided (fig.5) that should beconsulted together with this explanation.
3.1 End of 2nd year - after interview
– Finish the BootROM, and validation work thereof for the SpiNNaker2 chip.– Begin structuring of the MIB for the SNMP management platform.– Write and submit the ‘Low cost implementation of Internet Protocol, in
embedded systems’ paper.
3.2 3rd Year plans
– To complete the SNMP/MIB implementation and perform experiments todetermine its functionality and usefulness.
- Write up the ‘Protocol Translation between SpiNNaker and SNMP/MIBsystems’ paper, and draft the thesis chapter.
– To use the SNMP/MIB framework to create a functional imaging platformfor SpiNNaker, experimenting across a range of differently sized neural net-work simulations.
Cameron Patterson, 2nd year report 5
- Write the paper ‘Real-Time Functional Imaging of SpiNNaker’, and draftthe thesis chapter.
– To complete an FPGA implementation interfacing with a SpiNNaker chipon what is notionally an inter-chip link - and experiment to determine per-formance characteristics and comparisons with the Ethernet connection.
- To then create a paper ‘Interfacing to SpiNNaker (via FPGA and Eth-ernet)’ on this topic.
– Write up the remaining areas in the thesis, revise all existing documentation,take in feedback, and submit.
4 Planned Structure of Thesis
Chapter 1 – Introduction. Details what problems are being set out to besolved, including management, imaging and interfacing sections.
Chapter 2 – Background Research. A literature review into relevant exist-ing work, solutions and problems close to the research areas. PhD foundation.
Chapter 3 – Research Aims and Contribution. A chapter setting out themain topics of research in the PhD, detailing the approach taken, and statingthe goals for contributions to the research area.
Chapter 4 – Command and Control of the massively scalable SpiN-
Naker machine. The low cost management protocol translation implementa-tion, results from the experiments using SNMP/MIB as a bedrock for manage-ment of this type of machine, and its scalability.
Chapter 5 – Functional Imaging. A real-time view of the neural network,zooming in and out providing visibility of functional areas, and down to singleneuron monitoring. May be subsumed into a management chapter with Chapter4 above, if found to not justify its own chapter.
Chapter 6 – Interfacing to SpiNNaker. Covering research work from theBootROM, such as the low Cost IP Implementation, as well as separate workusing a FPGA in connecting sensors and actuators to the SpiNNaker machine.Comparisons with the performance achievable using the Ethernet, impact onsimulations of factors such as jitter (eg. remote sensors over long distance).
Chapter 7 – Conclusions and Future Research. What conclusions canbe drawn from the research within this PhD, what specific contributions has itmade, and which future avenues of research does it provoke.
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References
1. S. Davies, C. Patterson, F. Galluppi, A. Rast, D. Lester, and S. Furber. InterfacingReal-Time Spiking I/O with the SpiNNaker neuromimetic architecture. Submittedto ICONIP 2010 - 17th International Conference on Neural Information Processing.
2. X. Jin, S. B. Furber, and J. V. Woods. Efficient modelling of spiking neural net-works on a scalable chip multiprocessor. Neural Networks, 2008. IJCNN 2008.(IEEE World Congress on Computational Intelligence). IEEE International JointConference on, pages 2812–2819, September 2008.
3. Xin Jin, Francesco Galluppi, Cameron Patterson, Alexander Rast, Sergio Davies,and Steve Furber. Algorithm and Software for Simulation of Spiking Neural Net-works on the Multi-Chip SpiNNaker System. In 2010 International Joint Conferenceon Neural Networks (IJCNN 2010), pages 649–656, September 2010.
4. Paul Marks. Army of smartphone chips could emulate the human brain. New Scien-tist, 2758:18–19, May 2010. http://www.newscientist.com/article/mg20627585.700-army-of-smartphone-chips-could-emulate-the-human-brain.html?DCMP=OTC-rss—&nsref=online-news.
5. Cameron Patterson. Command and Control of a Massively Parallel GALS Environ-ment. In Proceedings of the 21st UK Asynchronous Forum, pages 23–26, 2009.
6. Alexander D. Rast, Xin Jin, Francesco Galluppi, Luis A. Plana, Cameron Patterson,and Steve Furber. Scalable event-driven native parallel processing: the SpiNNakerneuromimetic system. In CF ’10: Proceedings of the 7th ACM international confer-ence on Computing frontiers, pages 21–30, New York, NY, USA, 2010. ACM.
An electronic version of this report with functional hyperlinks may be found at:http://intranet.cs.man.ac.uk/apt/people/cpatterson/2ndyearshort.pdf
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