CMS Annual Review September 2004Geoff Hall1 Tracker Off-detector Electronics On-detector electronics...

CMS Annual Review September 2004 Geoff Hall1

Tracker Off-detector Electronics

On-detector electronics production approaching completion procuring spares

Off-detector electronics FED & FEC development complete

substantial software development Power supplies

prototyping of cavern version successful tender action complete

ESRs completed final one: Off-detector electronics November 2003

Grounding and shielding Fine tuning of systems already demonstrated in lab and beam tests


FEDv1 -first prototype•9U VME64x

•PCB 14 layers (incl 6 power & ground)

•~ 6 K components (smallest 0402) ; ~ 25 K tracks

•BGAs largest 676 pins @ 1 mm pitch

•96 ADC channels :AD9218 Dual package 10 bit @ 40 MHzHalf Analogue circuitry on Secondary Side

JTAG Boundary Scan

6 FEDv1 boards delivered to CERN

for Large Scale Assembly centres

(4 used in 25 nsec test beam June 2004)

5 FEDv1 boards kept in UK for Design Tests


FEDv1 Manufacture History Sep 2003

5 FEDv1 boards under test. (PCB and Assembly by separate small companies)

All boards working well. Only manufacturing minor faults.

Oct 2003

Further 6 FEDv1 made. (same manufacturers)

Major problems on all boards. Shorts under many BGAs.

Rework of BGAs attempted. After initial success on 2 boards failed on next 4.

Problem believed due to uncured solder resist ink leeching from vias of bare PCBs.

Precise diagnosis difficult, plus change of metal finish (Ni/Gold -> Immersion Tin).

Nov 2003 - Jan 2004

Identified candidate medium size companies suitable for 500 production boards.

Providing combined PCB and Assembly with guarantees.

Offer advanced Quality Controls, Auto Optical Inspection, X-ray (in house), BScan.

Mar 2004

Manufactured 6 FEDv1 with one identified company. Very professional production.

No BGA problems. All boards working well.


FEDv1 Design Testing

Objectives Validate final design done large scale assembly acceptance tests under way

Hardware few issues studied and resolved during testingVerified @ 100 kHz L1 S-LINK readout @ 80 MHz. TTC and TCS Interfaces verified

Analogue performance excellent. Optical inputs using FED Opto-Tester board.

To optimise OptoRx (1% settling in 15ns) some FE component values need final tuning.

Power/temp requirements finalised. Standard LHC crates satisfactory.

Firmware complete and working for assembly test useUsed in 25 nsec Test Beams June 2004.

Few minor issues (as expected!) under investigation.

Software fully integrated in CMS Tracker DAQ framework.Test bench Framework for essential Assembly Plant Testing nearly ready


FEDv2 pre-Production Board Aim to be final production version - minimal changes from v1

Power Block : General improvements.

QDR Memory : Replacement part (pin compatible) identified.

FE FPGA : Use larger 2M gate (pin compatible) part.

ADC : AD9218 Device bug. Reduce gain by half. Simple mod.

FPGA Configuration : VME Boot device reprogram via JTAG cable.

S-LINK & TCS Signals : New 6U VME Transition Card.

FE Analogue : Tune few components for optimal matching to Optical Link

StatusFirst 2 boards received in August. Tests proceeding well.Boundary Scan passed. VME crate tests in progress

Plan to make a further ~20 before end of 2004 for Full Crate tests.


Testing at Assembly Plant

1. Custom Tests atAssembly Plant

BScan, VME crate

3. Tests at CERNPrevessin

Readout Integration

2. Tests at RAL &IC

OptoRx, Full crate

4. Installation at CMSUSC55

0. Quality Controlsduring Assembly

processAOI, X-ray Boundary Scan Testing for Digital

Testing by Assembly plant operatives

0. Assembly ProcessQuality Checks

E.g. AOI

2. Fit FrontPanelDeflector Bar

Jumpers

1. VisualInspection

Multimeter tests

3. Serial NrFit FP label & 2D

Bar code

4. Insert in CrateCheck for

mechanics

5. Power On CrateVerify LEDs

6. Boundary ScanSave results

7.Program EPROM(change Jumper)

8.Power Reset

buttonVerify LEDs

10.Test Serial EPROM

Load with Ser Nr, Date etcJumper for Write Protect

9.Test VME Access

11.Test FPGA loadingInsert CFlash Card

Power ResetVerify LEDs for Load Done

Flashing Clocks

12.Run Test Bench Programs:Exercise FPGA Registers

Read TemperaturesRead Voltages

Scan DACs and OptoRx settings capture data

13.Final Tests

Box up

Results of Operator Checks andProgrammable Tests should go to

Dbase

For details of tests and checksand acceptance criteria see

detailed diagrams

VME Crate Testing for Analogue

Test Flow from Assembly Plant to USC55

500 boards to test over 10 months. Essential to catch any manufacturing faults early.


FED Schedule (v 1.6 March 2004)

Production Plans

Q1/2004 : Complete tests of FEDv1 design. Done.

Finalise design changes for FEDv2. Done.

Sign off against FED User Requirements Document. Done.

Q2/2004 : Implement changes for FEDv2 and review. Done.

Q3/2004 : Manufacture couple of FEDv2s. Done.

Q4/2004 : Test FEDv2. In progress.

Manufacture further 20 FEDv2s. All parts in hand except QDR memories on order.

Q2/2005 -> Q2/2006 : Manufacture 500 FEDs @ ~ 50 / month. Fully test batches in UK. Ship to CERN in batches of 50. Re-test at CERN/Prevessin prior to CMS installation.

EU Tender Procedure for PCB/Assembly

Q1/2004 : Place OJEC advert, invite Expressions of Interest. Done.

Q3/2004 : Dispatch calls for Quotes. Identify 2-3 companies. In progress.

Q4/2004 : Select company. Detailed negotiations re Testing, delivery schedules…etc

Q1/2005 : Award contract.

Expect to tune this schedule in response to availability of B904 and USC55


VME FEC Support for 1~8 control

rings per board.

VME 9U board.

VME64x compatible.

Control information passes through the VME bus.

Fast Timing Signals passes through the TTC link.

VMEinterface

FPGA

mFEC

mFEC

mFEC

mFEC

mFEC

mFEC

mFEC

mFEC

TTCrx

QPLL

Local Bus

Fast

Tim

ing

sig

nals

JTA

G

ECAL TTC/TTS bus

VMEbus

TTC link

TriggerFPGA

See also Kostas KloukinasECAL AR for all details

Now use for TK + ECAL, pixels, Preshower


VME FEC 1st Prototype

VME backplane

TTC/TTS bus

mFECs

TTC input

VME Interface FPGA

Trigger FPGA

6 Layer board

Final version and already in use


FEC Production

Tracker: 352 control rings: 44 VME FEC boards + spares total with ECAL, etc 112 VME boards + 950 mFECs

First VME PCB prototype: work, but manufacturing issue excessive bending after thermal cycle (solder components)

VME FEC Pre-Production PCBs at CERN this week. adjusted stacking of the FR4 layers

mFEC Pre-Production Run (50 off) Available late September.

Final Production (PCB fabrication + assembly + testing) mFECs Jan. 2005 - Jun. 2005 FEC boards Jan. 2005 - Jun. 2005


Power supplies

Two prototypes produced Cavern and counting room variants Performance looks excellent B-field tests done Radiation tests done

Lab tests show good performance noise isolation hardware protection and current limiting overvoltage protection efficiency 70-85% (load dependent) used in beam tests with long cables giving excellent results


Modules

Variants very similar - one allows cavern operation Sufficiently B-field and radiation tolerant Recent improvements in transformers optimise size


Tender & Schedule

Tender action complete Technical performance of two variants essentially identical Cavern Supply had required magnetic field and radiation tolerance Cost saved by PS in the Cavern was between 1.5 - 3.0 MCHF.. Cavern solution adopted June 2004 INFN adjudication committee accept CAEN offer

Production - if order placed before October 2004 Begin Q4 2004 Ramp to ~65 /month Complete deliveries in Q1 2006


Delivery Schedule

Delivery of CMS LV Power Supplies

0

500

1000

1500

2000

2500

A M J J A S O N D J F M A M J J A S O N D J F M

Red = SST + pixels

200620052004


Commissioning

Separate detector support activities from commissioning Stable DAQ and hardware needed for large scale assembly

Prevessin 904 for pre-commissioning phase USC55/UXC for final phase

NB TK DAQ essentially ready and working (XDAQ) Adapt plans to availability of space and plant Eg FEDs

1) Quality control in company during assembly

2) Tests at assembly plant (JTAG, Self Test)

Crate and software provided by IC-RAL, tests all functionality except ORx’s

3) Final acceptance of boards at Imperial and RAL

optical tests, and soak test

4) Test at CERN 904 with FEC, TTC, trigger etc

should verify previous results prior to move to cavern

• Installation in system at CERN


Conclusions

No showstoppers in sight Well advanced with hardware, pre-production, evaluation and

integration, including software Production plans almost complete

Main issues Quality of production (and associated cost & effort) Adapting commissioning plans to requirements

CMS Annual Review September 2004

Geoff Hall 17

Spare slides


FED Overview

VME-FPGA

TTCrx

BE-FPGAEvent Builder

Buffers

FPGAConfiguration

Compact Flash

PowerDC-DC

DAQInterface

12

12

12

12

12

12

12

12

Front-End Modules x 8Double-sided board

CERNOpto-

Rx Analogue/Digital

96 TrackerOpto Fibres

VMEInterface

XilinxVirtex-IIFPGA

Modularity

9U VME64x Form Factor

Modularity matches Opto Links

25,000 Si strips / FED

440 FEDs in Total.

8 x Front-End “modules”

OptoRx/Digitisation/Cluster Finding

Back-End module / Event Builder

VME module / Configuration

Power module

Other Interfaces:

TTC : Clk / L1 / BX

DAQ : Fast Readout Link

TCS : Busy & Throttle

VME : Control & Monitoring

JTAG : Test & Configuration

FE-FPGAClusterFinder

TTC

TCS

TempMonitor

JTAG

TCS : Trigger Control System

9U VME64x

Input ~ 3 GBytes/sec

after Zero Suppression : Output: ~ 200 MBytes/sec

19 Geoff HallCMS Annual Review September 2004

Firmware and FPGAs

Delay x 24 FE x 8

BE x 1

VME x 1

Delay FPGA: ADC Coarse and Fine Clock Skewing.

FE FPGA: Scope and Frame Finding modes.

BE FPGA: Event building, buffering and formatting.

VME FPGA: Controls and Slow Readout path.

Baseline of 4 FPGA Final Designs working...

34 Xilinx Virtex II FPGAsup to 2M equiv gates each


S-LINK VME Transition Card Simple 6U board:

Provides interface between FED and Slink Transmitter

Provides access to FED Throttle signals

DAQ Slink Transmitter

Slink Transition

Card

Ethernet Connector

FED Slink Data & Control Signals

FED Throttle Signals

VME Backplane

6U

3 Transition Cards in manufacture by end July. Now back for test in September.(compatible with both FEDv1 and FEDv2)

CMS Annual Review September 2004Geoff Hall1 Tracker Off-detector Electronics On-detector electronics...

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