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[12] R. Degraeve, G. Groeseneken, R. Bellens, J. L. Ogier, M. Depas, H. J.Roussel, and H. E. Maes, “New insights in the relation between electrontrap generation and the statistical properties of oxide breakdown,”IEEETrans. Electron Devices, vol. 45, pp. 904–911, Apr. 1998.

[13] D. J. DiMaria and J. H. Stathis, “Explanation for the oxide thicknessdependence of breakdown characteristics of metal-oxide-semiconductorstructures,”Appl. Phys. Lett., vol. 70, pp. 2708–2710, 1997.

CMOS Compatible HV Gate-Shifted LDD-NMOS

P. M. Santos, A. P. Casimiro, M. Lança, and M. I. Castro Simas

Abstract—This brief presents an improvement of lightly doped drain(LDD) FET based on a drain engineering technique—the gate-shifting.Gate-shifted LDD (GSLDD) devices were fabricated in a submicronCMOS technology with no extra processing steps. Breakdown voltages inthe range of 50 V and specific ON-resistances in the range of 2–4 m cmwere attained.

I. INTRODUCTION

The development of HV devices is usually achieved through rathersophisticated and costly technological processes [1]–[5]. This moti-vated the search for modified device structures compatible with stan-dard CMOS processes, in order to increase by tens of volts the usualBV capability, with specific ON-resistances in the range of a few mil-liohms per square centimeter.

The work reported in this brief deal with experimental characteriza-tion of a CMOS fully compatible device, the gate-shifted lightly dopeddrain (GSLDD) [6].

Comparison analysis with other high-performance devices is alsodiscussed, to prove that this low-cost solution presents interesting fea-tures, when compared with their counterparts.

II. STANDARD CMOS TECHNOLOGY

A standard, 0.7-�m, N-well CMOS technology, with one polysiliconlayer and two metal layers, aimed at low voltage customized circuits,was chosen for this work.

For this technology, gate oxide thickness is 150 Å and the recom-mended maximum value for gate voltage is 12 V. This oxide thicknessis thick enough to allow 10 V at the gate electrode, which correspondsto a field of 6.6 MV/cm, a value below the limit of 7 MV/cm, acceptedfor a reliable performance [7].

III. GATE-SHIFTED LDD-NMOS FET

The cross section of the proposed structure GSLDD NMOS FET ispresented in Fig. 1, whereLGS designates the distance between gatethin oxide and N-well layout masks edges andLGD is the distancebetween drain and gate active areas.

In the gate-shift technique, the edges of N-well and gate masks arekept apart byLGS, the continuity of the current path being ensured bythe N-well lateral diffusion (Fig. 1). The concentration of the lateral

Manuscript received June 29, 2000; revised November 20, 2000. The reviewof this brief was arranged by Editor R. Singh.

The authors are with the Instituto de Telecomunicações-Instituto SuperiorTécnico, Technical University of Lisbon, 1049-001 Lisboa, Portugal.

Publisher Item Identifier S 0018-9383(01)03260-9.

Fig. 1. Cross section of the proposed HV GSLDD structure.

(a) (b)

Fig. 2. Simulated electric field contours (V/cm) for devices with differentL

lengths: (a) 0.1�m and (b) 0.8�m (V = 30 V andV = 0).

diffusion decreases from a maximum value (N-well surface concen-tration), toward the substrate concentration, at the N-well/P-substratejunction. The classical LDD structure (LGS = 0�m) has the gate edgelocated over the N-well maximum concentration. On the other hand, inthe GSLDD, the gate edge is located over a less concentrated region.At off state, both LDD and GSLDD have the electric field peak locatedbeneath the gate edge region. However, electric field crowding will bestronger for the less resistive path device (LDD). As drain voltage isincreased, electric field peak will exceed critical value for Si and im-pact ionization rate (electron-hole pair generation) should experiencea huge increase. Thus, a breakdown voltage improvement is expectedfor increasedLGS lengths, due to the electric field peak location in ahigher resistive region (N-well lateral diffusion).

Simulation results at the onset of avalanche breakdown for GSLDDdevices, at off state, with different gate shift lengths confirm that themost stressed area is always located at the silicon surface, in the regionbeneath gate edge. Fig. 2 shows electric field distribution for deviceswith two differentLGS lengths: 0.1�m and 0.8�m, obtained at offstate(VGS = 0 V), with a drain voltageVD = 30 V. As expected, bothstructures present electric field peaks located at silicon surface, beneathgate edge and at the end of bird’s beak. Comparing the electric fielddistribution in these two cases, one can conclude the following for thestructure with longer gate-shift lengthLGS:

1) the stressed region (above2� 105 V/cm) is less extended;

2) the electric field peak is lower at this drain voltage.

Therefore, impact ionization rate is lower for devices with longerLGSlengths. As the drain voltage is increased, the device with longerLGSwill always experience lower impact ionization rates and should reachthe avalanche breakdown phenomenon at higher drain voltages.

IV. EXPERIMENTAL RESULTS AND DISCUSSION

The structures described above were submitted for fabrication intwo different runs. Effective channel lengths were maintained above

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1014 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 5, MAY 2001

TABLE IEXPERIMENTAL DATA FOR THE MOST RELEVANT GSLDD DEVICES

Fig. 3. Dependence of breakdown voltage onL obtained throughexperiment.

2.5�m, which was found to be sufficient to avoid punchthrough break-down, without causing significant leakage current [6]. Table I sum-marizes the most relevant devices layout characteristics and experi-mental results. The maximum breakdown voltage attained through thegate-shift technique was 51 V, corresponding to an improvement of al-most 20 V, when compared with the classical LDD device.

Fig. 3 shows experimental breakdown voltage values encounteredfor devices with differentLGS lengths, together with the classical LDDreference value. The experimental behavior allows two conclusions,previously predicted by simulation:

1) BV increases significantly withLGS in both fabrication runs,with a Gaussian behavior similar to the N-well lateral diffusionsurface profile;

2) the avalanche process, due to electron-hole pair generation byimpact ionization, is highly dependent on the surface concentra-tion in the region beneath the gate edge.

As expected, specific ON-resistance increases with Gate-shifting, ascan be seen in Table I, due to the enlargement of the drift region byLGS.

The high threshold voltage for devices withLGS > 0:8 �m seemsto be a drawback for the proposed technique. However, a multiplefinger GSLDD transistor can compensate this behavior. In fact, as canbe seen in Table I, devices with longer channel widths (26880�m)presentVTH of the order of magnitude of the conventional NMOSdevices fabricated using the same technological process (0.8 V).Although using a larger transistor area, this can still be a feasiblesolution when using a low cost CMOS technology, for applicationsrequiring higher currents.

Fig. 4. Comparison of specific ON-resistance versus breakdown voltage of theproposed GSLDD with previously published results.

V. COMPARATIVE EVALUATION

For an evaluation of the merits of the proposed transistor, in termsof breakdown voltage, specific ON-resistance and cost, characteristicsfor the proposed GSLDD are shown in Fig. 4, along with previously re-ported results obtained with submicron CMOS and BiCMOS technolo-gies [1]–[3]. LDMOS structures resorting to a Smart Power technology[4] are also included. State of the art UMOSFET characteristics, withultralow specific ON-resistance, using very sophisticated technologies[5], are also shown.

According to this comparative study, the GSLDD appears to be themost accessible and less expensive solution to achieve HV devices,with an ON-resistance slightly higher than that of their counterparts,which resort to more sophisticated and costly technologies.

VI. CONCLUSIONS

From the experimental results presented in this paper, the GSLDDshowed to be a very low cost solution with improved blocking capabil-ities, while ensuring a sufficiently low specific ON-resistance, whencompared with devices based on more expensive and sophisticatedtechnologies. These characteristics permit to envisage its applicationin important new areas, including automotive applications, requiringup to 45 V capabilities.

REFERENCES

[1] T. Efland, T. Keller, S. Keller, and J. Rodriguez, “Optimized comple-mentary 40 V power LDMOS-FET’s using existing fabrication steps insubmicron CMOS technology,” inIEDM Tech. Dig., 1994, pp. 399–402.

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 5, MAY 2001 1015

[2] P. Tsui, P. Gilbert, and S. Sun, “A versatile half-micron complementaryBiCMOS technology for microprocessor-based smart power applica-tions,” IEEE Trans. Electron Devices, vol. 42, pp. 564–570, Mar. 1995.

[3] Y. Q. Li, C. A. T. Salama, M. Seufert, P. Schvan, and M. King, “Designand characterization of submicron BiCMOS compatible high-voltageNMOS and PMOS devices,”IEEE Trans. Electron Devices, vol. 44, pp.331–338, Feb. 1997.

[4] A. Marty-Blavier, D. Farenc, T. Sicard, G. Blanc, and I. Pages, “A costeffective smart power technology for 45 V applications,” inProc. ESS-DERC, Stuttgart, Germany, 1997.

[5] T. Syan, P. Venkatraman, and B. Baliga, “Comparison of ultralow spe-cific ON-resistance UMOSFET structures: The ACCUFET, EXTFET,INVFET, and conventional UMOSFET’s,”IEEE Trans. Electron De-vices, vol. 41, pp. 800–808, May 1994.

[6] P. Santos, A. P. Casimiro, M. I. C. Simas, and M. Lança, “Fully CMOScompatible gate-shifted LDD NMOS,” inProc. IEEE-IAS, St. Louis,MO, 1998, pp. 1119–1123.

[7] R. Moazzami and C. Hu, “Projecting gate oxide reliability and opti-mizing reliability screens,”IEEE Trans. Electron Devices, vol. 37, pp.1643–1650, July 1990.

Reliability of Thin Oxides Grown on Deuterium ImplantedSilicon Substrate

D. Misra and R. K. Jarwal

Abstract—We have investigated the reliability of gate oxide with deu-terium incorporated at the Si/SiO interface through low energy ion im-plantation into the silicon substrate before thin gate oxide growth. Deu-terium implantation at a dose of1 10 /cm at 25 keV showed improvedbreakdown characteristics. Charge-to-breakdown seems to correlate wellwith the interface state density measured by conductance method.

I. INTRODUCTION

Interest in incorporation of deuterium at the Si/SiO2 interface forhot-carrier lifetime improvement in CMOS devices has increased inrecent years [1]–[3]. Significant portion of the dangling bonds at theSi/SiO2 interface is satisfied by deuterium. Typically, many hours ofannealing is used for deuterium incorporation [4]. In some cases, high-pressure deuterium annealing is used to reduce annealing time [5]. Re-cently, extended annealing time and temperature at a higher deuteriumconcentration was overcome by deuterium implantation before gateoxide growth [6]. Deuterium implantation is suitable for integrated cir-cuits with multilevel dielectric or metallization layers or where SixNy

is used as a sidewall spacer as SixNy could form a diffusion barrierfor deuterium [7]. The reliability of the gate oxide that is grown on adeuterium implanted silicon substrate must be determined before thisprocess can be used in integrated circuit processing. This work reportsthe breakdown characteristics of silicon dioxide when deuterium is in-corporated at the Si/SiO2 interface through low energy ion implanta-tion into silicon substrates before thin gate oxide growth. Oxides grownwithout any deuterium implantation were used as control devices.

Manuscript received July 6, 2000; revised November 27, 2000. This workwas supported by New Jersey Center for Optoelectronics and National ScienceFoundation Grant 9732697. The review of this brief was arranged by Editor R.Singh.

The authors are with the Electrical and Computer Engineering Depart-ment, New Jersey Institute of Technology, Newark, NJ 07102 USA (e-mail:dmisra@adm.njit.edu).

Publisher Item Identifier S 0018-9383(01)03261-0.

Fig. 1. PeakD values measured by conductance method at 1 MHz as afunction of gate voltage for various devices.

II. EXPERIMENTAL

Deuterium was implanted at room temperature (300 K) into (100)p-type Si substrates with a resistivity of 1.25–2.0-cm at 15, 25,and 35 keV with a dose of1 � 10

14/cm2 through a 200 Å sacrificialoxide. The sacrificial oxide was used to avoid any irreparable surfacedamage. SRIM simulations for the above energies resulted in peaksat 0.38�m, 0.6�m, and 0.75�m, respectively. After the sacrificialoxide was etched, the gate oxide was grown in dry O2 at 800�C for20 min. The oxide thickness was 40 Å for all the splits. The gate oxidethickness was measured by ellipsometry on 16 sites of each Si waferto obtain an average value. Deuterium implantation did not cause anyapparent thickness variation within a wafer or across the wafers. Someof the wafers were annealed at 850�C for 20 min in N2O ambient.A 3000 Å polycrystalline silicon layer was then deposited at 600�Cand patterned using reactive ion etching to form MOS capacitorswith 50�m diameters. Conductance method at 1 MHz was employedby using a HP 4156B parameter analyzer to estimate interface statedensity (Dit). Charge-to-breakdown measurement was performed bygate injection mode at a constant current of 400 mA/cm2.

III. RESULTS AND DISCUSSION

Fig. 1 shows the peak interface state density values measured by theconductance method.Dit is much smaller for the 25 keV-implantedoxide compared to the nonimplanted oxide. Note thatDit for 15 keV-implanted and annealed devices is higher than that of the unannealed25 keV-implanted devices. The 35 keV-implanted and annealed de-vices have largerDit than the control devices. Annealed 25 keV-im-planted devices show the lowest density of interface states. Implanteddeuterium likely results in formation of Si-D bonding at the interface,which plays an important role in the change of distribution of deuteriumin silicon during oxide growth and subsequent annealing. Once oxideis formed, the thermal energy to break the bond to silicon at the in-terface is higher than bulk silicon [8]. During thermal oxidation, deu-terium diffuses either to the bulk or to the surface. Since the oxidationtemperature (800�C) is identical for all cases, interface passivationthus depends on the implantation conditions, as shown in Fig. 2. Wespeculate that for the 15 keV-implanted devices the increase inDit in-dicates an absence of deuterium at the interface. The thermal budgetused in this work contributed to outdiffusion of deuterium during ox-idation for the 15 keV implanted devices. For the 25 keV-implanteddevices, on the other hand, retention of deuterium was noticed afteroxide growth when investigated by secondary ion mass spectroscopy(SIMS), reported elsewhere [9].

A reduction inDit improves the charge to breakdown characteris-tics of the gate oxide [10]. The charge to breakdown for deuterium-im-

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