Cmos Aoi Design

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Chapter 1Introduction to CMOS Circuit

Design

Jin-Fu LiAdvanced Reliable Systems (ARES) Lab.

Department of Electrical EngineeringNational Central University

Jhongli, Taiwan


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Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 2

Introduction

MOS Transistor Switches

CMOS Logic Circuit and System Representation

Outline


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Binary Counter

Presentstate

Next state

a b A B

0 0 0 1

0 1 1 01 0 1 1

1 1 0 0

A = ab + abB = ab + ab

A

B

a

b

CKCLR

Source: Prof. V. D. Agrawal


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1-bit Multiplier

A

B

C

C=AxB


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Switch: MOSFET MOSFETs are basic electronic devices used

to direct and control logic signals in IC design MOSFET: Metal-Oxide-Semiconductor Field-

Effect Transistor

N-type MOS (NMOS) and P-type MOS (PMOS)

Voltage-controlled switches

A MOSFET has four terminals: gate, source,drain, and substrate (body)

Complementary MOS (CMOS) Using two types of MOSFETs to create logic

networks

NMOS & PMOS


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P-N Junctions

A junction between p-type and n-typesemiconductor forms a diode.

Current flows only in one direction

p-type n-type

anode cathode


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NMOS Transistor

Four terminals: gate, source, drain, body

Gateoxidebody stack looks like a capacitor Gate and body are conductors

SiO2 (oxide) is a very good insulator

Called metaloxidesemiconductor (MOS) capacitor

Even though gate is no longer made of metal

n+

p

GateSource Drain

bulk Si

SiO2

Polysilicon

n+


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NMOS Operations

Body is commonly tied to ground (0 V)

When the gate is at a low voltage:

P-type body is at low voltage Source-body and drain-body diodes are OFF

No current flows, transistor is OFF

n+

p

GateSource Drain

bulk Si

SiO2

Polysilicon

n+D

0

S


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NMOS Operations (Cont.)

When the gate is at a high voltage: Positive charge on gate of MOS capacitor

Negative charge attracted to body

Inverts a channel under gate to n-type

Now current can flow through n-type silicon fromsource through channel to drain, transistor is ON

n+

p

GateSource Drain

bulk Si

SiO2

Polysilicon

n+D

1

S


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PMOS Operations

Similar, but doping and voltages reversed Body tied to high voltage (VDD)

Gate low: transistor ON

Gate high: transistor OFF

Bubble indicates inverted behavior

SiO2

n

GateSource Drain

bulk Si

Polysilicon

p+ p+


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Threshold Voltage

Every MOS transistor has a characterizingparameter called the threshold voltage VT

The specific value of VT

is established duringthe manufacturing process

Threshold voltage of an NMOS and a PMOS

VA=1

Mn On

VA=0

Mn Off

VDD

VA

VTn

0

Logic translation

VA

VGSn

Drain

Mn

Source

Gate-source voltage

Gate

+-

VA=1

Mp Off

VA=0

Mp On

VDD

VA

VDD-|VTp|

0

Logic translation

NMOS PMOS

VA

VGSp

Drain

Mp

Source

Gate-source voltage

Gate

+

-

VDD


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MOS Transistor is Like a Tap

Source: Prof. Banerjee, ECE, UCSB


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MOSFET & FinFET

MOSFET

Bulk FinFET SOI FinFET

G

S(D)

D(S)

G

S(D)

D(S)

G

D(S)S(D)

Buried OxideOxide

Si-SubstrateSi-Substrate

Si-Substrate


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According to the gate structure, FinFET canbe classified as Independent-Gate (IG) FinFET

Short-Gate (SG) FinFET


IG & SG FinFETs

IG FinFET SG FinFET

G

S(D)

D(S)

Oxide

Si-Substrate

GS(D)

D(S)

Oxide

Si-Substrate

G


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MOS Switches

NMOS symbol and characteristics

PMOS symbol and characteristics

5v

0v

0v5v

0v

5v

0v

5v-Vth

Vth

Vth

Vth

5v


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CMOS Switch

A complementary CMOS switch Transmission gate

C

5v

a

s

b a

s

b a

s

b

-s -s

0v

5v

0v

0v

5v

Symbols

Characteristics


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CMOS Logic-Inverter

The NOT or INVERT function is oftenconsidered the simplest Boolean operation F(x)=NOT(x)=x

Vin Vout Vin Vout

0

Vdd

Vdd Vdd Vdd

1 1 0 Vdd/2 Indeterminate

logic level


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Combinational Logic

Serial structure

S1

S2

S1

S2

S1=0

S2=0

S1=0

S2=1

S1=1

S2=0

S1=1

S2=1

S1=0

S2=0

S1=0

S2=1

S1=1

S2=0

S1=1

S2=1

a

b

b

a

S1

S20

1

0 1

S1

S20

1

0 1

a!=b a!=b

a!=b a=b

a=b a!=b

a!=b a!=b


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NAND Gate

A

B

A

B

Output

Output

A

B1

0

10

1 1

1 0


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NOR Gate

A

B

A

B

Output

Output

A

B1

0

10

1 0

0 0


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Compound Gate

A B

A

B

FF

C D

C

D

AB

CD

))()(( CDABF


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Structured Logic Design

CMOS logic gates are intrinsically inverting The output always produces a NOT operation

acting on the input variables

For example, the inverter shown belowillustrates this property

VDD

f=0a=1

1

0


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Structured Logic Design

The inverting nature of CMOS logic circuitsallows us to construct logic circuits for AOIand OAI expressions using a structured

approach AOI logic function Implements the operations in the order AND then

OR then NOT E.g.,

OAI logic function Implements the operations in the order OR then

AND then NOT

E.g.,

dcbadcbag ..),,,(

)()(),,,( dcbadcbag


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Dual Property

If an NMOS group yields a function of the form

then an identically wired PMOS array gives thedual function

where the AND and OR operations have beeninterchanged

This is an interesting property of NMOS-PMOSlogic that can be exploited in some CMOS designs

)( cbag

)( cbaG


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An Example of Structured Design

)( dcbaX

VDD

a

b

a

X

b

dc

d

c

Group 1 Group 2

Group 3


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An Example of XOR Gate

Boolean equation of the two input XOR gate , this is not in AOI form

But, , this is in AOI form

Therefore,

bababa

bababa

babababa )(

VDDa

b

a

b

a

b

b

a

ba

VDDa

b

a

b

a

b

b

aba

XOR Gate XNOR Gate


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Static CMOS Summary

In static circuits at every point in time (exceptwhen switching), the output is connected toeither Vdd or Gnd through a low resistance path

Fan-in of n(or ninputs) requires 2n(nN-type and nP-type) devices

Non-ratioed logic: gates operate independent of

PMOS or NMOS sizes No path ever exists between Vdd and Gnd: low

static power

Fully-restored logic (NMOS passes 0 only andPMOS passes 1 only

Gates must be inverting


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Design Flow for a VLSI Chip

Specification

Behavioral Design

Structural Design

Physical Design

Function

Function

Function

Timing

Power


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Behavior Representation

A one-bit full adder (Verilog)

modulefadder(sum,cout,a,b,ci);

outputsum, cout;inputa, b, ci;

regsum, cout;

always @(a or b or ci) begin

sum = a^b^ci;

cout = (a&b)|(b&ci)|(ci&a);

endendmodule

ci

a b

cout

sum

fadder


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Cmos Aoi Design

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