CMOS Analog Design Using All-Region MOSFET Modeling 1 CMOS Analog Design Using All-region MOSFET...

CMOS Analog Design Using All-Region MOSFET Modeling

1

CMOS Analog Design Using All-region MOSFET Modeling

Chapter 3

CMOS technology, components, and

layout techniques


2

Simplified CMOS process flow

p-type substrate

STISTI

(b)

STI STI

NitridePhotoresist Photoresist

p-type substrate (a)

Oxide

Photo-resistPoly

STI

p-type substrate

STI STI p-well n-well

(d)

Photo-resistPoly

p-type substrate

p-well n-well

(c)

STI STI STI

STI

n+ poly p+ polyn+ n+ p+ p+

p-type substrate

p-well n-wellSTI STI STI

(e)

Oxide spacern+

polyp+ polyn+ n+ p+ p+

p-type substrate

STIp-well

n-wellSTI STI STI

(f)

Oxide spacer p+

polyn+ n+ p+ p+

p-type substrate

STI

p-welln-well

STI STI STI

(g)

n+

poly


3

CMOS structure

Triple-well process

p-substrate

deep n-well

n-wellp-well

n+ n+ p+ p+

Transistors in deep-submicron process


4

180 nm technology node

nMOS pMOS

Supply voltage 1.3 - 1.5V 1.3 - 1.5V

Thin oxide 3 nm 3 nm

Lgate 130 nm 150 nm

VT 0.3 V (130 nm) -0.24 V (150 nm)

IDsat (1.5V) 0.94 mA/m 0.42 mA/m

Ioff 3 nA/m 3 nA/m

gmsat 860 mS/mm 430 mS/mm

Cj (0V) 0.65 fF/m2 0.95 fF/m2

Silicide ( S, D and poly) 3 - 5 /sq 3 - 5 /sq

Parameters of a six-metal-layer 180-nm CMOS technology node


5

Integrated resistors

( ) ( )

V FL LR

I hW qnv hW qn

h L

W

1SH

L LR R

W hq n W

1SH

hR q nh

1

0

h

SHR q ndx

In the general case


6

Resistivity of some metals

Metal (bulk) Resistivity at 20 oC TCR

Aluminum 2.8·10-6 -cm 3800 ppm/oC

Copper 1.7·10-6 -cm 4000 ppm/oC

Gold 2.4·10-6 -cm 3700 ppm/oC

Sheet resistance of a copper layer of 1000 nm depth

6

4

1.7 10 cm17 mΩ/sq

10 cmSHRh


7

Polysilicon resistors


7


8

Summary of resistors in CMOS technology

Resistor type Sheet resistance (/sq)

Temperature coefficient (ppm/oC)

Voltage coefficient

(ppm/V)

n+ Polysilicon 100 -800 50

p+ Polysilicon 200 200 50

n+/ p+ Polysilicon (silicided)

5

n+ Diffusion 50 1500 500

p+ Diffusion 100 1500 500

n-Well 1000 2500 10000


9

The MOS transistor as a resistor

Example: Verify that, in strong inversion, the equivalent resistance between source and drain of an MOS transistor at VDS=0 is given by

VQ is the dc potential at the source.

0 0 0

211 1

DS DS DS

SD Dms f

V D S tV V

IdI dIg i

R dV dV

0( )

0

1

DS

G Tms d ox Q

V

V VWg C n V

R L n


10

Metal-insulator-metal capacitors

(a)

Substrate

C1

C2

C3

Cparasitic

C=C1+C2+C3

Metal 1

Metal 2

Metal 3

Metal 4

Top view

Cross section

(b)

(a) vertical parallel plate structure, (b) lateral flux capacitor.


11

Metal-oxide semiconductor capacitors

(a) Poly-semiconductor (b) poly-poly capacitors

VCC is typically around 100 ppm/V

TCC is of the order of 20 ppm/oC.

11 1gb

c ox

C

C C

2

3ox

s A

CVCC

q N

2

1 1 1 1ox ox c ox ox

ox ox oxc

dt C dC d ddATCC

A dT t dT dT dT dTC


12

MOSFET gate capacitors - 1

Gate capacitors in a p-well CMOS technology


13


experiment

theory


14

Intrinsic capacitances of the MOS transistor for VDS=0

1

20

gs gd ox

gb

C C C

C

0gs gd

gb ox

C C

C C


In accumulation

In strong inversion


15

In accumulation

In inversion, a similar expression holds

2 21 1

2 2t t

gb ox oxt FB G s t FB G

C C CV V V V

2

2 t

FB G

VCCV V

2

2 t

G T

VCCV V



16

Summary of capacitors in CMOS


16

Capacitor type Capacitance per unit area ( aF/m2)

Temperature coefficient (ppm/C)

Voltage coefficient (ppm/V)

MOM 150 20 10

MOM (combined lateral and vertical structure)

200 20 10

MOS gate (biased) 5000 200 10000

MOS (heavily doped Si option)

1000 20 10

MIM (thin oxide option)

1000 20 10

Poly-poly 1000 20 10


17

Inductors

20

2 7 65 4 10 50 10 1.6 nH

L n r

Example: Inductance of a 5-turn spiral inductor with an average radius of 50 m .

Planar spiral inductor


18

Bipolar transistors (BJTs) in CMOS

Flow of carriers in the CMOS-compatible bipolar junction transistor


19

BJTs in triple-well CMOS


20

Latchup

Parasitic bipolar transistors in CMOS technology which may lead to latchup. (a) Cross section of the CMOS structure; (b) Equivalent circuit of the parasitic bipolar transistors and resistors


21

Optical lithography - 1

Wafer

Mask

Photoresist

Ultraviolet light


22

Source Wavelength (nm)

Intended resolution (nm)

Year of introduction

G-line * 436 1000

I-line * 365 500 1984

KrF laser 248 250 1989

ArF laser 193 100 2001

F2 laser 157 65 **

*Filtered spectral components of high-pressure Hg or Hg-rare gas discharge lamps.** The technology was abandoned.


Wavelength used for optical lithography


23


Optical proximity correction (OPC) counteracts lithography distortions


24

MOSFET layout - 1

Mask layout and cross section of a CMOS inverter. N-well and P-well contacts not shown. Dashed lines represent metal connections


25

Source/drain implant

Shaded region Asymmetry

MOSFET layout - 2

Diagonal shift in the source drain regions of a transistor due to a tilted implant


26

No Rule

1 Same structure

2 Same shape, same size

3 Same orientation

4 Same surroundings

5 Minimum distance

6 Common-centroid geometries

7 Same temperature

Rules for minimizing systematic mismatch of integrated devices

MOSFET layout - 3


27CMOS Analog Design Using All-Region MOSFET Modeling

27

Matching improvement by the addition of dummy devices for the layout of two resistors with a resistance ratio of 2/1: (a) unconnected dummy resistors (b) connected dummy resistors

Unconnected dummy

Unconnected dummy

Conn. dummy

Conn. dummy

MOSFET layout - 4


28

(a)

Cox Cox+Cox Cox+2CoxCox+3Cox

A B

AB

A B B A(b)

MOSFET layout - 5

Mock layouts of some possible common-centroid geometries for improved matching. Transistors with the same label are connected in parallel.


29

A differential pair with a folded layout

A B

C

D E

A B

C

D E

C

D E

A B

MOSFET layout - 6


30

A B

CD E

F

GC

D E

A B F

G

BA

GF

C

D E

MOSFET layout - 7

A third device is added to the differential pair without degrading the symmetry of the layout


31

Common-centroid layout of a differential pair.


31

A B

D E

C

A

C

B

E

DC

MOSFET layout - 8


32

Current mirror with an attenuation factor of 16: (a) Schematic; (b) Mock layout.

Iin

(b)

Iout

Iout

Iin

(a)

MOSFET layout - 9

CMOS Analog Design Using All-Region MOSFET Modeling 1 CMOS Analog Design Using All-region MOSFET...

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Transcript of CMOS Analog Design Using All-Region MOSFET Modeling 1 CMOS Analog Design Using All-region MOSFET...