CMOS Analog Design Using All-Region MOSFET Modeling 1 Chapter 6 Current Sources and Voltage...

CMOS Analog Design Using All-Region MOSFET Modeling

1


Chapter 6

Current Sources and

Voltage References


2

Simple MOS current source

(a) A simple MOS current source (b) Current x voltage characteristic of the input transistor and load line.

0 1 2 ln 1 1REF REFREF DD T t

S S

I IRI V V n

I I

IREF is, in general, very

sensitive to VDD, R,

and M

Low current requires high R (large silicon area)


3

Widlar current source

Low current can be generated without large resistances

N is also a design parameter (more important than RS)

Input current IREF often high – not convenient for low-power design


4

Self-biased current source - 1

1

1 1

1

1 1

1 1 ln

1 1

OUT

SS OUT OUT OUT

t S S OUT

S

I

IR I I I

I KI I

KI

lntOUT

S

I KR

22

21

2

2

1

11

2 11

/

tOUT

S S

S n ox

IR I K

R C n W L K

weak inversion

strong inversion

1 1 SWI

S

dRTC

T R dT

1 2n SSI

n S

dn dRTC

n dT R dT


5

I1

I2

I2=I1Current mirror

M3-M4

Current mirror M1-M2-RSPoint A

Point B

Start-up circuit:

ensures that A is the solution;

“wakes-up” current source ASAP after power-up

Self-biased current source - 2


6

MOSFET-only self-biased current source

1121

1

1 11 1 ln ln

1 1

ffSf

t f

iiVi K

K i

K

56 5 1

4D D D

SI I I

S

7 7 7 7 1 1 1( )D S f r D S fI I i i I I i

67 6

6

Df f

S

Ii i

I

727 7

7

1 11 1 ln

1 1

fSf r

t r

iVi i

i

5 17 1

4 6f f

S Si i

S S 6 6 54 4 1

7 7 15 7 5 7 4 6

1 1r f f

S S SS S Si i i

S S S S S S

,

2

7 2 1 2 ( 1)2t

OUT n oxI C n S J J J J=S5S7/S4S6


7

Bandgap voltage reference – 1

Choose M such that

00

0out BE

TT

dV dV kM

dT dT q

The output voltage for zero temperature coefficient is close to the “extrapolated” band-gap voltage of Si (1.206 V)

T

VBE

~ -2 mV/oC

T

k/q=+ 86.19 V/oC

t

VCC

t generator

t Mt

+VBE

-

M

I1

out BE tV V M


8

00

0out BE

TT

dV dV kM

dT dT q

T

constantBE

kTV M

q

BEV

tM



9

1 exp BEC sat

t

VI I I

2i n t

satB

qAnI

G

2 3 exp G

i

En DT

kT

0 0/m

n n T T EG: 1.206 eV, silicon bandgap extrapolated to 0 K.

Assume the average mobility of electrons in the base region is

The temperature coefficient of the voltage reference is

0

BW

B AG N dx

1 0 0/CI I T T

(4 )BE t GBE

d V M EV km M

dT T q kT

Assume that

0

0 0

(4 )/

BE GV EM m

kT q kT

=0 at T=T0

0

0

2

0

(4 )(1 ln )

(4 )2

GOUT

OUT T T

E TkTV m

q q T

T TkTV m

q T



10

CMOS-compatible bandgap reference - 1

1 21 2

2 1

/ln

/O BE BE

I W LkTV V V V V n

q I W L

Problem: n=n(T, VG)

Minimum supply: VBE+V1+VDSsat (current

source)

Both M1 and M2 in weak inversion


11


PTAT voltage generator. Transistors M1 and M3 are biased in weak inversion.

32 2 2

1 4 1 4

1 1 lnO

SR S SkTV

R S q S S


12


VCC

+VBE1

-

I1

VCC

+VBE2

-

I2

1 11

1 1

2 22

2 2

1 21 2

2 1

ln ln

ln ln

ln

BE t tS S

BE t tS S

BE BE BE t

I IV

I J A

I IV

I J A

I AV V V

I A

1 2 1 lnR E E

kTV V V N

q

22

1

1 lnREF BE

R kTV V N

R q


13


22

1

lnREF EB

R kTV V N

R q

Problems:

Op amp offset voltage

Poor performance of substrate pnp transistors ??


14

Exercise

22

3

1OUT EB EB OS

RV V V V

R

Band-gap reference in n-well CMOS

Vertical (substrate) pnp transistors

Exercise: Show that

Source of error


15


VFCMVFCM: voltage following

current mirror

23

1

lnREF EB

R kTV V N

R q


16

Eric A. Vittoz, MOS Transistors Operated in the Lateral Bipolar Mode and Their Application in CMOS Technology, IEEE JSSC, Vol. 18, no. 3, pp. 273-279, June 1983

p-well CMOS process



17

CMOS bandgap reference with sub-1-V operation

VDD

M3M1

M2

R1

1

Q1

N

I1aR2

VREF

Q2

+

R2 R3I2a

I1bI2b

I1 I2I3

I1=I2=I3

-


18

Design of a SBCS – 1

21 2 2

1

11 1f f f

Si i i

S N

2

2 2

2

1 11 1 ln

1 1

fXf f

t f

iVi i

i

2 2

1 1 2( ) ( 1)

S f x

S f f x

I i NI

I i i N I

Applying UICM to both M1 & M2

2 1f ri i

Sat.

Triode

2 xI NI

SELF-CASCODE MOSFET (SCM)

2

2 2

2

1 1

1 1 ln

1 1

X

SHX X X

t SH SH X

SH

NIS IV NI NI

S I S I NIS I


19

1 0.01 S

2 0.01 S IX

IX

2IX

3 10 S

4 1.13 S IX

IX

2IX 1 1

1 1 ln

1 1

X

SHX X X

t SH SH X

SH

ISIV I I

SI SI ISI

/X tV

/X SHI I

SCM1,2 SCM3,4 3

0.01S

18.71.13S



20

VOLTAGE FOLLOWING (NMOS) CURRENT MIRROR (PMOS)1

9 ln( )ref S tV V JK

When both M8 & M9 operate in WI:

898 8

8

1 11 1 ln

1 1

fref Sf f

t f

JKiV VJKi i

i



21

A self-biased current source

Vx

VFCMVx



22

VFCM

2

1

11 1 1 1 1 3

S

S N

1 30 11 30 1 10 ln 2.93

1 10 1X

t

V

M1 &M2 in MI: if2 = 10 S2= S1, N = 1

2

2 2

2

1 11 1 ln

1 1

fXf f

t f

iVi i

i

Let us choose

M3 &M4 in WI: if3(4) <<1

2.93ln 18.7X

t

Ve

4 4

3 3

118.7 1 1 8.85

1

S S

S S

Output current: Iref=10 nA

ISHn-channel100 nA, ISHp-channel40 nA

=1

=10 nA

2 2 2 2 110 nA 1 nA 0.01 S f SI i I S S Let us choose if3=0.187 4 3 4 3/ 1 2 / 0.01f fi i S S 4 4 4 410 nA 1 A 10S f SI i I S

43 1.13

8.85

SS



23

S if ir

M1 0.01 10 0

M2 0.01 30 10

M3 1.13 0.187 0.01

M4 10 0.01 0

M8, M8(a) 1 0. 1 0

M9, M9(a) 1 0. 1 0

MP (all) 2.5 0.1 0

4 10S

VFCM

=1

=10 nA

2 1 0.0S

2.93X tV 2.93X tV 3 1.13S 1 1 0.0S

Summary



24


CMOS Analog Design Using All-Region MOSFET Modeling 1 Chapter 6 Current Sources and Voltage...

Documents

Transcript of CMOS Analog Design Using All-Region MOSFET Modeling 1 Chapter 6 Current Sources and Voltage...