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1
Closing the loop in high speed design
Improving your process forhigh-speed PCB design
“Closing the loop between timing analysis and signal integrity”
A PCB Knowledge SetOnline Seminar from Cadence
presented by Todd Westerhoff
System Timing
Signal Integrity
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Closing the loop in high speed design
Agenda
• Basics of system timing analysis• Basics of signal integrity analysis • Flight time, buffer delay, standard loads and Tco
• Key process assumptions• Checking and verifying model data• Techniques for closing the loop• Summary
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Closing the loop in high speed design
Static Timing Analysis
• Systematic analysis of a synchronous ASIC, PCB or System design, that identifies:– Logic hazards– Clocked timing paths– Timing errors
• Required inputs– Functional description of circuit (netlist)– Component-level timing data– Circuit operating (clock) speeds
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Closing the loop in high speed design
What is a “Clocked Timing Path”?
• A timing path consists of all of the logic between two clocked elements that operate off the same clock signal
• The timing path is analyzed to ensure that setup and hold requirements are met at the input of each clocked element
• The slack (delay margin) in the path can be used to derive SI flight time constraints
D
Q
Qn D
Q
QnD
Q
QnD
Q
Qn D
Q
QnD
Q
Qn
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Closing the loop in high speed design
Modern System Design
• Modern systems are dominated by high speed bus interconnections
– Combinational logic has been “absorbed” into other chips
• Timing analysis for data buses can be performed using a simplified “bus-level” timing model
CPU
AGPDIMM
PCI
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Closing the loop in high speed design
Standard Synchronous Data Transfer
Hol
d
D0
D1
D2
D0
D1
D2
ClockDriver
Driving Receiving
Tco
Flight Time
Setu
p
1
2
3
4
Hol
d
D0
D1
D2
D0
D1
D2
ClockDriver
Driving Receiving
Tco
Flight Time
Setu
p
1
2
3
4
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Closing the loop in high speed design
Flight Time
• Accounts for the electrical delay of interconnect (PCB etch) between the driving device and receivers
• Can be estimated for slow speed circuits; must be simulated (signal integrity) for high speed designs
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Closing the loop in high speed design
Issues in Synchronous Design
• Clock Jitter increases / decreases the individual clock cycle, decreasing the time left for data transfer
• Clock Skew changes the effective clock period depending on which devices are driving / receivingD0
D1
D2
ClockDriver
D0
D1
D2
t = 0
t = 1 t = 2
Cycle 1 Cycle 2
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Closing the loop in high speed design
Crosstalk - Impact on Bus Timing
• Crosstalk between adjacent bus bits affects edge speed (and therefore flight time)
• Denser routing makes better use of board space, but at the expense of larger variations in flight time
• Pre-layout crosstalk analysis helps the designer make the best tradeoff between routing density and signal integrity
Even Mode
Reference
Odd Mode
D0
D1
D2
D0D1D2
D0
D1
D2
D0 D1 D2
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Closing the loop in high speed design
Bus-Level Timing Budget
• For each independent Driver Receiver path:– Tflightmax < Clock Period - Driver(Tcomax) - Skew - Jitter - Crosstalk - Receiver(Setup)
– Tflightmin > Receiver(Hold) - Driver(Tcomin) + Skew + Crosstalk
Driver(Tcomax) Tflightmax +/- Jitter +/- Skew Receiver(Setup)
< Clock Period
Driver(Tcomin) Tflightmin +/- Skew
> Receiver (Hold)
+/- Crosstalk
+/- Crosstalk
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Closing the loop in high speed design
Determining Device Timing
• Timings taken from “AC (dynamic) Specifications” sections of datasheets
• Many datasheets available on-line via WWW
• Important parameters– Clock Data Valid
• Conditions under which this is measured
– Setup / Hold requirements – PLL Jitter (if spec’d)
Example - Pentium Pro
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Closing the loop in high speed design
Determining Flight Times: ExampleDevice Timing Information
Tcomin Tcomax Setup Hold
Pentium Pro 0.55 ns 4.40 ns 2.20 ns 0.45 ns440FX 1.25 ns 7.25 ns 5.00 ns 0.00 ns
Pentium Pro to 440FXTflightmax = ClockPeriod - Tcomax - Skew - Jitter - Crosstalk - Receiver(Setup)
4.60 ns 15.00 ns 4.40 ns 0.20 ns 0.40 ns 0.40 ns 5.00 ns
Tflightmin = Receiver(Hold) - Tcomin + Skew + Crosstalk0.05 ns 0.00 ns 0.55 ns 0.20 ns 0.40 ns
440FX to Pentium ProTflightmax = ClockPeriod - Tcomax - Skew - Jitter - Crosstalk - Receiver(Setup)
4.55 ns 15.00 ns 7.25 ns 0.20 ns 0.40 ns 0.40 ns 2.20 ns
Tflightmin = Receiver(Hold) - Tcomin + Skew + Crosstalk-0.20 ns 0.45 ns 1.25 ns 0.20 ns 0.40 ns
• Tflightmax = 4.55 ns • Tflightmin = 0.05 ns
Budgeted Parameters
Clock Skew 0.2 ns
Clock Jitter 0.4 nsCrosstalk 0.4 nsClock Freq. 66.7 MHz
Clock Period 15 ns
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Closing the loop in high speed design
What Is Signal Integrity Analysis?
• Analog analysis of digital switching behavior
• Extracts routing information from PCB database
• Use special analog models for device inputs / outputs– IBIS modeling standard
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Closing the loop in high speed design
The Signal Integrity Model
• SI models represent only the behavior of the device output and input buffers
• Internal component functions and associated timing are not modeled
Driving Receiving
t = 0
InternalLogic notmodeled
InternalLogic notmodeled
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Closing the loop in high speed design
Measuring Interconnect Delay
• Accounts for electrical delay caused by interconnect (PCB etch) between the driving device and each receiver on the net
• Usually different for each driver – receiver combination
• Can be determined using signal integrity analysis
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Closing the loop in high speed design
Minimum and Maximum Delays
• The receiver’s input thresholds are used to determine the earliest and latest times that the input change may be detected– This information is then used to
determine minimum & maximum flight time data for each driver / receiver combinationEarliest Switch
Latest Switch
InputThresholds
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Closing the loop in high speed design
A Closer Look At Tco
Din
Clock
OutputBuffer
InternalLogic
RL = 50
Clocktriggersat t = 0
Vmeas
Tco
Load for Tco measurement(from databook)
Tco = time from clock rise to Vmeas into test load
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Closing the loop in high speed design
Components of Tco
Din
Clock
OutputBuffer
InternalLogic
RL = 50
Clocktriggersat t = 0
Vmeas
Tco
Internal delay = from clock trigger to the time when the output buffer is triggered
External (buffer) delay = howlong the buffer takes to drive thereference load to Vmeas
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Closing the loop in high speed design
The Double-Counting Problem
• We want to know at what point in the clock period signals arrive and stabilize at the receiver input
– This is compared to setup/hold constraints
• This is found by combining component timing data (TCO) with flight time data from signal integrity analysis
Hol
d D0
D1
D2
D0
D1
D2
ClockDriver
Driving Receiving
Tco
Flight Time
Setu
p
1
2
3
4
Hol
d D0
D1
D2
D0
D1
D2
ClockDriver
Driving Receiving
Tco
Flight Time
Setu
p
1
2
3
4
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Closing the loop in high speed design
But, If We Simply Add …
Din
Clock
OutputBuffer
InternalLogic
RL = 50
Clocktriggersat t = 0
Vmeas
Tco
Load for Tco measurement(from databook)
Tco = time from clock rise to Vmeas into test load
Din
Clock
OutputBuffer
InternalLogic
RL = 50
Clocktriggersat t = 0
Vmeas
Tco
Load for Tco measurement(from databook)
Tco = time from clock rise to Vmeas into test load
Driving Receiving
t = 0
InternalLogic notmodeled
InternalLogic notmodeled
Driving Receiving
t = 0
InternalLogic notmodeled
InternalLogic notmodeled
TCO (from Databook) + Simulated Delay
+
The external buffer delay portion of Tco gets double-counted !!
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Closing the loop in high speed design
Because, What We Really Wanted Was …
Din
Clock
InternalLogic
Clocktriggersat t = 0
Internal delay = from clock trigger to the time when the output buffer is triggered
Din
Clock
InternalLogic
Clocktriggersat t = 0
Internal delay = from clock trigger to the time when the output buffer is triggered
Driving Receiving
t = 0
InternalLogic notmodeled
InternalLogic notmodeled
Driving Receiving
t = 0
InternalLogic notmodeled
InternalLogic notmodeled
Internal Delay + Simulated Delay
+
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Closing the loop in high speed design
Making The Pieces Fit Together
• There are two ways to solve this discrepancy:
1. Adjust the value of TCO used for timing analysis by
subtracting out the time attributed to TCO buffer delay
2. Subtract the time attributed to the TCO buffer delay from
the input receiver switching times predicted by simulation
• By convention, the latter method is used.
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Closing the loop in high speed design
Determining The Buffer Delay ...
• The output buffer model used for signal integrity analysis is connected to the TCO “test load” and simulated
• The delay is measured at the point where the output pin crosses Vmeas
• The corresponding delay is saved and used in flight time computations
OutputBuffer
InternalLogic notmodeled
RL = 50 Bufferswitches
at t = 0
Vmeas
Buffer Delay
Load for Tco measurement(from databook)
OutputBuffer
InternalLogic notmodeled
RL = 50 Bufferswitches
at t = 0
Vmeas
Buffer Delay
Load for Tco measurement(from databook)
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Closing the loop in high speed design
Measuring Flight Time
• Flight time is therefore always measured with respect to the delay into the standard load
• This is accomplished by determining the TCO buffer delay, and subtracting that value from simulation results
Buffer delay into Standard Load880.55ps, 2.5V
3.0V = VIH
2.0V = VIL
2.5V = Vmeas
Max Flight608.71ps
Min Flight476.32ps
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Closing the loop in high speed design
Implications
• The output-to-input delay, as apparent from waveform data cannot be directly measured to determine flight time
• The loading condition used to compute buffer delay and the conditions under which Tco is measured must be identical
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Closing the loop in high speed design
Fundamental Assumptions
• Timing equations are valid for bus timing– Assumes common clock, synchronous design– Inter-symbol interference (ISI) can invalidate equations
• SI models provide good prediction of system behavior• Loading condition for Tco is “representative” of actual
system loading conditions• The Tco load is user to calculate buffer delay• Simulation results are correctly adjusted to meet the
definition for flight time (either by the tool or manually)
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Closing the loop in high speed design
A Few Words on Device Modeling …
• Quality problems are not unusual in SI models (unfortunately)– Check model quality!– Check buffer delay information
• Different models support different purposes– Pre-layout models (min / max
package parasitics only)– Post-layout models (detailed
per-pin parasitic data)
Data from IBIS model with per-pin lumped parasitics
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Closing the loop in high speed design
Verifying Standard Loading Conditions
. . .
Model_type I/O_open_drain
Polarity Non-Inverting
Enable Active-Low
Vinl = 0.8
Vinh = 1.2
Vmeas = 1.00
Cref = 0.00p
Rref = 25.00
Vref = 1.50
. . .
• IBIS provides specific keywords to define the conditions under which buffer delays should be simulated and measured
• The measurement / loading conditions in the IBIS file should be the same as the conditions under which TCO is specified in the device’s datasheet
IBIS Model File
Vmeas = 1.00
Cref = 0.00p
Rref = 25.00
Vref = 1.50
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Closing the loop in high speed design
Closing The Loop
• Different ways to integrate timing analysis and signal integrity results:– Manual approach: determine allowable min/max flight times
using component timing data and a spreadsheet. Use signal integrity analysis to verify that the design meets the computed flight time requirements.
– General approach: use static timing analysis to evaluate system timing, and signal integrity analysis to compute flight times. Feed flight time data back into the static timing tool.
– Bus-level timing approach: use standard timing equations and component timing data to perform spreadsheet-based timing analysis. Feed flight times from signal integrity analysis back into the spreadsheet to compute design margins.
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Closing the loop in high speed design
Manual Approach
• For common-clock buses, allowable min/max flight times can be computed from bus speeds, system budgets and component timing data
• Timing equations are programmed into a spreadsheet and allowable flight times computed
• While not elegant, this method is fast, flexible and reliable when the timing for a small number of buses needs to be determined
Device Timing InformationTcomin Tcomax Setup Hold
Pentium Pro 0.55 ns 4.40 ns 2.20 ns 0.45 ns440FX 1.25 ns 7.25 ns 5.00 ns 0.00 ns
Budge te d Pa ra m e te rs
Clock Skew 0.2 ns
Clock Jitter 0.4 nsCrosstalk 0.4 nsClock Freq. 66 MHz
Clock Period 15.15 ns
Pentium Pro to 440FXTflightmax = ClockPeriod - Tcomax - Skew - Jitter - Crosstalk - Receiver(Setup)
4.75 ns 15.15 ns 4.40 ns 0.20 ns 0.40 ns 0.40 ns 5.00 ns
Tflightmin = Receiver(Hold) - Tcomin + Skew + Crosstalk0.05 ns 0.00 ns 0.55 ns 0.20 ns 0.40 ns
440FX to Pentium ProTflightmax = ClockPeriod - Tcomax - Skew - Jitter - Crosstalk - Receiver(Setup)
4.70 ns 15.15 ns 7.25 ns 0.20 ns 0.40 ns 0.40 ns 2.20 ns
Tflightmin = Receiver(Hold) - Tcomin + Skew + Crosstalk-0.20 ns 0.45 ns 1.25 ns 0.20 ns 0.40 ns
• Tflightmax = 4.70 ns• Tflightmin = 0.05 ns
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Closing the loop in high speed design
General Approach
• Timing analysis, layout and SI analysis are run as separate processes• Flight time data from signal integrity analysis is fed back into timing
analysis to complete the loop and integrate the two sets of data• Changing the design requires re-running the complete loop
Schematic Capture
PCB Layout
Static Timing Analysis
Signal Integrity Analysis
Netlist RoutedDatabase
FlightTimes
Constraints
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Closing the loop in high speed design
Bus-Level Approach
• Component timing, bus speeds and clock jitter / skew budgets are captured as part of the PCB database
• Signal integrity analysis is run from the PCB database
• A spreadsheet containing bus-level timing equations is used to compute the design margins based on simulation results
Schematic Capture
PCB Layout
Timing Spreadsheet
Signal Integrity Analysis
Netlist
FlightTimes
Component Timing Data
Component Timing Data
RoutedDatabase
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Closing the loop in high speed design
SPECCTRAQuest Timing Model
Loaded from component timing dataSpecified in timing spreadsheet and saved in databaseDefined as property in Allegro databaseComputed using SI analysis
Driver(Tcomax) Tflightmax +/- Jitter +/- Skew Receiver(Setup)
< Clock Period
Driver(Tcomin) Tflightmin +/- Skew
> Receiver (Hold)
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Closing the loop in high speed design
SPECCTRAQuest Timing FlowComponent timing data
Clock Net declarations, operating speeds, clock jitter
Clock jitter and skew budgets
Simulated flight times
SPECCTRAQuest floorplanner
SigNoise analysis
SPECCTRAQuest Timing Spreadsheet
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Closing the loop in high speed design
Observations – Bus Timing Model
Advantages• Bus-level timing and signal
integrity analysis is integrated in a single tool
• Analysis can be run interactively as parts are moved or nets are routed
• All information is kept in a single design database
Caveats• The bus timing model is targeted
at common-clocked synchronous buses
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Closing the loop in high speed design
Summary
• Both timing and signal integrity analysis are critical aspects of ensuring a design will work “at speed”
• The results of both analyses must be integrated to get the complete picture of system timing behavior
• Each type of analysis assumes certain conventions about how delays are computed
• Designers must understand these conventions and be able to check/validate design data for conformity
• SPECCTRAQuest provides a “bus timing model” capability for integrating signal integrity and timing analysis
37
Closing the loop in high speed design
Improving your process forhigh-speed PCB design
“Closing the loop between timing analysis and signal integrity”
A PCB Knowledge SetOnline Seminar from Cadence
presented by Todd Westerhoff
System Timing
Signal Integrity