Clockless Chip by rahul rk(9986510206)

Clockless ChipsClockless ChipsUnder the esteemed guidance of

Romy SinhaLecturer, REC Bhalki

Presented by:Lokesh S. Woldoddy

3RB05CS122

Date:11 April 2009Date:11 April 2009..

Presentation on Clockless Chips 2

Content:Content: Introduction. Concept of clock. Working of synchronous circuit. Asynchronous logic circuits. GENERAL MODEL OF ASYNCHRONOUS DESIGN Synchronous and asynchronous. How do they work? Clock time cycle vs. clockless time cycle. Simple and efficient design DIFFERENT STYLES. Problems with Synchronous Approach. Synchronous circuit. Some features. Challenges. Advantages. Applications. Conclusion. References.


Introduction.Introduction.

Struggle for the improvement in the microprocessor’s

performance/functioning.

– Pipelining

– (Simultaneous) Multi-threading

– Clockless / Asynchronous logic

}Synchronous


Concept of clockConcept of clockCLOCK:

– Tiny crystal oscillator.

– Sets basic rhythm used throughout the machine.

ADVANTAGES:

– Signals the device of the chip when to i/p or o/p.

– This functionality makes designing of synchronous chip easier.

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Presentation on Clockless Chips 5Adapted : http://www.cs.columbia.edu/async/misc/technologyreview_oct_01_2001.html

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Clockless chips (Asynchronous logic circuits)Clockless chips (Asynchronous logic circuits)

Colckless chips/Asynchronous/self-timed circuits.

Functions away from the clock.

Different parts work at different speeds.

Hand-off the result immediately.


GENERAL MODEL OF ASYNCHRONOUS GENERAL MODEL OF ASYNCHRONOUS DESIGNDESIGN::

Adapted:David Geer,”Is it time for clockless chips?,”IEEE paper,pp.18-21,March 2005 7


Courtesy:Courtesy: Computers without clocks – Ivan E Sutherland and Jo Ebergen Computers without clocks – Ivan E Sutherland and Jo Ebergen


How do they work?How do they work?

No pure asynchronous chips are available.

Uses handshake signals for the data exchange.

Data moves only when required, not always.

– Minimizes power consumption.

– Less EMI less noise more applications.

– Stream data applications.


Clock time cycle vs. clockless time cycleClock time cycle vs. clockless time cycle

Courtesy:Courtesy: Fulcrum Microsystems. Fulcrum Microsystems.


Simple and efficient designSimple and efficient design

No centralized clock required.

Standardized components can be used.


DIFFERENTDIFFERENT STYLES:STYLES: Simplest implementation of asynchronous

design.

Assumption: we know the largest amount of time for each component to perform its task.

Very similar to synchronous design.

Prototype delay is introduced here.12


Problems with Synchronous ApproachProblems with Synchronous Approach

Distributing the clock globally.

Wastage of energy.

Traverse the chip’s longest wires in one clock cycle.

Order of arrival of the signals is unimportant.

Clocks themselves consume lot of energy (~30%).


Synchronous circuitSynchronous circuit

Longest path determines

the minimum clock

period.

Dissipation of energy for

each clock cycle.

EMI is more in

synchronous elements.


Some featuresSome features

Integrated pipelining mode.

– Domino logic.

– Delay – insensitive.

Two different implementation details

– Dual rail.

– Bundled data.


ChallengesChallenges

Interfacing between synchronous and asynchronous– Many devices available now are synchronous in nature.

– Special circuits are needed to align them.

Lack of expertise. Lack of tools. Engineers are not trained in these fields. Academically, no courses available.


Advantages (technical look)Advantages (technical look)

Asynchronous for higher

performance:

– Data-dependent delays.

– All carry bits need to be

computed.


AdvantagesAdvantages

Works at its average speed. Low power consumption.

Twice life-time.

Less heat generated. Good to mobile devices.

Less EMI less noise more applications. Smart cards (due to asynchronous nature).


ApplicationsApplications::In the lab.

In mobile electronics.

In personal computers.

In encryption devices.

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Conclusion:Conclusion:

Clocks are getting faster , while chips are getting bigger both of which make clock distribution harder

o There are also various other problems associated with it. So we could only get out of it , if more focus , especially at the university level is given to the asynchronous design.

o It is certainly a challenge , but as software community is moving towards concurrency, hardware community must move to incorporate asynchronous logic.


ReferencesReferences

Scanning the Technology: Applications of Asynchronous Circuits

– C. H. (Kees) van Berkel, Mark B. Josephs, and Steven M. Nowick

Computers without clocks – Ivan E Sutherland and Jo Ebergen.

http://ieeexplore.ieee.org/iel5/2/30617/01413111.pdf (October

2001)

http://csdl2.computer.org/comp/mags/dt/2003/06/d6005.pdf

http://www1.cs.columbia.edu/async/misc/technologyreview_oct_01_2001.html

http://www.technologyreview.com/articles/01/10/tristram1001.asp

http://www1.cs.columbia.edu/async/misc/economist/Economist_com.htm


Thank youThank you

Clockless Chip by rahul rk(9986510206)

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