CLASS – Clockless Logic, Analysis, Synthesis &...
Transcript of CLASS – Clockless Logic, Analysis, Synthesis &...
CLASS – ClocklessLogic, Analysis,
Synthesis & SystemsRoger Brees
Boeing Solid-State Electronics Development
Sponsors: DARPA Microsystems Technology Office and Air Force Research Labs
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CLASS
Outline
CLASS Motivation
CLASS Objectives
CLASS Approach and Plan
Current Status
Summary
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Motivation
• Development cost of advanced ASICs is becoming too great for low volume, DoD applications
• But DoD applications require capabilities enabled by advanced ASICs
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20
40
60
80
100
180nm 130nm 90nm 65nm
Dev
elop
men
t Cos
t($M
) Clockless Logic addresses Many of the ASIC Development Cost Drivers
Improves ReuseSimplifies Timing DesignReduces PowerReduces NoiseEliminates Fab Passes
Baseline
CLASS
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CLASS
CLASS Program Objectives
Enable Very Complex SoC Designs by Overcoming Approaching Limits of Clocked Design
Timing ClosureNoise/EMIIP ReusePower Management
Key Program Goals:Enable design of clockless circuitsOvercome clocked design inertiaMake clockless design available ASAP to DoD
1x
10x
102x
103x
104x
Perf
orm
ance
(Gop
s/W
att)
1x 10x 102x 103x 104xDevelopment Cost
DSPGPP
FPGAASIC
CLASS Custom
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Need for CLASS Program
• CLASS program develops critical enablers for design of clockless circuits
• ECAD – automated clockless logic implementation and optimization
• Multiple integrated clockless design styles providing range of power, performance, complexity, robustness
• IP• Methodology
• CLASS Program demonstrates clockless in complex, highly-constrained, DoD system
• Prove design methodology and tools• Provide Direct comparison of clockless system to clocked
system • Demonstrate benefits of clockless technology in compelling
defense application
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CLASS Impact
• CLASS will move clockless design into the mainstream
• Strategy:• Complete EDA infrastructure• Support diverse technologies• Show clear benefits to DoD SoC design houses• A vs. B (clocked vs. clockless) benchmark• Provide Compelling SoC Demonstration• Technology Transfer – Supported by commercial
companies
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Approach
• Build on proven clockless design toolset from Handshake Solutions
• Support multiple clockless logic styles for increased performance, power, reliability trade space
• Enhance with Optimizations
• Demonstrate value of asynchronous design in compelling DoD application
• Compare asynchronous implementation to equivalent synchronous implementation
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Team
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• Prime Contractor, Application, Demonstration Chip Design
• Null Convention Logic, Demonstration Chip Design
• Mobius Tool Flow
• Handshake Technology, Tool Flow
• Handshake Optimizations, NCL Optimizations, High-Speed Pipelines
• High-Speed Pipelines
• Locally Clocked Dynamic Logic
• Substrate Noise Coupling
• Integrated Testability Approach
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Asynchronous Technologies
• Combining benefits of broad range of Asynchronous Technologies
• Handshake Circuits• Very low power• Production design flow• Standard Libraries
• Null Convention Logic• Very low power• Delay insensitive
• Mousetrap High Speed Pipelines• Standard libraries• Integrated high-speed capability
• Locally Clocked Dynamic Logic• Highest speed capability
Performance
Des
ign
Rob
ustn
ess NCL
HandshakeMousetrap
LCDL
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CLASS
CLASS Infrastructure Development
Integrated Clockless Design
Environment
Test Tools
Clockless Design Tools
Libraries
Clockless Logic
Technologies
Clockless Analysis
Tools
IP
GALS InterfacesMemory Interfaces
Performance AnalysisClockless Rules CheckingPerformance Estimation
0.25µm0.18µm0.13µm
HandshakeMousetrapNull Convention LogicLocally Clocked Dynamic Logic
SimulationSynthesis
Test InsertionATPGIntegrated Test
Approach
Optimizations
PeepholeParallelismConstraint DrivenRe-synthesis
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Clockless Design Tools
• Proven Tool Framework from Handshake Solutions
• Simulation • Synthesis• Test
• Expanded integration with standard back-end tools• Support for Artisan 130nm libraries• Optimizations to push to higher performance
capabilities• Integration of High-speed pipeline (Mousetrap)
technology
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Clockless Design Tools
• Mobius from Codetronix• High-level Design • Flexibility to incorporate other asynchronous logic
styles• Path to delay insensitive Null Convention Logic from
Theseus Logic
• Integrated test strategy
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Optimizations
• Improve power, performance for Handshake circuits and NCL circuits
• Circuit transformations• Peephole optimizations• Control re-synthesis
• Design Flow optimizations• Improved parallelism between data path and control
path• Constraint driven synthesis and layout• Design templates
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CLASS Plan: Phased Development with Progress Demonstrations
Initial Tool Integration & Test Chip – Integrate async design tools into Boeing foundry-flexible design flow and demonstrate in silicon a significant block from the demonstration chip
Enhanced Tools & Demonstration Chip – Develop & integrate complete async design flow and demonstrate in silicon significant benefits of clockless design using complete ASP
Horizon Tools & Demonstration – Develop extended tool capabilities necessary to overcome clocked design inertia and demonstrate with ASP
J J A S O N D J F M A M J J A S O N D2005 2006
Test ChipTest Chip
Demonstration ChipDemonstration Chip
Horizon ToolsHorizon Tools
Initial ToolsInitial Tools
Enhanced ToolsEnhanced Tools
Horizon Demo.Horizon Demo.
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Initial Tools & Test Chip
• Initial tool capabilities installed
• Proven with 3 test chips
• IBM 130nm CMOS8RF
• Released on Trusted Foundry Multiproject Wafer
• Estimated Delivery: May 15
LCDL Test Chip
600k xstrs128 I/O
MousetrapTest Chip
100k xstrs128 I/O
T2 Test Chip• Handshake Circuits• 3.2M transistors
(async logic)• 1.5M bits RAM• 427 I/O
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Enhanced Tools
• Initial Optimizations incorporated• Handshake Circuits• NCL Circuits
• NCL technology integrated into Mobius tools
• Demonstration chip combines • Handshake Circuits• NCL Circuits• LCDL Circuits• Synchronous Circuits
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Demonstration Chip
• Compelling demonstration of async benefits• Improved Design Time• Improved Power/Performance• Improved Noise Characteristics
DIPF
Memory25Mbits
Target Enhancement Processor
• DoD Relevant Circuit• Advanced Sensor Processor• Mix of processing styles
– DSP– Numerical Methods
• Integrated memory (25 Mbits)• Integration into synchronous system• Challenging performance (180 MHz)• Challenging complexity (50M XSTRS)
• Trusted Foundry release in IBM 130nm CMOS8RF• Compare to Equivalent Synchronous Chip
DSP Processing
ADC ASP Processor
Sensor Computer
RFChain
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Demonstration
PXI Controller
GX5282 GX5282
ASIC Load Board
ASP Input
Corner
CLASSMemory
Turning
ASIC
Input Data Buffer
Input Scenario Resolved
Data
Real-Time
Off-Line
PXI ControllerNational Instruments
Lab View DiagnosticsNational Instruments
GX5282GeoTest
RTTB Post Process
Embedded PCNational Instruments
Output Data
Buffer
RTTB Data Set
Source Data Results
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Horizon Tools & Demonstration
• Complete development and integration of optimizations
• Complete integration of Mousetrap technology
• Initial system performance analysis capability
• Demonstrated using ASP circuits
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Key Products
Clockless Design Infrastructure A vs. B Comparison
Asynchronous Advanced Sensor Processor ASIC Real-time Demonstration
CLASS
Testability TechniquesDIPF
Memory25Mbits
Target Enhancement Processor
Tech.
Libraries
Methods
Training
Tools
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Summary
• Clockless Design is enabler for advanced DoD systems
• CLASS Program is lowering the barriers to adoption of clockless logic
This material is based upon work supported by the United States Air Force and DARPA under Contract No. FA84750-04-C-0007.
Any opinions, findings, and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the United States Air Force and DARPA.