CLOCKLESS CLOCKLESS CHIPSCHIPS

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Abi MathewAbi Mathew Roll No:1Roll No:1

CONTENTSCONTENTS

1.1. INTRODUCTIONINTRODUCTION2.2. BASIC CONCEPT OF CLOCKBASIC CONCEPT OF CLOCK3.3. WORKING OF SYNCHRONIZE CHIPSWORKING OF SYNCHRONIZE CHIPS4.4. ADVANTAGES & DISADVANTAGESADVANTAGES & DISADVANTAGES5.5. WORKING OF ASYNCHRONOUS CHIPSWORKING OF ASYNCHRONOUS CHIPS6.6. ADVANTAGES AND DISADVANTAGESADVANTAGES AND DISADVANTAGES7.7. TYPES OF ASYNCHRONOUS DESIGNTYPES OF ASYNCHRONOUS DESIGN8.8. COMPARISONCOMPARISON9.9. APPLICATIONS OF CLOCKLESS CHIPSAPPLICATIONS OF CLOCKLESS CHIPS10.10. BRIEF HISTORYBRIEF HISTORY11.11. CONCLUSIONCONCLUSION

INTODUCTIONINTODUCTION

CLOCKLESS CHIPS OR ASYNCHRONOUS CHIPS DON’T HAVE CLOCKLESS CHIPS OR ASYNCHRONOUS CHIPS DON’T HAVE A GLOBAL CLOCK.A GLOBAL CLOCK.

BUT THERE SHOULD BE SOME CONTROL MECHANISM BUT THERE SHOULD BE SOME CONTROL MECHANISM INSTEAD OF GLOBAL CLOCK.INSTEAD OF GLOBAL CLOCK.

CLOCKED CHIPS OR SYNCHRONOUS CHIPS HAVE A GLOBAL CLOCKED CHIPS OR SYNCHRONOUS CHIPS HAVE A GLOBAL CLOCK FOR CONTROLLING TIMING OF ENTIRE CHIP.CLOCK FOR CONTROLLING TIMING OF ENTIRE CHIP.

CLOCKLESS CHIPS HAVE SOME ADVANTAGES LIKE CLOCKLESS CHIPS HAVE SOME ADVANTAGES LIKE LOW LOW POWER CONSUMPTION,HIGH SPEED & LESS POWER CONSUMPTION,HIGH SPEED & LESS ELECTROMAGNETIC NOISEELECTROMAGNETIC NOISE OVER CLOCKED CHIP. OVER CLOCKED CHIP.

CONCEPT OF CLOCKCONCEPT OF CLOCK

Clock is a tiny crystal oscillator. Clock is a tiny crystal oscillator. Clock regulates the rate at which the Clock regulates the rate at which the instructions are executed. This rate is known instructions are executed. This rate is known as clock rate or clock speed. The clock speed as clock rate or clock speed. The clock speed can be expressed in terms of gigahertz and can be expressed in terms of gigahertz and megahertz.megahertz.

One advantage of clock is that One advantage of clock is that the clock signals to various components the clock signals to various components inside a chip when to input and output can be inside a chip when to input and output can be determined very easy.determined very easy.

Because of this clock there are Because of this clock there are some disadvantages like high power some disadvantages like high power consumption, low speed which can be consumption, low speed which can be overcome by clockless chips. overcome by clockless chips.

BLOCK DIAGRAM OF SYNCHRONOUS BLOCK DIAGRAM OF SYNCHRONOUS CIRCUITCIRCUIT

SYNCHRONOUS CHIPSSYNCHRONOUS CHIPS

ADVANTAGEADVANTAGE CHIP DESIGN VERY SIMPLE BECAUSE OF CHIP DESIGN VERY SIMPLE BECAUSE OF

CLOCKCLOCK

DISADVANTAGESDISADVANTAGES WASTAGE OF COMPUTATIONAL TIME WASTAGE OF COMPUTATIONAL TIME

AFFECTS THE SPEED OF CHIPAFFECTS THE SPEED OF CHIP HIGHER POWER CONSUMPTIONHIGHER POWER CONSUMPTION DESIGN OF COMPLEX CIRCUITS CANNOT BE DESIGN OF COMPLEX CIRCUITS CANNOT BE

DONE BECAUSE OF HIGH POWER DONE BECAUSE OF HIGH POWER CONSUMPTIONCONSUMPTION

BLOCK DIAGRAM OF BLOCK DIAGRAM OF ASYNCHRONOUS CHIPSASYNCHRONOUS CHIPS

MERITS OF MERITS OF ASYNCHRONOUS ASYNCHRONOUS CIRCUITS CIRCUITS

Increase in speed.Increase in speed. Reduced power consumption.Reduced power consumption. Less electromagnetic noise.Less electromagnetic noise. The ability to provide superior encryption.The ability to provide superior encryption. It is very flexible.It is very flexible. Replacing any part with a faster version improves Replacing any part with a faster version improves

the speed again and againthe speed again and again Designers have more freedom in choosing the Designers have more freedom in choosing the

system’s part.system’s part.

LIMITATIONS OF LIMITATIONS OF ASYNCHRONOUS CIRCUITSASYNCHRONOUS CIRCUITS

Design difficulties.Design difficulties. Lack of good tools.Lack of good tools. Testing difficulties.Testing difficulties.

TYPES OF TYPES OF IMPLEMENTATIONSIMPLEMENTATIONS

BOUNDED DELAY METHODBOUNDED DELAY METHOD DELAY INSENSITIVE METHODDELAY INSENSITIVE METHOD NULL CONVENTIONAL LOGIC(NCL) NULL CONVENTIONAL LOGIC(NCL)

SPEED COMPARISONSPEED COMPARISON

POWER COMPARISONPOWER COMPARISON

A BRIEF HISTORYA BRIEF HISTORY

A BRIEF HISTORY

COMPANY ACHIEVEMENTS GOALS

SUN MICROSYSTEMSPalo Alto, CA

Prototypes have demonstrated two to three times the speed ofStandard chips.

Gradually integrate “islands” of clockless logic into futureGenerations of microprocessors.

INTELSanta Clara, CA

Clockless prototype in 1997 ran three times faster than the conventional chip equivalent, on half the power.

Stay current with clockless R&D.

ASYNCHRONOUS DIGITAL DESIGNPasadena, CA

Founded by students of Caltech’s Alain Martin, who developed the First asynchronous microprocessor.

Produce chips for cell phones and other low-power communications devices; expected to announce plans byYear-end.

THESEUS LOGICMaitland, FL

Patented “null convention logic,” a way of letting clockless chips know when an operation isComplete.

License designs to manufacturers of smart cards and mobile devices; Motorola is a current customer.

PHILIPS ELECTRONICSEindhoven, Netherlands

Markets a clockless chip that gives its pagers up to twice the battery life of competitors.

Clockless chips for mobile devices and smart cards.

SELF-TIMED SOLUTIONS Manchester, England

Founded Steve Furber who has developed clockless chips for communications devices.

Clockless chips for smart cards.

The Caltech Asynchronous The Caltech Asynchronous Microprocessor is the world’s first Microprocessor is the world’s first asynchronous microprocessor asynchronous microprocessor (1989).(1989).

APPLICATIONSAPPLICATIONS

MOBILE ELECTRONICSMOBILE ELECTRONICS PERSONAL COMPUTERSPERSONAL COMPUTERS ENCRYPTION DEVICESENCRYPTION DEVICES

CONCLUSIONCONCLUSION

Clocks are getting faster, while chips are getting bigger, both Clocks are getting faster, while chips are getting bigger, both of which make clock distribution harder. Chips are also of which make clock distribution harder. Chips are also becoming more heterogeneous, with functions like memory becoming more heterogeneous, with functions like memory and network interfaces being considered, all of which and network interfaces being considered, all of which complicates the global timing analysis necessary for a complicates the global timing analysis necessary for a synchronous design. Finally, we are entering an age when synchronous design. Finally, we are entering an age when processors will be just about everywhere, and this will processors will be just about everywhere, and this will require very low power designs. It’s just not practical to require very low power designs. It’s just not practical to expect a clean, skew-free clock for every (say) piece of expect a clean, skew-free clock for every (say) piece of clothing with a processing element.clothing with a processing element.

But this can only happen if more focus, especially at the But this can only happen if more focus, especially at the university level, is given to asynchronous design. Most of university level, is given to asynchronous design. Most of today’s designers don’t understand it well enough to use it, today’s designers don’t understand it well enough to use it, and may even regard it with suspicion. It is certainly a and may even regard it with suspicion. It is certainly a challenge, but just as the software community is moving challenge, but just as the software community is moving towards more concurrency, the hardware community must towards more concurrency, the hardware community must move to incorporate asynchronous logic. move to incorporate asynchronous logic.

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