Joseph A. Elias, PhD 1

Class 07: Layout and Rules1. Introduction2. CMOS Assumptions3. Layout Layers for Transistor4. CMOS Formation - P+ diffusion5. CMOS Layout Example6. List of Rules to be Considered7. Layout and Cross Section - NMOS8. Lambda Based Rules 9. Reasons behind Rules: Contacts, Poly 10. Reasons behind Rules: Poly, Diff 11. Reasons behind Rules: Poly, Diff 12. Reasons behind Rules: NWELL Width, Space13. Reasons behind Rules: Poly 14. Reasons behind Rules: Diffusion and Tap, Width and Space 15. Reasons behind Rules: Diffusion and Tap, Enclosure-Spacing16. Reasons behind Rules: Illegal Example

Joseph A. Elias, PhD 2

Class 07: Layout and Rules

Assumptions for CMOS:•Substrate is p-type•Gate material is made of polysilicon•The process is single-well (nwell)•CMOS (complementary MOS) uses n- and p-type•CMOS process has a substrate (p-type) and

(usually) one well (nwell)

CMOS Assumptions

Joseph A. Elias, PhD 3

Class 07: Layout and RulesLayout Layers for Transistor

Drawn layers used to create a transistor:1) Well (aka substrate, tub, moat)• nmos are in pwell, pmos are in nwell

2) Diffusion (aka diff)•type of diffusion for Source/Drain set by well•defines active vs. isolation (or field) regions

3) Poly (aka gate)•gate material over diff defines W and L of transistor

4) Contact (aka ct)•defines how the source, drain, gate, and tap are contacted to higher levels

5) Tap•defines contact to substrate or well•heavily doped, same type as sub/well (i.e., n-type in nwell, p-type in p-substrate)

Joseph A. Elias, PhD 4

Class 07: Layout and RulesCMOS Formation - P+ diffusion (Martin p.45)

•Where and how many masks•N-type are in what?•P-type are in what?

nwell

Diff-tap

poly

Pdiff

Joseph A. Elias, PhD 5

Class 07: Layout and RulesCMOS Layout Example (Martin p.55)

•Where are the transistors?

Joseph A. Elias, PhD 6

Class 07: Layout and Rules

Layout Rules cover the following topics:•intra layer, that is, within one layer

•width, spacing•inter layer, that is, layer to layer

•spacing, enclosure, extension, overlap

Rules are going to be separated into the masks:•NWELL•DIFF/TAP (a.k.a. active, fom)•POLY•CONTACT•METAL

List of Rules to be Considered

Joseph A. Elias, PhD 7

Class 07: Layout and RulesLayout and Cross Section - NMOS (Martin p.50)

IsolationRegion

IsolationRegion

IsolationRegion

IsolationRegion

How many masks arein this picture?

Joseph A. Elias, PhD 8

Class 07: Layout and RulesLambda Based Rules (Martin p.50)

Based on the assumption of:λ half of the minimum feature size (a.k.a. ?)0.75λ worst case misalignment of a mask1.5λ worst case misalignment mask to mask

Gives the following rules for an NFET:2λ Minimum width of gate (a.k.a. channel ___)2λ Minimum width of contactλ Minimum enclosure of contact by diff2λ Minimum extension of poly beyond diff2λ Minimum space of contact to poly

And the following “derived” rules:4λ Minimum width of diff (a.k.a. channel ___)5λ Minimum length of diff

Joseph A. Elias, PhD 9

Class 07: Layout and RulesReasons behind Rules: Contacts, Poly (Martin p.51)

•If max misalignment is 1.5λ, and mincontact is 2λ, what is min contact togate spacing needed?

•If max misalignment is 1.5λ, and mincontact is 2λ, what is min enclosureof contact by diff?

•If max misalignment is 1.5λ, what ismin extension of poly beyond diff?

What layers are misaligned? What to what?

Joseph A. Elias, PhD 10

Class 07: Layout and RulesReasons behind Rules: Poly, Diff (Weste p.151)

•What are the problems with the layout on the right?•What would cause diff to grow or “bloat”•What would cause poly to shrink?

Grown diff

Shrunk poly

Joseph A. Elias, PhD 11

Class 07: Layout and Rules

•Where is thin oxide?•Where is isolation (a.k.a. _______ oxide)?

Reasons behind Rules: Poly, Diff (Weste p.151)

Joseph A. Elias, PhD 12

Class 07: Layout and RulesReasons behind Rules: NWELL Width, Space (Cypress)

nwell

Diff-tap

Minimum width1) Peak doping concentration needs to be repeatable,independent of width, or the lateral diffusion2) Photoresist must have a minimum opening toallow the implant. Since resist must be thick tostop high energy implant, aspect ratio considered.

Minimum space:1) Aspect ratio of resist width vs. length, and depth2) Punchthrough of two separate wells

space

width

Joseph A. Elias, PhD 13

Class 07: Layout and RulesReasons behind Rules: Poly (Martin p.44, Runyan c.5, Cypress)

nwell

Diff-tap

poly

width

space

Minimum width1) Resist critical dimension (CD) (related to what?)2) control of poly resistance (for resistors)

Minimum space:1) separation between transistors (shadowing)2) separation of features

Poly on field to diff or tap:•shadowing of implant

•Diff/Tap Contact to Poly on fieldpossible short

Joseph A. Elias, PhD 14

Class 07: Layout and RulesReasons behind Rules: Diffusion and Tap, Width and Space (Martin p.44, Cypress)

nwell

Diff-tap

poly

Pdiff Minimum width:1) Peak doping concentration needs to be repeatable,independent of width, or the lateral diffusion2) Photoresist must have a minimum opening toallow the implant.3) Must be wide enough to enclose a contact

Minimum space:1) Aspect ratio of resist width vs. length, and depth2) Punchthrough of two separate:•diff to diff•diff to tapdue to lateral diffusion of the implant and depletionregion variation with bias

Joseph A. Elias, PhD 15

Class 07: Layout and RulesReasons behind Rules: Diffusion and Tap, Enclosure-Spacing (Martin p.44, Cypress)

nwell

Diff-tap

poly

PdiffEnclosure of :•p diff by nwell due to need to isolate pdiff from psub•ntap by nwell for latchup and ESD concerns (good contact to the well)

Spacing of:•ndiff to nwell due to isolation, lateral diffusion•ptap to nwell due to isolation, lateral diffusion,but it is a reverse-biased junction

Joseph A. Elias, PhD 16

Class 07: Layout and RulesReasons behind Rules: Illegal Example (Weste p.151 , Cypress)

Poly cannot cross inner corners on diff

Besides catastrophic misalignments issues, what else would be difficult on this transistor?