CIDSP Assignment 5

8/12/2019 CIDSP Assignment 5

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In the Name Of God

Custom Implementationof DSP Systems

(Winter 2013)

Assignment 5 - Digital FIR FilterImplementation Using Xilinx ISE

Description5-1-

In this assignment, you will get familiar with FIR filter

structures and Xilinx ISE Core Generator and DSP48A1 slice inSpartan6 FPGAs. Nowadays, FPGAs have special functionblocks to implement signal processing systems as DSPfunctions and you should be able to use them for your goals.

Details5-2-

Equation (1) shows the basic equation for a single-channel FIR filter. Fig. 1 shows conventional tapped delay lineimplementation of FIR filters [1]:

(1) 1

0

)()()( N k

k

k n xk hn y

Fig. 1: Conventional Tapped Delay Line FIR Filter [1].

Due Date: April 06, 2013Teacher Assistant:

Siamack Beig [email protected]

Silicon Intelligent Lab oratorySILab
mailto:[email protected]:[email protected]:[email protected]


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Digital FIR Filter Implementation Using Xilinx ISE2

First of all, look at customized FIR filter structures for FPGAs in [1-2] and shortlycompare and report their architectures with respect to their features.

Then look at DSP48A1 user guide [2] and analyze its architecture and find and reportthe features you need to configure. Also, explain how to configure the slice to do your

desired function. Now, you should be able to show how to map a filter structure to one or more

DSP48A1 slices to have a FIR filter. In this assignment you will configure DSP48A1slice using Xilinx ISE Core Generator.

Step 1: In this step FIR filter will be designed by MATLAB and implemented entirelyusing Xilinx ISE Core Generator. Follow these steps:

a. Using MATLAB filter design and analysis tool (FDATool) achieve FIR filtercoefficients according to low-pass filter specifications in Assignment 3. Quantizethe filter coefficients with 16 bits and best-precision fractional length. Exportquantized coefficients to a file.

b. In order to import the coefficients youll need a .coe file with the format describedin [4]. Change the exported file to match this format.

c. Create a project in Xilinx ISE and use FIR compiler in IP cores from Xilinx CoreGenerator following this path: Digital Signal Processing -> Filters -> FIR Compiler.Import the coefficients and choose non-symmetric structure. You can observe thefrequency response of filter with FIR compiler tool according to your coefficients.Set sample period equal to clock cycle.

d. Repeat the previous step again and choose symmetric structure. Note thatTranspose Multiply Accumulate architecture doesnt support symmetricstructure. Use Systolic Multiply Accumulate structure for both structures.

e. Please note that you should configure filter options such as word length,coefficient width, and according to your FIR filter design in MATLAB. In theImplementation Details tab, observe the cycle latency which shows the delaybetween first input to the filter and first valid output. Report and compareestimated resource usage and cycle latency in symmetric and non-symmetricimplementations. Can you describe how clock latency is calculated? For input and

coefficient buffers (memory), FIR compiler gives you a few options such asdistributed buffers or a block of memory. It is important to know that a circularbuffer is a suitable option for FIR implementation.

Step 2: In this step you should instantiate just one DSP48A1 slice (in IP cores fromCore Generator follow this path: Basic Elements -> DSP48 Macro) to build previousfilter with your own design (symmetric structure). For this single-MAC structure,youll need to add a coefficient ROM, a circular data buffer (RAM), and a controller inVerilog to do the filtering operation (Hint: use pre-adder in DSP48A1). Fig. 2 showscorresponding top-level block diagram (with the exception of pre-adder which is not

included in DSP48 slice but youll use it in DSP48A1 ).


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Fig. 2: Symmetric Single-MAC FIR Filter [1].

Follow steps below:

a. Create a new project and add DSP48A1 slice using Core Generator. Report appliedsettings. Which instruction have you set for this macro?

b. For the memory elements use Block Memory (in IP cores from Core Generatorfollow this path: Memories & Storage Elements -> RAMs & ROMs -> Block MemoryGenerator). For the coefficients create a single port ROM module and initialize itwith your coefficients. Remember to change the exported coefficients fileaccording to the format specified in [5] and remove half of them (due tosymmetry). Select and report proper memory width and depth.

c. Select dual port RAM structure for the data RAM module with read-first property.Note that circular operation of data RAM is achieved via control unit and properselection of read addresses. Select and report proper memory width and depth.

d. Create a Verilog module for the control unit. It should control reset, read/writeaddress, and write enable signals for your IP cores. Sample code for a smallerblock will be provided.

e. Create a top-level Verilog module and instantiate previous modules to build thecomplete structure of FIR filter. View HDL Instantiation Template in the Designtab under Design Utilities would be useful.

Step 3: Using your controller in previous step, write a Verilog description for

Multiply-Accumulation (MAC) unit and use it to do the same operation of previousstep (symmetric structure). Synthesize the description and with schematic viewerobserve the mapping result and compare observation with previous step (Select top-level module -> Synthesize -> View Technology Schematic). Refer to [6,7] for help onVerilog hardware description language or just google it.

Step 4: Now the filters will be tested. Follow these steps:

a. Develop input file in text format with MATLAB. A .wav file with high-frequencynoise components will be given. Sampling rate and dynamic range are already setto proper values for this file. You can do quantization with MATLAB fixed-point

numeric object. Apply 16-bit quantization to inputs. Check these codes:


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b. Filter quantized input data (with filter function) and extract expected outputtext file. Use output bit-widths set in Xilinx ISE for output qantization. Rememberto use 16-bit quantized coefficients for filtering.

c. Develop a self-checking testbench able to read input samples from a text file,apply them to an instance of implemented structure, and compare the output with

expected output read from a text file. You can consider cycle delay by addinginitial zero values in expected output file. Your testbench should be changed a bitfor single-MAC structure. Sample code will be provided.

d. The testbench must create a text file which includes the simulation outputs.Import this file to MATLAB and plot output spectrum. You can use script below toimport text file to MATLAB (apply any change needed):

Test all the different structures youve developed. Show output data waveform alongwith expected value for one sample (Just for one of the simulations).Note that onlyinput signal and coefficients have been quantized in MATLAB and additions andmultiplications are done perfectly. Justify why we would expect exact match betweenMATLAB and ISE simulation outputs? (Hint: check internal bit-width of DSP48A1module)

Report Inclusion5-3- Write your observations in your report and explain all steps you did in your experiment,

expected comparisons and explanations. Report all the described and requested steps,any setting you change for IP cores, and answer all questions. Also append yourtestbench and m-files developed in MATLAB and clearly explain the final results andyour experiences.

Use reference standard format to write your reports.


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References5-4-

[1] Xilins, XtremeDSP for Virtex-4 FPGAs User Guide, May 15, 2008.[2] Xilinx, Spartan-6 FPGA DSP48A1 Slice User Guide, August 13, 2009.[3] Xilinx, ISE Core Generator User Guide, 2010.[4] LogiCORE IP FIR Compiler v5.0, Product Specification/ auth. Xilinx. - [s.l.]: Xilinx

Inc., 2011-DS534.[5] LogiCORE IP Block Memory Generator v4.2, Product Specification / auth. Xilinx. -

[s.l.]: Xilinx Inc., 2010 -DS512.[6] Wikipedia: The Free Encycloped ia, Verilog, [Retrieved: March 10, 2013],

Available: http://en.wikipedia.org/wiki/Verilog[7] D. K. Tala, Asic-World: Online knowledge source for hardware designers, 2013.

Available: http://www.asic-world.com/verilog/index.html.

Good Luck Happy Norouz!

Monday, March 11, 2013

CIDSP Assignment 5

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