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ChipSat – a System-on-a-chip for Small Satellite Data...
Transcript of ChipSat – a System-on-a-chip for Small Satellite Data...
ChipSat – a System-on-a-chip for Small Satellite Data Processing and Control
Architectural Study and FPGA Implementation
Dr Tanya VladimirovaLeader of the VLSI Systems Research Group
Surrey Space Centre, University of SurreyAlex da Silva Curiel
Head of R & DSurrey Satellite Technology Ltd.
Microelectronics Presentation Days, 4-5 February 2004, ESTEC
T.Vladimirova, A da Silva Curiel, MPD’04, ESTEC2
Outline! Single chip implementation of an on-board command and data
handling subsystem for a low-cost small satellite - mixed-mode ASIC. ! SoC design of an on-board computer for a small satellite - based on
integration of soft IP cores, compatible with the LEON microprocessor core.
! Downsized on-board computer implementation on a single programmable logic chip and a low-cost CCSDS-based communication system.
! Design and integration of a mathematical floating-point co-processor core, based on the CORDIC algorithm.
! Credit-card size on-board computer system using the SoC.! DMA controller and DDR SDRAM Controller core for the LEON CPU. ! Aspects of reconfigurability.
T.Vladimirova, A da Silva Curiel, MPD’04, ESTEC
SoC Research at SSC
SOC
Surrey Satellite Technology's (SSTL) On-Board Computer (OBC)Miniaturisation of the Small Satellite Platform
Credit-Card Size OBC System
1)
2)
Long-term
T.Vladimirova, A da Silva Curiel, MPD’04, ESTEC4
OBCDH Mixed-Mode SoCfor EO Small Satellite Missions
CAMERA
Wave le tCompre s s or Bit Sync Enc ode r
RS/Vite rbi Modulator
TX
FIR
De modulatorDe c ode r
Prog ramMe mory
DAC
FIR
FIR
UART PIO
NAVMAGX Y Z
Mag ne -torque rGPS
ADCSCo-Proc
NCO
Analog Mux
Slow ADCADC 20Ms ps
DS PCo-Proc
NCO
ADC ADC
FIR
RX
ROMBootload EDAC
Imag eMe mory
UART2 Channe ls CAN
GPT/WDT
SPI
PWM
Whe e l
DEBUG CAN I/ONETWORK EXPANSION
DMAMMU ICUSYNC/ASYCNRISC CORECACHE
Four subsystems:
• a 32-bit RISC processorcore modified for space use; • an image handlingsubsystem capable of capturing and compressing still or video-rate images; • a communication subsystem for the satellite uplink and downlink connection; and • a supporting peripheral subsystem.
5
System-on-a-Chip OBC
ESA Core
Debug
CAN Network >100Mbps
170MbyteMicrodrive
TX
TCSP1M*64SRAM
CAN Ethernet PHY
RX2RX1RX0
Linear Regulator
POR
+3.3V
EDACDECDED
ROM LUTBootstrap
AMBA APB
CANInterface
AMBA AHB
LEON Sparc V8 CORDICCoprocessor
AMBA AHB
AMBA AHB
HDLC TXController
AMBA AHB
HDLC RXController
FIFO
AMBA AHB
HDLC RXController
FIFO
AMBA AHB
HDLC RXController
FIFO
System Bus
CF+ I/FTrue IDE
FIFO
Ethernet MAC
UART
AMBA AHB
PIO
FIFO
AMBA AHB
+2.5V +3.3V
CLK CLK CLK CLK
XILINX Virtex XCV800 FPGA
SP
T.Vladimirova, A da Silva Curiel, MPD’04, ESTEC6
Downsized SoC - FPGA Implementation
LEONIU
AMBA AHBAHB
CONTROLLER
MEMORYCONTROLLER
AHB/APBBRIDGE
AMBA CANCONTROLLER
ABUS(19:1)
CAN TX
CAN RXSN65HVD2
32
EDAC(16,8)
DATA MEMORY512K *16 BITS
PARITYMEMORY
512K *16 BITS
RIGHT BANKLEFT BANK
DBUS
VIRTEX V800VIRTEX V800VIRTEX V800VIRTEX V800
UART A
UART B
CANTRANSCEIVER
MAX232CPE
SERIAL PORTTRANSCEIVER
CPLDXC95108
232ACBH
PCPCPCPC
COM 1 COM 2
CommunicationSoftware(Between PCand the Board):
Tera TermXESS GXLoad
SCOPE
Parallel Port
Integration of CAN, EDAC and LEON
T.Vladimirova, A da Silva Curiel, MPD’04, ESTEC7
FPGA Chip Usage
! Synthesis Tool: Synplify 6.0 +! LEON IP core + CAN IP core + EDAC IP core => 43% of XCV800! QPRO XILINX Virtex family of radiation hardened FPGAs:
– qualified for space use– guaranteed total ionising dose to 100K Rad (si)– latch-up immune to LET > 125 Mev cm2/mg @ +125 oC
0.010.04
0.04
0.430.48 LEON1- 2.4.0 + CAN + EDAC
FIFO
HDLC
IDE
IDLE
Virtex XCV-800 FPGA
Based on Synthesis Results
UNUSED
T.Vladimirova, A da Silva Curiel, MPD’04, ESTEC8
A CCSDS-Based Communication System for a Single-Chip OBC
" Implementation of a simplified yet RELIABLE Consultative Committee of Space Data Systems (CCSDS) TLM & TC space communication system satisfying the needs of a single chip on-board computer (OBC) of a small satellite.
" Simulation of the operation of the software on a single-chip OBC prototype.
SoC OBC
TC
TLM
GROUND SEGMENT
SPACECRAFT SEGMENT
T.Vladimirova, A da Silva Curiel, MPD’04, ESTEC9
CCSDS! Standard space industry communication protocol. ! Employed on numerous missions ranging from relatively simple low
earth missions to deep space probes.! Could lead to spacecraft interoperability, re-usable systems and
mission cross support – not just for in-house missions but across the CCSDS space agencies members.
Tx_Tc
TLM_Tx
FOP
TLM_Rx
Tc_Rx
FARM
TLMframes
CLTUs
CCSDSGround
CCSDSSpacecraft
R-SEncoder
R-SDecoder
TLMframes
Frame Acceptance and Report Mechanism
Frame Operation Protocol
Tx_Tc
TLM_Tx
FOP
TLM_Rx
Tc_Rx
FARM
TLMframes
CLTUs
CCSDSGround
CCSDSSpacecraft
R-SEncoder
R-SDecoder
TLMframes
Frame Acceptance and Report Mechanism
Frame Operation Protocol
Structure and Interfaces of the CCSDS Software Package
T.Vladimirova, A da Silva Curiel, MPD’04, ESTEC10
Simulation SchemeCCSDSCCSDSCCSDSCCSDSTC_TxTC_TxTC_TxTC_Tx
CCSDSCCSDSCCSDSCCSDSTLM_RxTLM_RxTLM_RxTLM_RxFOPFOPFOPFOP
Serial PortSerial PortSerial PortSerial Port
UARTUARTUARTUART
CCSDSCCSDSCCSDSCCSDSTC_RxTC_RxTC_RxTC_Rx
FARMFARMFARMFARM
CAN_Node1CAN_Node1CAN_Node1CAN_Node1(CAN_Core)(CAN_Core)(CAN_Core)(CAN_Core)
CAN_Node2CAN_Node2CAN_Node2CAN_Node2(CAN_Card)(CAN_Card)(CAN_Card)(CAN_Card)
R-SR-SR-SR-SDecoderDecoderDecoderDecoder
CCSDSCCSDSCCSDSCCSDSTLM_TxTLM_TxTLM_TxTLM_Tx
R-SR-SR-SR-SEncoderEncoderEncoderEncoder
CLTU
CLCWTLM_Frames
TC
TC
TLM
Space SegmentSpace SegmentSpace SegmentSpace Segment(XESS Prototyping Board)(XESS Prototyping Board)(XESS Prototyping Board)(XESS Prototyping Board)
Ground SegmentGround SegmentGround SegmentGround Segment(PC)(PC)(PC)(PC)
Single Chip OBCSingle Chip OBCSingle Chip OBCSingle Chip OBC
T.Vladimirova, A da Silva Curiel, MPD’04, ESTEC11
Downsized FPGA ImplementationSummary
! Processor - LEON 2-1.0.2a VHDL IP core (SPARC V8) (ESA)" Working Frequency – 25 MHz" UART Baud Rate – 38,400 bps" Internal S-Record Boot Loader
! On-Board Network (Node 1) - HurriCANe VHDL IP core (ESA)" Baud Rate: 312,500 bps
! EDAC – EDAC VHDL IP core (SSTL)" Double-bit correcting Quasi-Cyclic (16,8) shortened EDAC code
! Prototyping Board - XESS XSV800 (Xilinx Virtex XCV800 FPGA)" Up to 100 MHz programmable oscillator" 16M Bits SRAM (two banks - 512K x 16)" 16M Bits flash RAM
! On-Board Application Program – S-Record File" 160K Bytes (CCSDS_SC Software Package)
T.Vladimirova, A da Silva Curiel, MPD’04, ESTEC12
The CORDIC Algorithm1
0
n
i ii
θ δ α−
=
=∑ { }1, 1iδ ∈ −
1 2 ii i i ix x m y δ −+ = −
1 2 ii i i iy y x δ −+ = +
1i i i iz z δ α+ = −
( )( ) 4141
11tanh2lncoshsinhexp
coshsinhtanhcossintan
22
1
−=+=−=
−=+==+=
==
−
wyandwxwhereyxw
wyandwxwherexywzzz
zzzzz
0
0
n -1
K-1 = 1 / ΠΠΠΠ (1 - 2-2i)1/2 for n iterationsi=0
n -1
K1 = 1 / ΠΠΠΠ (1 + 2-2i)1/2 for n iterationsi=0
K1 (x cos z � y sin z)
K1 (y cos z + x sin z)
0
CIRCULAR (m=1), δδδδ = sgn z
x
y
z
x
y
z
CIRCULAR (m=1), δδδδ = - sgn y
x
y + xz
0
LINEAR (m=0), δδδδ = sgn z LINEAR (m=0), δδδδ = - sgn y
K-1 (x cosh z � y sinh z)
K-1 (y cosh z + x sinh z)
0
HYPERBOLIC (m=-1), δδδδ = sgn z HYPERBOLIC (m=-1), δδδδ = - sgn y
K1 (x2 + y2)1/2
0
z + tan-1(y/x)
0
z + y/x
K-1 (x2 - y2)1/2
z + tanh-1(y/x)
x
y
z
x
y
z
x
y
z
x
y
z
x
y
z
x
y
z
x
y
z
x
y
z
x
y
z
x
y
z
CORDIC equations:
CORDIC modes
)( ii zsign=δ 1,...,2,1,0 −= ni
[ ]Tyx 00,
Composite functions:
T.Vladimirova, A da Silva Curiel, MPD’04, ESTEC13
CORDIC Algorithm – Domain ExtensionIdenitity Domain
{ sin D if Q mod 4 = 0 }sin(Q 90 + D) = { cos D if Q mod 4 = 1 }
{ -sin D if Q mod 4 = 2 }{ -cos D if Q mod 4 = 3 }
|D| < 90
{ cos D if Q mod 4 = 0 }cos(Q 90 + D) = { -sin D if Q mod 4 = 1 }
{ -cos D if Q mod 4 = 2 }{ sin D if Q mod 4 = 3 }
|D| < 90
tan(Q 90 + D) = sin(Q 90 + D) / cos(Q 90 + D) |D| < 90
tan-1(1/y) = 90 � tan-1 (y) |y| < 1
sinh(Q loge 2 + D) = (2Q/2)[cosh D + sinh D � 2-2Q(cosh D � sinh D)] |D| < loge 2
cosh(Q loge 2 + D) = (2Q /2)[cosh D + sinh D + 2-2Q(cosh D � sinh D)] |D| < loge 2
tanh(Q loge 2 + D) = sinh(Q loge 2 + D) / cosh(Q loge 2 + D) |D| < loge 2
tanh-1(1 � M2-E) = tanh-1(T) + (E/2) loge 2where T = (2 � M � M2-E) / (2 + M � M2-E)
0.17 < T < 0.75for 0.5 ≤≤≤≤ M < 1, E ≥≥≥≥1
exp(Q loge 2 + D) = 2Q(cosh D + sinh D) |D| < loge 2
loge (M2E) = loge M + E loge 2 0.5 ≤≤≤≤ M < 1.0
sqrt(M2E) ={ 2E/2 sqrt(M) if E mod 2 = 0 }{ 2(E+1)/2 sqrt (M/2) if E mod 2 = 1 }
{0.5 ≤≤≤≤ M < 1.0{0.25≤≤≤≤ M/2 < 0.5
(Mx2Ex)(Mz2
Ez) = (MxMz)2Ex + Ez 0.5 ≤≤≤≤ Mz < 1.0
(My2Ey) / (Mx2
Ex) = (My / 2Mx)2Ey � Ex + 1 0.25 ≤≤≤≤ My / 2Mx < 1.0
T.Vladimirova, A da Silva Curiel, MPD’04, ESTEC14
32-Bit Floating Point Co-Processor Design
Function Group Number
sin 000 000
cos 000 001tan 000 010sinh 000 100
cosh 000 101tanh 000 110
exp 000 111
sin-1 001 000cos-1 001 010
tan-1 010 000
tanh-1 011 000
sqrt 100 000
multiplication 101 000
division 110 000
loge 111 000
Sign bit Exponent Mantissa Number represented
0 0 0 Zero
0 255 0 +∞
1 255 0 -∞
0 or 1 255 Not 0 Not-a-number (NaN)
Prescale000
Prescale001
CORDICModule
Postscale000
Postscale001
FiniteState
MachineGO Done
… …
Top-Level Block-Diagram
IEEE 754 standard compliance
Grouping of Functions
4 arithmetic + 13 elementary functions
T.Vladimirova, A da Silva Curiel, MPD’04, ESTEC15
CP Integration with LEON SPARC V8The LEON IP core
The Real Time Executive for Multiprocessor Systems (RTEMS) is an open source real-time operating system (RTOS), which provides a high performance environment for embedded systems
LEON with RTOS RTEMS
T.Vladimirova, A da Silva Curiel, MPD’04, ESTEC16
Interface with the LEON IP Core
Command 31-30 29-25 24-19 18-14 13-5 4-0
cpop1 10 rd 110110 rs1 opc rs2
cpop2 10 rd 110111 rs1 opc rs2
Math Library Example - module 7 of the Whetstone program
Format of the co-processor operate instructionsEnabling co-processor support in a user program
T.Vladimirova, A da Silva Curiel, MPD’04, ESTEC18
Co-processor Summary! A 32-bit maths co-processor VHDL core is developed for a SoC OBC
based on the LEON SPARC V8 IP core -– aimed at speeding up computationally intensive on-board
applications, traditionally implemented in software, e.g ADCS.! The co-processor is fully compliant with the IEEE 754 floating-point
standard and implements 17 functions:– add, sub, mul, div, + sqrt, + sin, cos, tan + sin-1, cos-1, tan-1 +
sinh, cosh, tanh, + tanh-1 + exp, ln.! The co-processor occupies half the size of a Virtex XCV800 chip.! The co-processor operates at 2.5MHz, when integrated with the LEON
IP core, at 25 MHz - when standalone.! The co-processor accelerates execution of floating-point calculations
on the Leon processor: – the Whetstone benchmark runs 70% faster on Leon+RTEMS+CP
compared with the time it takes on Leon+RTEMS.
T.Vladimirova, A da Silva Curiel, MPD’04, ESTEC19
Credit-Card Size OBC System
FPGA
1.5V Regulator
PROM
SDRAM16MByte
85
54
SpaceWire Connector
CAN Connector
Dual CAN transceiverJTAG connector
Power/PPS connectorHDLC/RS422 Connector
SDRAM16MByte
SDRAM16MByte
SDRAM16MByte
Requirements:Power consumption: 2WMass: 50gSize: 85mm ×××× 54mmTemperature range:
–20°C to +50°C
Components:FPGAMemoryClock GeneratorPower SupplyTransceivers
Xilinx XQR2V30003 x 106 sys. gates; 1.5 V
Actel RTAX2000S2 x 106 sys. gates; 1.5 V
Candidate FPGAs:
T.Vladimirova, A da Silva Curiel, MPD’04, ESTEC20
Onboard Computer
System on Chip / FPGA
FPU
Boot PROM
EDACController
HDLC1Up/Downlink
HDLC0Up/DownlinkSpaceWireRS422
1.5V Linear Regulator
+3.3V
+3.3V +1.5V
CLK Generator
Configuration PROM
JTAG
Jumper
PPS in PPS out
DMAController
HDLCController
CANController
SpaceWireController
HDLCController
CANSwitch
Dual CAN transceiver
CAN0 CAN1
MemoryController
Timers IRQCtrl
UART
AHB/APB Bridge
AMBA AHB
AMBA APB
Leon CPUI/O port
16MbyteSDRAM
16MbyteSDRAM
Data Memory Parity Memory
16MbyteSDRAM
16MbyteSDRAM
32bit Data bus
Address/Control bus
IP CoresLEON-2 CPU v.1.0.13Math Co-processor
DMA ControllerCAN Controller/Switch
EDAC UnitHDLC Interface RS422 Interface
SpaceWire InterfaceBoot Loader
Credit-Card SizeOBC System
Detailed Diagram
T.Vladimirova, A da Silva Curiel, MPD’04, ESTEC21
DMA Controller DMA Controller
Priority Arbiter
Channel 0DACK0
EOP0
DREQ0
APB Slave Interface
General Register
DACK1EOP1
DREQ1
DACKnEOPn
DREQn
AMBA AHB Master Interface
DMA Engine
IRQ
AMBA APB Slave Interface
Channel n
Channel 1
Mul
tiple
xer
Virtex-II V2MB1000 development board from Memec:•XC2V1000-4FG456C FPGA• 32 MByte DDR SDRAM (MT46V16M16TG-75 IC from Micron)• 24 & 100 MHz clock generator
HGRANT
HREADY
HRDATA[M-1:0]
HRESP
HCACHE
HBUSREQ
HLOCK
HTANS
HADDR[31:0]
HWDATA[M-1:0]
HWRITE
HSIZE[2:0]
HBURST[2:0]
HPROT[3:0]
PSEL
PENABLE
PADDR[31:0]
PWRITE
PWDATA[31:0]
PRDATA[31:0]
DMA controller
AM
BA
AH
B M
aste
r int
erfa
ce
AM
BA
APB
Sla
ve in
terfa
ce
DREQ[N-1:0]
DACK[N-1:0]
EOP[30:0]
IRQ
RESETn
CLK
N - number of channelsM - width of AMBA AHB
T.Vladimirova, A da Silva Curiel, MPD’04, ESTEC22
DMA Controller - Features
! Variable number of independent DMA channels (1 up to 32) -priority of the channels is fix; Channel 0 has the highest priority.
! Supports single transfer and block transfer! Supports burst transfer with programmable burst length to maximize
data bandwidth! Programmable data width! Supports both hardware initiated transfer and software initiated
transfer! Several transfer types:
• Peripheral →→→→ Memory• Memory →→→→ Peripheral• Peripheral →→→→ Peripheral• Memory →→→→ Memory
! Interrupt generation on transfer completion or on transfer error! Handles wait state insertion by any slave devices! Supports all slave device responses: OKAY, RETRY, SPLIT, and
ERROR! Designed for the AMBA® 2.0 Bus.
T.Vladimirova, A da Silva Curiel, MPD’04, ESTEC23
DMA Controller Integration Test
System on Chip
UARTDMA Controller
MemoryController
CPU
DREQ
AMBA AHB Bus
RS232
T.Vladimirova, A da Silva Curiel, MPD’04, ESTEC24
LEON-2 IP Core and DDR SDRAM
The memory controller integrated in the LEON core does not support DDR SDRAM memory.
DDR SDRAM controller from Array Electronics, Germany(OpenIPCore General Public License) • Integrated bank management; it does not need the CPU to initialise the memory IC.•Adjusted to the LEON memory interface via addition of a glue logic unit.
System on Chip
LEON core
DDR SDRAM controller
DDR SDRAM Bus
User Switch interface
CLK Resetn
UART1 UART2 DSU UART
7-Segment LED Display interface
DCM
IO
RAM CLKCPU CLK
T.Vladimirova, A da Silva Curiel, MPD’04, ESTEC25
DDR SDRAM Controller
The glue logic output signals to the memory controller are synchronous with a 100 MHz clock. The glue logic output signals to the LEON CPU are synchronous with a 24 MHz clock. Two finite state machines are included in the glue logic block to match the frequencies.
T.Vladimirova, A da Silva Curiel, MPD’04, ESTEC26
Reconfigurability
Server
Client 1 Client 2 Client n
Request
Respond
TCP/IP
On-Board SoCIn Virtex FPGA
TCP/IP Server
XHWIF Server
TCP/IP Client
XHWIF Net
TCP/IP Client
XHWIF Net
TCP/IP Client
XHWIF Net
Remote Hardware Configuration
! The SoC-OBC can be reconfigured remotely if implemented on a VirtexFPGA.
! The Java Runtime Environment JBits is used communicating with the ground station via Internet protocols (TCP/IP).
! The RSC-OBC acts as an equivalent to an application server allowing client Java programs to run on the server and use its resource.
06/02/2004T.Vladimirova, A da Silva Curiel, MPD’04, ESTEC
27
Summary of SoC Research! High-density FPGAs can serve as an appropriate medium for SoC
implementation.! A downsized configuration of the single-chip OBC consisting of
LEON+CAN+EDAC has been implemented on a Virtex FPGA.! The developed CCSDS s/w + single-chip OBC + a thin-layer h/w interface
can provide a cost-effective and flexible communication solution for low-cost small satellites.
! A 32-bit floating-point co-processor based on the CORDIC algorithm which is IEEE 754 compliant has been developed and integrated with the LEON CPU: " 17 functions - add, sub, mul and div + 13 elementary functions
! A credit-card size OBC system based on the SoC OBC has been specified.
! A 32-channel DMA controller has been designed and incorporated with the LEON CPU together with a DDR SDRAM controller.
! A feasibility study on the SoC remote reconfigurability via TCP/IP protocols using JBits is in progress.
! Specialised peripheral cores e.g, an image compression core, are in a process of development.
T.Vladimirova, A da Silva Curiel, MPD’04, ESTEC28
Acknowledgements! The research results included in this presentation would not have
been achieved without the financial support received from the following sponsors:– ESA– SSTL
! Thanks are due to the following individuals for their help and encouragement:– Hans Tiggeler – Saros Technology Ltd.– Sandi Habinc - Gaisler Research– Roland Weigand - ESA
! The following past and present students have contributed to thisresearch during their project work at the Surrey Space Centre, University of Surrey: – Jackie Rutter– Daixun Zheng– David Eamey– Sven Keller– Michael Meier
T.Vladimirova, A da Silva Curiel, MPD’04, ESTEC29
References
1. H.Tiggeler, T.Vladimirova, J.Gaisler. “Designing a System-on-a-chip for Small Satellite Data Processing and Control”, IIE Magazine on Engineering Technology, vol. 4, N 6, June 2001, pp. 38-42
2. I.Rutter, T.Vladimirova, H.Tiggeler. “A CCSDS Software System for a Single-Chip On-Board Computer of a Small Satellite” – 15th AIAA/Utah Sate University Conference on Small Satellites, Utah, USA, August 13-16 2001, SSC01-VI-4
3. D. Zheng, T. Vladimirova and Prof Sir M. Sweeting. “A CCSDS-Based Communication System for Single Chip On-Board Computer”, MAPLD’02 Conference, D5, September 2002
4. D.Zheng, T.Vladimirova, H.Tiggeler, M.N.Sweeting. “Reconfigurable Single-Chip On-Board Computer for a Small Satellite”, 52nd International Astronautical Congress, 2001, IAF-01-U3.09.
5. T. Vladimirova, D. Eamey, S. Keller and Prof Sir M. Sweeting. “Floating-Point Mathematical Co-Processor for a Single-Chip On-Board Computer”, MAPLD’03 Conference, D5, September 2003
6. T. Vladimirova, Prof Sir M. Sweeting. “System-on-a-Chip Development for Small Satellite Onboard Data Handling,” JACIC, AIAA, January 2004
7. M. Meier. “Credit-Card Size Onboard Computer”, Internal Report, SSC/SSTL, September 2003
8. M. Meier. “DMA Controller for a SoC OBC”, Internal Report, SSC/SSTL, 2003