Chip package system apache - publish version
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May 4, 2011 1 Chip-Package-System (CPS) Co-Design Verification Chipex 2011 Track D: Power Management & Signal Integrity Ronen Stilkol, Apache Design Solutions
Transcript of Chip package system apache - publish version
May 4, 2011 1
Chip-Package-System (CPS)Co-Design Verification
Chipex 2011 Track D: Power Management & Signal Integrity
Ronen Stilkol, Apache Design Solutions
May 4, 2011 2
What is Chip-Package-System?
Chip-Package-System Sign-offPower, Thermal, Timing, EMI
May 4, 2011 3
Chip-Package-System (CPS)
Board
vdd_d
gnd_d
vdd_a
gnd_a
May 4, 2011 4
Technology Impact on CPS Issues
45nm65nm
Decap size
Rela
tive
Dec
ap
Rela
tive
ESR
Decap is less effective at advanced technologiesAdvanced technologies show more Di/Dt
0 10 20 30 40 50 60 700
102030405060708090
0
0.5
1
1.5
2
2.5
3
0 4 8 12 16 200
0.5
1
1.5
2
Buffer size
Buffe
r di/
dt R
atio
28nm : 65nm
45nm : 65nm
65nm vs 45nm 45nm ,28nm vs 65nm
One die modeling is critical for CPS
May 4, 2011 5
Concurrent Chip-Package-System Design
Board
Package
Traditional view of chip is black box or simplistic modelDetail Model of Chip allow concurrent system-package-die SI&PI analysisImpedance Analysis of entire system level PDN network
Zin
Transient Analysis of entire system level PDN networkSignal Integrity analysis of high speed signals
May 4, 2011 6
Chip-Package-System (CPS)
BoardBoardBoardBoardBoardBoard
VRM
Package
CHIP 2
1.8V
1.2V
May 4, 2011 7
Chip-Package-System (CPS)
BoardBoard
VRM
CHIP 2
1.8V
1.2V
Package
May 4, 2011 8
Chip-Package-System (CPS)
BoardBoard
VRM
1.8V
1.2V
Package
CHIP 2
Chip Power Model + Package Extraction
+ PCB/Board Extraction
EMI NoisePower Integrity
Thermal IntegrityPower Delivery Network Impedance
Cost Control (low cost market and/or high volume)
May 4, 2011 9
Chip-Package-System (CPS)
With Package ModelWithout Package ModelRed: Chip + Pkg analysisGreen: Chip + Pkg + PCB analysis
AC Analysis Dynamic Voltage Drop
Models of the Chip, Package and PCB are necessary for an accurate result.
May 4, 2011 10
Chip-Package-System (CPS)
2nd harmonic 5th harmonic
Chip EmissionsEMI/EMC Analysis
Package/PCB EMI Map
SSO Timing Analysis
Necessary to model the noise
source (Chip) and propagation
medium (Package/PCB)
May 4, 2011 11
C4 PG Bump
L Metal
C MetalOn die Decap
Leaf TxR Metal R Pkg L PCB R PCB
C Pkg On Boarddecap
VRMGlobal PDNview
C4 PG Bump
L Metal
C MetalOn die Decap
Leaf TxR Metal PCB/Pkg RLC,
S parameterSoC Designers
view
C4 PG Bump
R Pkg L PCB R PCB
C Pkg On Boarddecap
CPMChip Power Model
VRMPCB Designers
view
Only Common reference point
Model-Based CPS Convergence
May 4, 2011 12
Chip on-die Power Grid RLC
Transistor current/cap/ESR
Multi-domain, distributed model
DC to multi-GHz validity
Advanced chip excitation modes
Full chip correlation
Model creation
Package/BoardModel
Chip PowerModel
ASICVendors
Two sides, co-verification
System Houses
Chip Power Model (CPM™)
May 4, 2011 13
Static (Iavg, R)Frequency domain (RLC)Time-domain (I(t), RLC)
Modes
CHIP DATA
Layout(Early to Sign-off)
Library
CHIP ANALYSIS
Static Dynamic VCD
Dynamic VectorLess
Chip Power Model
Chip Power Model (CPM)
May 4, 2011 14
Chip Power Model (CPM)
Pads/bumps (Power & Ground) need to be associated to its corresponding
Chip PDN RLC Physical model of chip layout
Transistor/cell current /cap/ESR Electrical model of chip layout
PCB + Package
May 4, 2011 15
Chip Power Model (CPM)
1. Each port (or bump) reflects the current flow
associated with that port (or bump) reflecting
the on-die activity
2. Parasitics are associated with every port (or
bump)
3. Each port (or bump) are coupled with every
other port
Active Current SignaturePassive RC Values
May 4, 2011 16
Detailed Chip Power Model Advantage
Traditional Die Model
Design
Layout
Chip Power Model
RLC reduction: billions of parasitics to thousands of Spice elements
Distributed with full couplings
Detailed Chip Power Model
Library
Chip
Cur
rent
Chip
Par
asiti
cs
Traditional Die Model
Single Lumped Model
Detailed Chip Power Model
May 4, 2011 17
Chip Power Model : Parasitic Model Benefits
Traditional approaches to modeling the chip parasitics:
Spreadsheet based
Hand-calculated estimates
Limited coverage
Poor accuracy, especially for large, multi-domain designs
CPM advantages
Accurate broadband response over wide frequency range
Captures all chip capacitive effects (PDN, device, signal net)
Resistive and inductive shielding of die capacitances
Spatially accurate
May 4, 2011 18
Top Level500MHz
Chip Power Model – Distribution Matters
CPU1.6Ghz
mem
mem
mem
PLLvictim
Ground C4 Bumps
Bumps above CPU
Bumps above Top
Bumps above Mem
+ Rdie/Cdie
+ Rdie/Cdie
+ Rdie/Cdie
Top Level
ARM
mem
mem
mem
PLL
Top Level
ARM
mem
mem
mem
PLL
Top Level
ARM
mem
mem
mem
PLL
Top Level
ARM
mem
memm
em
PLL
Which ground planefits your request best?
May 4, 2011 19
Noise in Power Delivery Network (PDN)
•4 major noise signatures in PDN
Very low frequency noise:kHz range
Voltage RegulatorBoard L,C
Global Impact
Low frequency noise:MHz range
BoardSocket
PackageGlobal
Mid frequency noise:10’s MHz range
PackageDie
Global
High frequency noise:10’s GHz range
DieLocal
Low Mid High
Chip-Package-Board PDN simulation
Decaps ~ uF Decaps ~ nF Decap ~0.1pF
May 4, 2011 20
Chip Power Model - Resonance Aware–Default chip simulation is activating all the clock frequencies–In Resonance Aware, CPM should focus on a specific stressing
frequency
time
Digital Current
Cons
tant
Po
wer
Mod
e
time
Digital Current
Reso
nanc
e Aw
are
Mod
e
FFT
FFT
freq
dB
freq
dB
More energy aroundResonance frequency
Distributed energybetween frequencies
May 4, 2011 21
When to Consider Resonance?Small Die
(4mm x 4mm)Medium Die
(7mm x 7mm)Large Die
(10mm x 10mm)
QFP (5n - 10n)
BGA (0.5n - 2n)
FCBGA (50p – 0.3n)
Die cap/unit area can be used to estimate total die capacitance
diepkgCLf
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May 4, 2011 22
Chip-Package-System Summary
Chip, package and system integrated Power and Signal integrity simulations,
are essential for accurate modeling of the design using advanced processes
• Chip, package co-verification is done on the chip side when a package model is
integrated into the die simulation
• Chip, package co-verification is done on the package and system side using a detailed
chip model that is extracted from the complete die spatial and electrical data
• Early analysis model of the chip is required for early convergence of the package and
system design
• Chip Power Model includes the required features to support : VRM, jitter, impedance,
transient, and resonance analysis
May 4, 2011 23
Thank You
