CHARACTERIZATION OF DIGITAL

PHASE-LOCKED LOOPS

by

SRI KIRAN V. S. VEPA. B.E.

A THESIS

IN

ELECTRICAL ENGINEERING

Submitted lo the Graduate Faculty of Texas Tech University in

Partial Fulfillment of the Requirements for

the Degree of

MASTER OF SCIENCE

IN

ELECTRICAL ENGINEERING

Approved

May, 2003

ACKNOWLEDGEMENTS

I consider this as a privilege to thank the people who have made this thesis

possible.

I am extremely indebted to my thesis advisor. Dr. Micheal Parten, who provided

me clear direction and sound advice. He constantly monitored my progress and provided

me with lots and lots of good ideas throughout the time I worked on my thesis. Needless

to say, I would have been lost without him.

I also thank Dr. Bredeson, Chairman of the Department of Electrical Engineering,

for being an important part of my thesis committee. I also thank the Department of

Electrical Engineering for the excellent computer lab facility. I also express my sincere

gratitude for the Texas Tech University libraries for providing access to all the necessary

literature.

Last, but not the least, I wish to thank my parents and all my friends for providing

emotional support, encouragement and caring during the difficult times.

TABLE OF CONTENTS

ACKNOWLEDGEMENTS ii

ABSTRACT v

LIST OF TABLES vi

LIST OF nOURES vii

CHAPTER

1 INTRODUCTION 1

2 PHASE LOCKED LOOP BASICS 3

2.1 Operating Principles of the PLL 3

2.2 Overview of the Funclional Blocks 4

2.2.1 Phase Detector 4

2.2.2 Voltage-Controlled Oscillator 8

2.2.3 Loop Filter 11

2.3 PLL Bandwidth 11

2.4 Some Common Terms Encountered in PLL Literature 13

2.5 Design Problem 16

3 DIGITAL PHASE-LOCKED LOOP: DESCRIPTION OF COMPONENTS 18

3.1 Phase Detector 18

3.1.1 Phase/Fr«quency Detector 19

3.2 Charge Pump 23

3.3 Dynamics of the Charge Pump PLL 25

3.4 Voltage-Controlled Oscillator 32

3.4.1 Ring Oscillator 33

3.4.2 Current Starved Inverter 35

4 DESIGN OF DPLL CIRCUrP 37

4.1 Phase Detector 37

4.2 Charge Pump/Loop filter 42

4.2.1 Charge Pump 43

4.2.2 Loop Filter 48

4.3 Voltage-Controlled Oscillator 48

4.4 PLL Design 50

5 PLL SIMULATIONS AND RESULTS 51

5.1 Phase/Fr«quency Detector 51

5.1.1 Phase Lag 52

5.1.2 Phase Lead 56

5.1.3 Frequency Lag 57

5.1.4 Frequency Lead 58

5.2 PFD Transfer Characteristic 59

5.3 Charge pump/Loop Filter 60

5.3.1 Phase/Frequency Lag 61

5.3.2 Phase/Frequency Lead 62

5.4 Transfer Characteristic of the Charge Pump/Loop Filter Combination 63

5.5 Voltage-Controlled Oscillator 65

5.6 PLL Performance 67

5.7 Conclusion 76

6 CONCLUSIONS AND FUTURE WORK 77

REFERENCES 79

ABSTRACT

Phase-locked loops are a relatively new class of circuits used primarily tn

communication applications. The capture range of a phase-locked loop is a critical

parameter because it trades directly with the loop bandwidth. Different architectures for

the phase-locked loop (PLL) have been proposed which can broaden the capture range

(1-3]. However, in most of the research, very little emphasis was made on studying the

exact dependence of the capture range on the different circuit parameters, which define

the individual components of a phase-locked loop. The effect of these parameters, for

instance, the W/L ratio of the transistors, can be prominent. This thesis is aimed at

designing a circuit for a digital phase locked loop, characterizing the components and

discussing a method of estimating the capture range. This circuit can act as a starting

point in solving the above mentioned problem. The next step would be to observe the

dependence of capture range on circuit parameters.

LIST OF TABLES

4.1 Truth Table for 2-inpul NAND Gate

5.1 Range of Frequencies for which Capture Occurs

LIST OF FIGURES

2.1 A Basic Phase Locked Loop 3

2.2 Phase Detector Characteristic 5

2.3 Phase Detector's Shifted Characteristics 6

2.4 Signal Flow Model of a Phase Detector 7

2.5 VCO Charactenstics 9

2.6 VCO Shifted Characteristic 10

2.7 Signal Flow Model of a VCO 10

2.8 Linear Model of a PLL 11

2.9 Lock and Capture Range Relationship 15

3.1 Three-State Phase Detector 19

3.2 PFD State Diagram 21

3.3 Outputs of the PFD 22

3.4 Output Circuitry for Use with Phase/Frequency Detector 24

3.5 Plot of Average PFD Output Signal versus Phase Error 25

3.6 PFD with Charge Pump 27

3.7 Linear Model of a Simple Charge Pump PLL 29

3.8 Addition of Zero to the Capacitor 30

3.9 Addition of C2 to Reduce Ripple on the Control Line 31

3.10 Ring Oscillator with Inverters 34

3.11 Current Starved Inverter 35

4.1 Phase/Frequency Detector Implementation 37

4.2 Positive Edge-Triggered D Flip-FIop with Reset 38

4.3 Representation of D Flip-Flop 39

4.4 Three-input NAND Gate 40

4.5 Two-input NAND Gate 41

4.6 Schematic of Charge Pump/Loop Filler 43

4.7 Circuit for a Basic MOSFET Constant-Current Source 44

4.8 Schematic of an Inverter 47

4.9 Schematic of a Current-Starved Inverter 49

5.1 Phase/Frequency Detector 51

5.2 Zero-Phase Error 53

5.3 Phase Lag for 9a-Degrees Phase Error 54

5.4 Phase Lag for 180-Degrees Phase Error 55

5.5 Phase Lead 56

5.6 Frequency Lag 57

5.7 Frequency Lead 58

5.8 PFD Transfer Characteristic (Ideal) 59

5.9 PFD Transfer Characteristic (Actual) 59

S.IOCharge Pump/Loop Filter Combination 60

5.11 PLL Using a Charge Pump 61

5.12 Loop Filter Output for Phase/Frequency Lead 62

5.13 Loop Filter Output for Phase/Frequency Lag 63

5.14 PFD/Charge Pump Transfer Characteristic (Ideal) 64

5.15 PFD/Charge Pump Transfer Characteristic (actual) 65

5.16 Typical VCO Input and Output 66

5.17 VCO Transfer Characteristic 66

5.18 Control Voltage for 1 MHz 68

5.19 Control Voltage for Input Frequency of 1.6MHz 69

5.20 Input and Output Frequencies for I.6MHz Input 69

5.21 Input Frequency for 2MHz 70

5.22 Control Voltage for 2.5 MHz Input 71

5.23 Input and Output Signals for 2.5MHz Input 71

5.24 Control Voltage for a Frequency of 3 MHz 72

5.25 Control Voltage for a 3.6MHz Signal 73

5.26 Input and Output Signals for 3.6MHz Input 73

5.27 Control Voltage for 4MHz Input 74

5.28 Input and Output Frequencies for 4MHz Input 74

5.29 Control Voltage for 4.5MHz Input 75

CHAPTER I

INTRODUCTION

Phase-Locked Loops (PLL) are a relatively new class of circuits, used primarily

in communications applications. They are suitable for a wide variety of applications, such

as AM radio receivers, frequency multipliers, dividers, and as frequency synthesizers.

The phase locked loop was first described in the early 1930s, where its application was in

the synchronization of the horizontal and vertical scans of television. Later on with the

development of integrated circuits, the PLL found uses in many other applications,

including clock recovery from digital data signals, ftequency and phase modulation and

demodulation, and carrier signal recovery from satellite transmission signals. The first

PLL ICs came in existence around 1965, and were built using purely analog devices.

Recent advances in integrated circuit design techniques have led to an increased use of

the PLL, as it has become more economical and reliable. Now, whole PLL circuits can be

integrated as a part of larger circuits on a single chip.

The increased application of PLLs has led to the desire to improve the

characteristics and extend the range of the PLLs. To accomplish this feat requires more

detailed knowledge of the effects of different components and parameters on a digital

phase locked loop, specifically on the capture and lock range. The first step in such a

study is to design a digital phase locked loop circuit and estimate the capture range. This

thesis attempts at solving this initial step by designing a digital phase locked loop,

characterizing the components, and then discussing a method of estimating the capture

range.

The report is divided into six chapters. Chapter 2 introduces the reader to the

concept of phase-locked loop and its basic operating principles. It also discusses the

design problem with some background information, its significance, the current research

going on and various other issues related to it. Chapter 3 deals with the common methods

of implementing the components of a digital phase locked loop. Chapter 4 discusses the

approach used to solve the problem. This includes the design steps involved, some basic

equations supporting the research and the assumptions made. Chapter 5 describes the

simulation results and the calculations. Finally, Chapter 6 deals with the scope for future

work and conclusions.

CHAPTER 2

PHASE-LOCKED LOOP BASICS

A phase-locked loop is a feedback control circuit. As the name suggests, the

phase locked loop operates by trying to lock to the phase of an input signal through the

use of a negative feedback path. A basic form of a PLL consists of three fundamental

blocks, namely,

• Phase detector (PD),

• Loop filter,

• Voltage controlled oscillator (VCO).

The basic block diagram is shown in Figure 2.1.

! - •

PHASE DETECTOR *

LOOP FILTER VCO

Figure 2.1: A Basic Phase Locked Loop

2.1 Operating Principles of the PLL

The phase detector compares the phase of a periodic input signal against the phase

of the VCO. Output of the PD is a measure of the phase difference between its two

inputs. The difference vohage is then filtered by the loop filter and applied to the VCO.

The control voltage on the VCO changes the frequency in a direction that reduces the

phase difference between the input signal and the local oscillator.

When the loop is locked, the control voltage is such that the frequency of the

VCO is exactly equal to the average frequency of the input signal. As long as the initial

difference between the input signal and the VCO is not too big, the PLL eventually locks

on to the input signal. This period of frequency acquisition, is referred as pull-in time,

this can be very long or very short, depending on the bandwidth of the PLL. The

bandwidth of a PLL depends on the characteristics of the phase detector, voltage

controlled oscillator and on the loop filter [3].

2.2 Overview of the Functional Blocks

2.2.1 Phase Detector

The role of a phase/frequency detector in a phase-locked loop circuit is to provide

an error signal which is some function of the phase error between the input signal and

VCO output signal. If 6d represents the phase difference between the input phase and the

VCO output phase, the PD produces a voltage, vj, in response to Bj. A typical relation

between the voltage Vd, and the phase difference Bj is shown in Figure 2.2. The curve is

linear and periodic and it repeats every 27i radians. This periodicity occurs because a

phase of 27u radians is generally indistinguishable from a phase of zero [3].

N^y' ' * i

v< i IvoM

4,

/ 3

2

1

- \ y

""* ^ \

1 ^nL. ^

Figure 2.2: Phase Detector Characteristic [3]

When no signal is applied to the PD, it generates some free-running voltage, Vjo,

which is shown in Figure 2.2. Corresponding to Vjo on the curve is some phase, Gdo- The

usual convention is to shift the characteristic so that a phase error of zero corresponds to

Vd = Vdo- Therefore, the phase ertor is defined to be

The shifted characteristic of the phase detector is shown in Figure 2.3 [3].

- T -r/2 9^

Figure 2.3: Phase detector's Shifted Characteristics [3]

The ideal characteristic of the PD is linear between -nil and :t / 2. The slope of

the curve is constant and is equal to

K, =dvjd9^.

For this case, there is a slope = 4V/7u radians. = 1.27 V/rad. In the linear region, the PD

can be modeled by

This is represnted by the signal flow graph in Figure 2.4

Figure 2.4: Signal Flow Model of Phase Detector [3]

Phase-locked loops can be classified into three types based on their topologies

and mode of operation:

1. Analog PLL: In this type, all the components are analog circuits. The signals used

are also analog in nature.

2. Digital PLL: In this type, only the phase detector is digital whereas the loop filter

and VCO are analog in nature.

3. All-digital PLL: In this case, all the components are digital in nature. The signals

used are completely digital.

There are many ways to implement a phase detector circuit in a digital PLL, but

the most common approach is a multiplying phase detector. The three most important

multiplying phase detectors are:

• The EXOR gate,

• JK flip-flop,

• Phase-frequency detector (PID).

The underiying principle behind the operation of each of these phase detectors is

the multiplication of the VCO signal with the input signal, which outputs a dc error signal

that is a function of the phase error.

The other most commonly used technique to implement a phase detector is a

sequential detector. These types of PDs are constructed using digital circuit components,

such as flip-flops, latches and inverters. The only limitation for these types of phase

detectors is the switching speed of the digital logic circuitry they employ [8].

2.2.2 Voltaee-Controlled Oscillator

A VCO is a voltage controlled oscillator, whose output frequency is, ideally, a

linear function of its control voltage, Vc, which is generated by the phase detector. This

linear relation between the control voltage and the output frequency simplifies the PLL

design. A typical characteristic of a VCO is shown in Figure 2.5. The slope of the curve

is constant 13].

Figure 2.5: VCO Characteristics [3]

The slope of the curve is constant. As v varies from 0 to 2 volts, the output

frequency of the VCO varies from 3Mrad/s to 12Mrad/s. Outside this range the curve

may not be linear and the VCO performance degrades or becomes non-linear. When the

PLL is in the lock condition, the output frequency (Oo = (o,. For example, when the output

frequency of the VCO (co,) is 6Mrad/s from Figure 2.6. this frequency requires that the

control voltage Vc = 1 voU. This means that vj = Ivolt. A Vd = I requires a phase error of

9e = -0.79 radians. This average value of the phase error is called the static phase error.

The basic approach is that the static phase error should remain near zero and must not

increase beyond the PD linear range of +3i/2 and -idl radians. Based on these constraints,

the general strategy is that Vc should correspond to AtOo. the difference between tOoand o>,.

This results in a shifted characteristic of that VCO as shown in Figure 2.6 [3],

^o" TTT = lUxtiN

Figure 2.6: VCO Shifted Characteristics [3]

Figure 2.6 indicates that A(0o = 0 corresponds to Vc = V o. The slope of this curve

is the VCO gain, Ko, and is given by

KQ=dAo]^jdv^.

A simple model of the VCO is thus given as

and the signal flow graph is shown in Figure 2.7.

- \ _

Figure 2.7: Signal Flow Model of VCO [3]

2.2.3 Loop Filler

The filtering operation of the error voltage (coming out from the Phase Detector)

is performed by the loop filter. The output of PD consists of a slowly varying component

superimposed on a rapidly varying component. A low pass filter is used lo filter out the

higher frequency component, as it is undesired as an input to the VCO. The loop filter is

one of the most important functional blocks in determining the performance of the loop.

A loop filter introduces poles in the transfer function of the PLL, which in tum is a

parameter in determining the bandwidth of the PLL. Since higher order loop filters offer

better noise cancellation, loop filters of order 2 or more are used in most of the critical

applications involving PLL circuits [3].

2.3 PLL Bandwidth

The bandwidth of a PLL, which determines how fast the PLL follows the input

phase, or how long it will remain in the lock condition, depends on the characteristics of

the phase detector (PD), the voltage controlled oscillator (VCO) and the loop filter. Since

the bandwidth has to do with variations or ac signals, an ac model of the PLL can be

formed by eliminating the dc parameters. The model is shown in Figure 2.9.

Gis)

9, / ^ T ^ «. I I va — ^ + V — ^ /frf — ^

$0 ^ • • i . . .

*/> (C. — » - I/, - r * -

Figure 2.8: Linear Model of a PLL [3]

The integration (assuming a sinusoidal VCO, where the phase is the time integral

of frequency) can be replaced with I/s, using the Laplace transform, whets s represents

complex frequency. The closed loop transfer function is given by

0M_ G{s) ^ G(jco) 9M \+G{s) l+djw)

s

The forward gain of the PLL is given by

^ = ^<i^A^O-

The bandwidth occurs when

|G(;«)| = 1.

This occurs when

or in other words when

^ = 1

Oh,=K=K,K,K,.

Hence, the bandwidth of the PLL depends upon

• the gain Kd of the phase/frequency detector,

• the high frequency gain Kh of the loop filter,

• the gain Ko of the VCO [7].

Designs of the PD and the VCO are based on numerous other constraints. Thus,

the design of the loop filter is the engineer's principle tool in determining the bandwidth.

The selection of loop bandwidth forces trade-offs in the frequency acquisition speed. The

PLL pull-in speed is a function of the loop bandwidth. The simplest method of improving

the frequency acquisition characteristic is to widen the bandwidth of the loop filter.

However, the wider bandwidth degrades the tracking abilities of the PLL and increases

the time to obtain the desired output frequency [8].

2.4 Some Common Terms Encountered in PLL Literature

Free-running frequencv (fn, tOn). Also called the center frequency, this is the

frequency at which the loop VCO operates when not locked to an input signal. The

appropriate units for ft and coo are Hz and radians per second, respectively. [12]

Lock Range f2fT. 2(0i„). This is the range of frequencies over which the loop will

remain in lock. Normally the lock range is centered at the free running frequency, fo,

unless there is some nonlinearity in the system which limits the frequency deviation on

one side of ft. The deviations from ft are referted to as the Tracking Range or Hold-in

Range. The ti-acking range is therefore one half of the lock range. Lock range is also

called as synchronization range. It increases as the overall gain of the PLL is increased

[13].

Capture Range r2fr. 2tQr). It is the band of frequencies in the vicinity of ftwhere

the PLL can establish or acquire lock with an input signal. The capture range also is

centered at fo with the equal ranges called the Lock-in or Pull-in ranges. The cj^ture

range can never exceed the lock range. Capture range is also called Acquisition range

[13].

Lock-up Time (t^l. The transient time required for a free-running loop to lock.

This time depends principally upon the bandwidth selectivity designed into the loop with

the low-pass filter. The lock-up time is inversely proportional to the selectivity bandwidth

[12].

The lock and capture ranges of a PLL can be illustrated with reference to the

following figure, which shows the typical frequency-to-voltage characteristics of a PLL.

In the figure, the input is assumed to be swept slowly over a broad frequency range. The

vertical scale corresponds to the loop-error voltage.

I'd 0

K, 0

-VL-

• V

Lock range 2A/ -L—

Capture range

Figure 2.9: Lock and Capture Range Relationship [13]

Frequency

In the upper part of the above figure, the loop frequency is being gradually

increased. The loop does not respond to the signal until it reaches a frequency /y.

corresponding to the lower edge of the capture range. Then, the loop suddenly locks on

the input, causing a negative jump of the loop-error voltage. Next, Yd varies with

frequency with a slope equal to the reciprocal of the VCO voltage-to-frequency

conversion gain, and goes through zero asfs=fo. The loop tracks the input until the input

frequency reaches f2, corresponding to the upper edge of the lock range. The PLL

then loses lock, and the error voltage drops lo zero.

If the input frequency is now swept slowly back, the cycle repeats itself as shown

in the tower part of the preceding figure. The loop recaptures the signal at fi and traces it

down to f4. The frequency spread between (/"/, f3) and (/";, /<) corresponds to the total

capture and lock ranges of the system; that i s , ^ - / / = capture range and/4 -/2 = lock

range. The PLL responds only to those input signals sufficiently close to the VCO

firequency fo to fall within the lock or capture range of the system. Its performance

charactenstics, therefore, offer a high degree of frequency selectivity, with the selectivity

characteristics centered about/p.

If an incoming frequency is far removed from that of the VCO, so that their

difference exceeds the pass band of the low-pass filter, it will simply be ignored by the

PLL. Thus, the PLL is a frequency-selective circuit [I3J.

2.5 Design Problem

The capture range of a PLL is a critical parameter because (1) it trades directly

with the loop bandwidth; i.e., if an application requires a small loop bandwidth, the

acquisition range will be proportionally small; (2) it delermines the maximum frequency

variation in the input or the VCO that can be accommodated. In monolithic

implementations, the VCO free-running frequency can vary substantially with

temperature and process, thereby requiring a wide acquisition range even if the input

frequency is tightly controlled [2],

The phenomenon of lock acquisition (or capture) has attracted a lot of research.

The capture range is estimated for different topologies. Different architectures for the

PLL have been proposed which can broaden the capture range [1-3]. However, in most

of the research, very little emphasis was made on studying the exact dependence of the

capture range on the different circuit parameters, which define the individual components

of a phase-locked loop (a digital PLL. in particular). The effect of these parameters, for

instance, say, the W/L ratio of the transistors, can be prominent. Likewise, there are many

other factors which can affect the capture range. In order to study those effects, the first

step is to design a circuit which can actually estimate the capture range. The components

of this circuit should be characterized completely.

Thus the main objective of this thesis is to develop a circuit for a digital phase

locked loop, which can be used for solving the actual problem described above. This

circuit can be used as a starting point. Since the capture range is already estimated, the

next step would be to observe the dependence of this range on other circuit parameters.

CHAPTER 3

DIGITAL PHASE LOCKED LOOP: DESCRIPTION OF COMPONENTS

The main components in the design of a PLL are the phase detector, the loop filter

and the voltage contiislled oscillator (VCO). The basic operation of these components is

explained in Chapter 2. These components can be implemented using various

technologies. Usually, technical requirements of an application limit the selection of the

components that can be used in a particular design. In this chapter, some commonly used

technologies and the methods for selecting them based upon given specifications are

discussed.

3.1 Phase Detector

Many different types of phase detectors have been used in PLL designs. Two

broad categories of phase detectors can be distinguished: multiplier circuits and

sequential circuits. Multipliers generate the useful DC error output as the average product

of the input-signal waveform times the local oscillator waveform. A properly designed

multiplier is capable of operation on an input signal buried deeply in noise. A sequential

phase detector generates an output voltage that is a function of the lime interval between

a zero crossing on the signal and a zero crossing on the VCO waveform. Sequential [rfiase

detectors are capable of detecting both the phase and frequency differences [4]. They are

usually buih up from digital circuits and operate with binary, rectangular input

waveforms. In this design, a sequential phase detector was chosen. There are three main

digital phase detectors:

• Phase/frequency detector.

• EXOR phase detector,

• JK flip-flop phase detector.

3.1.1 Phase/Frequency Detector

The phase/frequency detector (PFD) is discussed here because it is the workhorse

of the Digital Phase Locked loop (DPLL), since it offers virtually unlimited pull-in range,

which guarantees PLL acquisition under even the worst operating conditions [6].

The schematic diagram of the phase frequency detector is shown in Figure 2.9.

ONE

Lx orr.

-CK

Be >CK

n

t—°o*

-Ct >Qg

ONE OFF,

Figui« 3.1: Three-State Phase Detector [1]

The operation of this ciituit is based on two D-type flip-flops and a simple AND

gate. Each flip-flop has the D-input wired high. Under this condition, the flip-flop with a

low Q output will transition to high on the next rising edge of its clock input. Also if such

a ti-ansition occurs when Q is high, then there will be no change in the flip-flop state. A

high signal on a reset input will force Q low as soon as the reset signal is applied. Finally,

a logically high on both of the Q outputs causes the resetting of both the flip-flops.

The PFD generates two outputs that are not complementary. The output signal

depends not only on phase error, 9e, but also on the frequency error, Ato = WA-COB- If the

firequency, COA, of the input A. is less than that of input B, WB, then the PFD produces

positive pulses at QA, while QB remains at zero. Conversely, if WA > MB, then positive

pulses appear at QB while QA= 0. If WA = OJB, then circuit generates pulses at either QA or

QB with a width equal to the phase difference between the two inputs. Thus the average

value of the QA - QB is proportional to the frequency or the phase differences between

the inputs at A and B. the outputs QA and QB are usually called the UP and DOWN

signals. Depending on the operation described above, the PFD is in at least one of the

three logical states: QA = QB = 0; QA = 0, QB = 1; and QA = L QB = 0. Also, to avoid

dependence of the output on the duty cycle of the inputs, the circuit should be

implemented as an edge-triggered sequential machine [1].

Numbers can be assigned to the various states as:

• QA = QB = 0-s ta te2 .

• QA = O.QB = 1 - state 0.

• Q A = 1 . Q B = 0-s ta te 1.

The circuit changes stales only on the rising edge of the transitions at the inputs A and B.

A state diagram summarizing the operation is shown in Figure 3.2

Figure 3.2: PFD State Diagram. [1]

The state of the PFD is determined by the positive edge transitions on the inputs

A and B as shown in the state diagram. If the PFD is in state 0, then a transition on A will

take the circuit to state 1. where the state values QA = I and QB = 0. The circuit remains

in this state until a positive transition occurs at the input B, and the PIT) returns to state 0.

The transition from the zero state to state 2 is same as a transition from 0 to I state. The

only difference being a positive transition at B occurs instead of at A.

i_ji_r-^i.-_

....rL_n.ru~iJ";L .n _r"l h f".

Figure 3.3: Outputs of the PFD [4]

Typical outputs of the Phase Detector are shown in Figure 3.3. Based on this

description of the circuit, it is easy to see that Figure 3.1 is a three-state logic device. Tlie

state where both QA and QB are high is not stable and is not included in the PFD state

diagram, since it generates a signal that resets both flip flops.

Also, if the input frequency, m„ is greater than that of the output frequency, a>o.

it implies that more transitions occur at input A, as compared to input B. In this situation,

the PFD output states toggle only between stales 0 and I. but never go into state 2. If ra,

» (Oo, then the PFD will remain in state 1 most of the time. When w, < ©o. PFD toggles

between state 2 and 0. and if w, « cOo, then it will remain in state 2 most of the time.

Thus, the average output signal, Vd. of the PFD varies monotonically with frequency

error, Aoo = o), - rao, when the phase lock loop is tracking in the out-of-lock mode.

3.2 Charge Pump

The output of a PFD can be converted into DC (voltage/current) in many different

ways. Since the difference between the average values of QA and QB is of interest, the

two outputs can be low-pass filtered and sensed differentially. However, a more common

approach is to interpose a charge pump between the PFD and the loop filter.

A charge pump is a three state design. It lakes two inputs from the PIT) and

outputs a DC current or voltage. The charge pump consists of two switched current

sources that pump charge into or out of the loop filter according to two inputs. It charges

or discharges a capacitor with voltage or current pulses. A filter is used to limit the rate of

change of capacitor voltage, and the result is a slowly rising or falling voltage that

depends on the frequency difference between the PLL output voltage and the reference

frequency. The VCO increases or decreases its frequency of operation as the control

voltage is increased or decreased [8].

Figure 3.4: Output Circuitry for Use with Phase/Frequency Detector [8]

In Figure 3.4, each transistor acts as simple switch that closes or opens based on

the input. Hence, when QA goes high, the terminal common to both FETs goes high and it

is grounded when QB goes high. In most applications, a high QA causes the charge pump

to pump some current into the loop filter. This generates a VCO control voltage that

slews the oscillation in the proper direction.

If the average signal, Uj, is plotted versus phase error, 9e, a saw tooth ftinction is

obtained, as shown in Figure 3.5 [1]. Figure 3.5 also shows the average detector output

24

signal for phase errors greater than 2ii or smaller than -2it. When the phase error, 6,,

exceeds 2ji, the PFD behaves as if the phase error is recycled at zero; hence the

characteristic curve of the PFD becomes periodic with period 27t. The gain, Kj can be

calculated from Figure 3.5 to be

' In

Figuie 3.5: Plot of Average PFD Output Signal Id versus Phase Error 6,. [1]

3.3 Dynamics of the Charge Pump PLL

With reference to the charge pump PLL shown in Figure 3.6, it can be deduced

that for a pulse of width, T, on QA, II deposits a charge equal to IT on Cp (which is the

25

low-pass filter, in this case). Thus, if WA > O>B, or WA = tos, but A leads B, then positive

charge accumulates on Cp steadily, yielding an increasing positive voltage on Wow-

Similarly, if the pulses appear on QB, I2 removes charge from Cp on every phase

comparison, dnving Voui towards a large negative voltage. In the third state, with QA = QB

= 0, Voui remains constant. Since the steady-state gain is infinite, it is more meaningful to

define the gain for one comparison instant, which is equal to IT/ (2ii Cp) [I].

«Vou»

Figure 3.6: PFD with Charge Pump [1]

The input period to the charge pump is T,. and the charge pump provides a current

of ± Ip to the capacitor. As shown in Figure 3.6, beginning with a zero phase difference,

at t = 0, and stepping the phase of B by "Ko gives

AO = < I > O H ( 0 -

As a result, QA or QB continues to produce pulses that are OoTJ (2jr) seconds wide,

raising the output voltage by

*„7-,

(2/r)

in every period. Approximated by a ramp, V^M thus exhibits a slope of (V Cp)<I)o/2rt and

can be expressed as

y..=j^.^.uo).

The impulse response is therefore given by

2 ; r C p

yielding the transfer function

A<1> (.) =

V 2;rC„ , V p J

Thus, the PFD/LPF combination contains a pole at the origin. The quantity (l-p/2n Cp) is

the gain of the PFD and is denoted it by KPFD-

PFD/CP/LPF vco

-nL^qx-

-T Ip 1

271 Cp «

fvco s

fout

Figure 3.7: Linear Model of a Simple Charge pump PLL [I]

A linear model of the charge pump PLL is shown in Figure 3.7. In this figure,

Kvco is the VCO gain and Kvco /s is the VCO transfer function. The open-loop transfer

function is given as

0 / Jf

* „ "^" InC ^ s'

Since this loop has two poles at the origin, this topology is called a "type 2" PLL. The

closed loop transfer function, denoted by H(s), for the sake of brevity, is thus equal to

I p K ^cf.

u{sy- ITTC p

5 2 ^ / P ^ V

2 ; r C p

The result contains two imaginary poles and is. hence, unstable. To avoid

instability, a zero must be added to the open-loop transfer function. This is in contrast to

the case of a simple low-pass filler, where the loop is. in principle, stable even with no

zero. The stabilizing zero in a charge pump PLL (CPPLL) can be realized by placing a

resistor in series with the charge-pump capacitor as shown in Figure 3.8

Figure 3.8: Addition of a Zero lo the Capacitor Cp [I ]

The PFD/CP/LPF now has the transfer function

It follows that the PLL open-loop transfer function is equal to

^f'^^ii^'hfT

His

The above compensated type 2 PLL suffers from a critical drawback. Since the

charge pump drives the series combination of Rp and Cp, each time a current is injected

into the loop filter, the control voltage experiences a large jump. Even in the locked

condition, the mismatches between I| and I2 and the charge injection and clock feed

through of Si and S2 introduce voltage jumps in Vcom- The resulting ripple severely

disturbs the VCO. corrupting the output phase. To relax this issue, a second capacitor is

usually added in parallel with Rp and Cp, suppressing the initial step [1].

Figure 3.9: Addition of C2 to Reduce Ripple on the Control Line [2]

3.4 VoUage-Controlled Oscillator

The voltage-controlled oscillator is perhaps the most critical part of PLLs. The

basic functioning of the VCO is explained in Chapter 2. For a VCO that is to be used in a

PLL, the following parameters are important [I]:

• Center frequency: It is also called the mid-range value and is determined by the

environment in which the VCO is used.

• Tuning range: The tuning range is determined by the variation of the center frequency

with process and temperature and the frequency range necessary for operation.

• Tuning linearity: The tuning characteristic of the VCO exhibits non-linearity, i.e. the

gain, is not constant. This degrades the settiing behavior of PLLs. Hence it is

desirable to minimize the variation of Kvco across the tuning range.

• Output amplitude: It is desirable to achieve large output oscillation amplitude, thus

making the waveform less sensitive to noise. The amplitude trades with power

dissipation and supply voltage. Also, the amplitude may vary across the tuning range,

an undesirable effect.

• Power dissipation: As with other analog circuits, oscillators suffer from trade-offs

between speed, power dissipation, and noise. Typical oscillators drain 1 to lOmW of

power.

• Supply and Common-Mode rejection: Oscillators are quite sensitive to noise,

especially if they are realized in single-ended form. Noise may be coupled to the

control line of a VCO as well. Hence it is preferable, to employ differential paths for

both the oscillation signal and the control line.

32

• Output signal purity: Even with a constant control voltage, the output waveform of

the VCO is not perfecUy periodic. The electronic noise of the devices in the oscillator

and supply noise lead to noise in the output phase and frequency. These effects are

quantified by "jitter" and "phase noise" and determined by the requirements of each

application.

3.4.1 Ring Oscillator

A common oscillator topology in monolithic PLLs is the ring oscillator, shown in

Figure 3.7. This circuit consists of an odd number of inverters connected in a circular

chain. Due to the odd number of inverters, this circuit does not have a stable operating

point and oscillates. The period T of oscillation is determined by the propagation time of

a signal transition through the complete chain, or T = 2 x tp x N, with N the number of

inverters in the chain. The factor 2 results from the observation that a full cycle requires

both a low-to-high and high-to-low transition. The fan-out of each inverter is one. Since

in a typical IC technology the gate delay is monitored and controlled within the process

comers, the oscillator frequency and its variation can be predicted with reasonable

accuracy [7].

Figure 3.9: Ring Oscillator with Invertors [7]

One of the primary reasons for implementing CMOS oscillators in the form of

ring oscillators is that these ring oscillators can be used for higher frequencies and better

phase noise performance than other CMOS VCO designs. They also have lower power

consumption [2],

While designing the VCO using ring oscillators with the simple topology used in

Figure 3.8(a), two important factors are taken into consideration, the frequency of

oscillation and the tuning range. These parameters have already been discussed in

Chapter 2. The factors on which these depend and how they can be controlled must be

determined. (1) Frequency of oscillation: A simple expression for the time period of

oscillation is given above. The frequency of oscillation is thus

F = I / ( 2 x t p x N ) .

This expression serves the purpose of finding the factors on which the oscillation

frequency depends and how it can be conti-oUed [7], (2) Tuning range: The tuning range

primarily depends on two factors, the supply voltage and the channel length of the

transistor. However, the effect of supply voltage is far less compared to that of the

34

channel length of the transistor. But practical constraints determine the limits to which

these parameters can be varied lo optimize the range. The capture range of the phase

locked loop depends lo a large extent on this tuning range of the oscillator [1].

3.4.2 Current Starved Inverter

The VCO is implemented as a simple ring oscillator as explained above. To vary

the oscillating period, the propagation delay of the composing inverters, which are

implemented using CMOS logic, is to be manipulated. This can be achieved by

controlling the current available to (dis)charge the load capacitance of the gate. Such a

circuit, called a current-starved inverter, is presented in Figure 3.10.

Figure 3.10: Current Starved Inverter [7]

In this VCO, the maximal (dis)charge current of the inverter is limited by adding

some extra devices. The NMOS transistor M3, controlled by the input voltage Vconn , acts

as a current source with value I„f and sets an upper Hmit on the discharge current.

Lowering V^^u reduces the discharge current and, hence, increases tpm,- Similarly, the

35

charging current is controlled with the aid of M5 is translated into a charge current with

the aid of the current mirror formed by the PMOS devices M^ and M4. M^ acts as a diode

and sets a bias voltage VGS6 that is controlled by Uf. With VGS4=VOS6 and assuming that

both devices operate in the saturation region, it follows that IDS4 = bse = Iief. Since both

M3 and M5 operate in the saturation region, a quadratic relation exists between Vconir and

Iref (and tp). As such, the oscillating frequency of the VCO can be controlled over quite a

large range. Also, to compensate for the asymmetry due to the difference in the mobility

of electrons and holes, a width ratio of 2:1 is maintained in the circuit. A Schmitt trigger

also can be included lo achieve fast rising and falling outputs at low frequency [7].

The circuit implementation of the topologies discussed above is dealt with in the

next chapter.

CHAPTER 4

DESIGN OF DPLL CIRCUIT

The individual components of a Digital Phase locked loop are explained in

Chapter 3. This chapter deals with the implementation of these components, the various

design steps involved and the assumptions made. The design and simulations of the PLL

are done in Oread Pspice.

4.1 Phase Detector

The phase detector is implemented as a phase/frequency detector based on two D-

flip-flops and a nand gate as shown in Figure 3.1. The schematic diagram for this circuit

designed in Pspice is as shown in Figure 4.1.

Figure 4.1: Phase/frequency detector implementation

nand2

VI • s v O I N ; _

ji

IF • iP TR-SP PW-7DUS

HCTIVELOWRESEn

Figure 4.1 cont.

The schematic of the D-flip flop circuit is as shown in Figure 4.2

yj—^ZH—^

Figure 4.2: Positive Edge-Triggered D-Flip Flop with Reset

38

The representation of the flip-flop and the tinth table are as shown in Figure 4.3

u X X I T 0 1 t 1

Figure 4.3: Representation of D Flip-PHop.

As can be inferred from the above truth table, the D-flip flop has a negative reset,

which means when the reset, R, is low. the flip-flop is reset and the output. Q. is always

at 0 level no matter what the logic level of the D-input or the clock is. When the reset is

high, the output follows the input at every rising edge. To perform the reset operation in

the PFD, an AND gale is used with the outputs of the flip-flops as the inputs. In this

design, since the flip-flop used in Figure 4.2 has a negative reset, a NAND gate

('nand2_4') is used to perform the positive reset (or reset operation when both the outputs

are high). The inputs and outputs are denoted as follows:

'CLOCKl' and 'CLOCK2' - the clock inputs to the flip-flops.

'DINI' and 'DIN2' - the d-inputs to the flip-flops, which are always kept high.

'QIOUT' and 'Q20UT' are the outputs of flip-flops.

'nand2' , 'nand2_r.' nand2„2'. 'nand2_3', 'nand2_4' are Ihe instances of the 2-

input NAND gales.

'nand3', 'nand3_l'.' nand3_2'. 'nand3_3'. 'nand3_4' , 'nand3_5'. 'nand3_6',

'nand3_7* are the instances for the 3-input NAND gales.

As can be seen from Figure 4.2, the flip-flop consists of four 3-inpul nand gates

and two 2-input nand gates. These gates are designed using CMOS logic. The schematic

diagrams are shown in Figure 4.4 and Figure 4.5, respectively.

Figure 4.4: Three-input NAND Gate

40

Figure 4.5: Two-input NAND Gate.

The NAND gates are implemented using CMOS. The operation of the two-input

NAND gate is explained here and can be extended to the three-input NAND gate also.

The circuit in Figure 4.5 consists of a series connection of two identical NMOS

transistors named 'CMOSN' and a parallel connection of PMOS transistors named

'CMOSP'. *A' and 'B' are the two inputs and 'nand2out' is the output. One end of the

NMOS transistors is connected to the output and the other end to ground. Likewise, one

end of the PMOS transistors is connected to the power supply, 'VCC, and the other end

to the output, 'nand2out'. The power supply voltage is equal to 5V. and a part named

VDC found in the Pspice library is used. The truth table of the NAND gate is given

below.

Table 4.1 Truth Table for a 2-input NAND Gale [I7J

OUTPUT

0

B INPUT

1

A INPUT

0 1

1

I

1

0

This table explains the operation of the 2-input NAND gate. In this case, a *0'

means ground or zero volts, and a ' 1' means supply voltage (5 volts in this case). The

parameters of the MOS ti-ansistors are included in the Appendix. To compensate for the

difference in mobility of electrons and holes, the W/L ratio of the PMOS transistors is

chosen to be twice that of the NMOS transistors.

4.2 Charge pump/Loop Filter

The schematic of a charge pump PLL is shown in flgure 3.9. The design of the

PFD is discussed in the previous section. This section discusses the design of the charge

pump and the loop filter. The schematic diagram used for implementing the charge pump

and loop filter is shown in Figure 4.6.

CMOSI*"] L

i} (^-l 1 1

f • ^ R3 ^ 30P

i

Figure 4.6: Schematic of Charge Pump/Loop Filter

4.2.1 Charge Pump

The charge pump consists of two switched current sources. The current sources, I|

and I2, are implemented using MOSFET current sources. Ii, which acts as a current

source, is implemenled using PMOS transistors whereas I2. which acts as a current sink,

is implemented using NMOS transistors. MOSFET current-sources can be used in place

of the resistors since the actual implementation of resistors requires a relatively large area

on a silicon chip [16].

VDD

i t

4^ ID\\

erJi^V^

\>o

Figure 4.7: Circuit for a Basic MOSFET Constant-Current Source. [16]

The operation of a basic current mirtor circuit is explained with reference to

Figure 4.7 which gives a basic current source using NMOS transistors [16]. The heart of

the circuit is transistor Qi whose drain is shorted to its gate and thus is operating in the

saturation region, such that

U ' fW D\ 2 « L j l G S

V ^ , - V , -(4.1)

where the channel-length modulation is neglected. Here, k'n is the process

transconductance of a NMOS transistor. W and L are the width and length of the

channels in the transistor, respectively.

The drain current of Q, is supplied by VDD through resistor R. Since the gate

currents are zero,

V - V / = / DP GS Dl 'REF ^ ^^ ,

where the current through R is considered to be the reference current of the current

source and is denoted IREF.

Transistor Q2 has the same VGS as Qi Thus, if it is assumed that it is operating in

saturation, its drain current, which is the output current lo of the current source, will be

'0 = 'o2-k'^n[l-)^[yCS-^.f (4.3)

From equations 4.1 and 4.3. the output current lo can be related to the reference current

IREF,

^0 _ ( ^ / ^ ) 2

^ REF

Thus, the relationship between lo and IREF is solely determined by the geometry of

the transistors. When the transistors are of the same size, then lo = IREF, and the circuit

simply mirrors the reference current in the output terminal, and is hence called a current

mirror circuit. The operation of a PMOS current is quite similar to that of a NMOS

current mirror, except that a PMOS current source sources the current from the power

supply, and the NMOS current source sinks the current to the ground [16],

From Figure 4.6, the PMOS current mirror consists of PMOS transistors M9 and

MIO, with a bias resistor RI = 30K£l and a power supply VCC = 5V. The NMOS current

45

mirror consists of NMOS transistors MI 1 and MI2, with a bias resistor R2 = 30Kn. The

switches S, and S2 in Figure 3.9 are implemented using PMOS (M7) and NMOS (M3)

transistors respectively. A MOS transistor can act as a switch, by controlling the voltage

applied to its gate. The voltage applied to the gate can turn the transistor either on or off

In the off position, the MOSFET behaves as an open circuit between drain and source,

whereas in the on position, the MOSFET presents a resistance rps between drain and

source which is given by [16]

The value of the on resistance of the switch depends on the location of the

operating point on the triode-region, and also the gate-source voltage and the device

dimensions [8].

From Figure 4.6, it can be observed that the outputs of the PFD. QIOUT and

Q20UT are connected to the MOS switches through inverters. An inverter is placed at

the input of the PMOS transistor, since as explained in Chapter 3, the switch is supposed

to be closed (or ON) when the pulses at QIOUT are high. For a PMOS transistor to be

on, the gate-to-source voltage vcs^Vi. For a high input (5V in this case) to the gate, the

switch is closed since the above relation is not satisfied. Hence an inverter is used to

provide the necessary voltage at the gate of the PMOS transistor. Two inverter circuits

are placed in series at the input to the NMOS transistor (M3), to performing buffering

action. The inverter circuit is used as instances named 'inverter'. 'inverter_r and

•inverter_2'. The connectors CIN and COUT are used to connect the outputs of the

current mirrors to the sources of the transistors M3 and M7.

The inverter circuit in the design is shown in Figure 4.8

CMOSFH U

VCC

CMOStJn I 'J_

J "0

Figure 4.8: Schematic of an Inverter

The inverter circuit consists of a NMOS transistor (MI) and a PMOS transistor

(Ml). When there is a HIGH (5V) signal at the input (VIN). the M2 is off and Ml is on,

pulling down the output (VOUT) to LOW (ground or OV). Similarly, when there is a

LOW at the input. Ml is OFF and M2 is ON, pulling up the output to HIGH.

4.2.2 Loop Filter

The loop filter is a 2ND-order low-pass filter consisting of a resistor R3 equal to

Ikil and capacitors Cl and C2 with values 150pF and 30pF respectively. The reason

behind choosing a 2ND-order filler is explained in Chapter 3. Discrete components are

used in this design. However, in practical circuits, these are implemented using MOS

transistors because discrete components require large areas on the chip. A resistor can be

implemented using a CMOS transmission gate and a capacitor using a NMOS transistor

with the source, drain and bulk grounded and control voltage applied to gate [1, 16]. The

output of the loop filter is VOUT, which is connected lo the input of the VCO.

4.3 Voltage-Controlled Oscillator

The voltage-controlled oscillator is implemented using a current-starved inverter.

The operation of a current-starved inverter is explained in Chapter 3. The schematic used

to implement this circuit is shown in Figure 4.9.

T5

QSht4l I

22

asF^ I I a osrta I ) cijosr

CMOS) a

CMOSlfig J

•f*"] I I a osp'ia I ) c« osF*! M CMCSffia I

cf asm U

•^Mi

Mjqj

CMJJT

^ .

"1 Hh

1 Figure 4.9: Schematic of a Current-Starved Inverter.

In relation to Figure 3.10. the inverter is implemented using CMOS logic. The

operation of a CMOS inverter is explained in an earlier section. In this design, three

inverter stages are used. The output of the inverter stages is connected to another inverter,

which acts as a buffer, the control voltage is given at the gate to the NMOS transistor

M3I. This input is actually the output of the loop filter 'VOUT', which thus act as the

control voltage to the VCO. Transistors M21, M22, M23, M24. M31, M32. M33, and

M34 drive the inverters. The source of each of the NMOS transistors and PMOS

transistors is connected to the ground or 0 volts and the supply voltage or 5 volts

49

respectively. The output is observed at the inverter formed by M35 and M36. Il is

denoted by *VCO_OUT'.

4.4 PLL Design

When the operation of the PLL is observed, these individual components are

connected and the output of the VCO. 'VCO_OUT' is connected to 'CL0CK2', which is

one of the clock inputs of the PFD. The components are connected as shown in Figure

3.9. In the next chapter, the simulations used to test the designed components are

discussed.

CHAPTER 5

PLL SIMULATIONS AND RESULTS

The digital-phase locked loop is built from three individual components as

explained in earlier components. These three blocks are then integrated to get the final

loop. The individual blocks are tested for their proper functionality. The corresponding

simulations and resuhs are shown.

5.1 Phase/Frequency Detector

A phase/frequency detector designed with D- flip flops is shown in Chapter 3. For

the sake of convenience, the block diagram of a PFD implemented with D-flip-flops is

shown in Figure 5.1.

one DPF.

A « ^ > C K t — ' O *

>CK

n &

>Q(

DFF, ONE

Figure 5.1: Phase/Frequency Detector [1]

The PFD has two inputs, A and B, one is the reference or the input signal (A), and

the other is the output of the Voltage Controlled Oscillator (VCO) (A), which is also the

control signal. A supply voltage of 5V is used in all the simulations. As shown in the

figure above, the D input of each of the flip-flops is tied to logic I, which is connected to

the supply voltage in this case.

To verify the operation of the PFD, the output of the VCO is not given; instead

another test signal is given as the 2"" input, B. It is tested for different cases, which are

mentioned here along with the corresponding simulation results. The width of the output

pulses change with varying input phase or frequency difference, at either one of the

outputs, depending on lag or lead.

5.1.1 Phase Lag

In this case, the signal at input B has the same frequency as the signal at input A,

but lags it in phase. In this example, a frequency of 0.5MHz is chosen. As explained in

chapter 3, the pulses occur at the QA output of the PFD (V (QIOUT) from the Figure

4.2). When the phase error is zero, as shown in Figure 5.2, no pulses occur on either QA

or QB- AS the phase ertor increases, the width of the pulses occurring also increases. This

can be seen for three cases of phase errw, 0, 90 and 180 degrees in Fig. 4.2 - 4.3. In

Figure 5.2, V (CLOCKl) and V (CL0CK2) are the two inputs to the Phase/frequency

detector, with the same frequency and the same phase. The other two waveforms V

(QIOUT) and V (Q20UT) are the outputs of PFD. which are short narrow pulses as

expected since there is no phase/frequency error between the two inputs.

" V (CLOCK 1

1 1 1

1

Figure 5.2 Zero-Phase Error

Figure 5.3 shows the PFD waveforms for the case where V (CL0CK2) lags V

(CLOCKl) by a phase error of 90 degrees, by of the same frequency. In this case, pulses

should appear at V (QIOUT), which is evident from the figure.

r" h

SELi..

50V

„v

P"

• ' 1 1 1 1 j • ViCtOCKIJ

1 n V(CLOCK?)

1 ! t n

o VfOlOUTi

. 1 1

• viozouT]

Figure 5.3 Phase Lag for 90-Degrees Phase Error

Figure 5.3 shows waveforms which are similar to Figure 5.2 except that the phase

error is ISO degrees in this case. Pulses at V (QIOUT) are broader than the case when the

phase lag is 90 degrees (figure 5.3). This is also expected since the width of the output

pulses of a PFD increases with increase in phase error.

p

„.

3 5V

50V

2 5\1

OV

SEL>

•

11 1 l l | j | | ! | = VlCLOCKt}

1 !

II 11 1 . VIC10C«2>

w r n ir n t 1 1 n

. V.O-OUT.

. Vr020UT)

Figure 5.4 Phase Lag for 180-Degrees Phase Error

5.1.2 Phase I.ead

In case of phase lead, the output signal leads the signal at input A in phase, but

has the same frequency. For a phase lead, the pulses should occur at the QB output of the

PFD, which is V (Q20UT) as shown in Figure 5.5. V (CLOCKl) and V (CL0CK2) are

the 'A' and 'B' inputs respectively to the PFD. and V (QIOUT) and V (Q20UT) are the

outputs. V (CLOCKl) lags V (CL0CK2). Hence, the circuit behaves as expected.

i,ov4

2 . 5 W •

i

V I ' C L C C K J ;

1

11

s.ov-l 1-1

1

Figure 5.5 Phase Lead

5.1.3 Frequency Lap

Here, the frequency of the signal at input B lags the fi^quency of the signal at

input A. The PFD detects this difference in frequency by giving pulses at the QA output

Again, the width of the pulses at QA is proportional to the frequency difference between

the two signals. This is verified in Figure 5.6, where the input signal V (CLOCKl) has a

higher frequency than V (CL0CK2), and as explained before, pulses appear at QA (which

is V (QIOUT).

, w

° ,»

ov

s.cw

2.t\

OV

i .cu

2 5 i

= V 'CLOCK; 1

I i

]_

•> V 1 CLOCK? 1

1 J , " \. (OiQiri

1 1 "". V(Q20U- i

Figure 5.6 Frequency Lag

5.1.4 Frequencv Lead

Finally, the case where the frequency of the signal at input B leads the frequency

of the signal at input A is observed. The pulses appear at the output of QB- This is verified

in figure 5.7. Here. V (CLOCKl) represents signal at input A and V (CLOCK2)

represents signal at input B.

• • 1 1 1 t

1 1 ' 11 1 1 II ! 1 1 T I

\

'" I^ r • n i II ^

Fig. 5.7 Frequency Lead

5.2 PFD Transfer Characteristic

The PFD u-ansfer characteristic is plotted with the average output voltage

(average of the difference between output signals at QA and QB in Figure 5.1) versus the

phase error between the two input signals (al A and B inputs in Figure 5.1). The two

input signals have the same frequency, but the phase is varied. The X-axis gives the phase

error between the two signals at the PFD input. The y-axis is the average voltage.

Figure 5.8 PFD transfer characteristic (ideal) [2]

In Figure 5.8, the ideal characteristic is shown. The transfer characteristic plotted

from the measured values is given in Figure 5.9.

Figure 5.9 PFD Transfer Characteristic (actual)

59

From Figure 5.9, it can be inferred that the average output voltage is fairiy linear

over the range -360 degrees to +360 degrees, which can be verified from the ideal curve.

5.3 Charge Pump/Loop Filter

The operation of charge pump/loop filter combination is explained in Chapter 3.

The circuit used to implement this combination is shown in Figure 4.6. It is repeated here

in figure 5.10 for convenience.

J

Li? ^^^~^^

T "

i

Figure 5.10 Charge Pump/Loop Filter Combination

Figure 5.11 PLL Using a Charge Pump [1]

The PFD/CP combination is tested for two cases. The simulation waveforms are

shown in both the cases.

5.3.1 Phase/Frequency Lead

With reference to Figure 5.9 and Figure 5.10, when two signals with equal

frequency, but different phase are given at the two inputs to the PFD, with the signal at

'B' input leading the signal at 'A' input, pulses appear at QB output. This is verified from

Figure 5.5. Now, if these output pulses are given to the inputs of the charge pump, QA

and QB, then, the NMOS transistor M3 is 'ON' and the charge pump discharges the loop

filler. Thus, the output of the loop filter is a gradually decreasing voltage. This is verified

from the simulation shown in Figure 5.11 where V (QIOUT) and V (Q20UT) are the

two inputs to the charge pump and V (VOUT) is the output of the loop filter. A slowly

decreasing voltage is observed, which is as expected.

Figure 5.12 Loop Filter Output for Phase/Frequency Lead

5.3.2 Phase/Frequency Lag

In this case, the signal at the 'B' input of the PFD lags the signal at the 'A' input,

but with the same frequency. Now, pulses occur at QA output of the PFD, as shown in

Figure 5.3. In this case, the PMOS transistor 'M7' is 'ON' and voltage slowly builds up

at the output of the loop filter. This is shown in the simulations in flgure 5.11, where V

(VOUT) represents the output voltage of the filter, V (QIOUT) and V (Q20UT) are the

outputs of the PFD (which are the inputs of the charge pump)

62

Figure 5.13 Loop Filter Output for Phase/Frequency Lag.

5.4 Transfer Characteristic of the Charge Pump/Loop Filter Combination

The transfer characteristic of the PFD/charge pump combination is mentioned in

Chapter 3. Figure 3.5. It is quite similar to that of the PFD except that the average value

of the pump current h is plotted against the phase error. The ideal curve is shown in

Figure 5.14. The actual curve for twolMHz signals at the input of the PFD, but with

different phase errors is plotted in Figure 5.15.

Figure 5.14 PFD/Charge Pump Transfer Characteristic (Ideal)

In Figure 5.15, the x-axis is the phase error between the two input signals to the

p r o expressed in degrees. It can be inferred that the curve is fairly linear over the range

from -360 degrees to +360 degrees. A linear fit is performed for data points in this range.

From the curve, the gain of the PFD/charge pump combination is calculated as follows:

Kd = Id/ee [AA/rad = Ip/2jc [lAJrad = 130.77/2n^A/rad

g -4X) -300 -200 -100 100 200 300 4110

ERROR(DEGREES)

Figure 5.15 PFD/charge pump transfer characteristic (actual)

5.5 Voltage-Controlled Oscillator

The operation of the voltage-controlled oscillator is explained in Chapter 3. As

the control input voltage of the VCO increases or decreases, the output frequency

increases or decreases, as long as the input voltage is in the operating voltage range of the

VCO.

As explained in an earlier chapter, a current-starved inverter is used to perform

the required operation. A typical simulation is shown in Figure 5.16. In this simulation,

the input to the VCO is a ramp voltage, varying from IV to 4V (upper part of Figure

5.15). The output is a signal continuously varying in frequency (lower part of Figure

5.15). The frequency of the output is plotted as a ftinction of the input voltage to get the

transfer characteristic shown in Figure 5.13.

; ..,.,

\ : Si.. ..

.^AhMi

.

—

[

If' ill fir

, - ^

.

X"^""^

i

ilHH

- • - -

1 Figure 5.16 Typical VCO input and output

VCO CURVE

g 4 - —

— - - ,

y - 1.627X-

.y> y^

l.032J^

VOLTAGEtVOLTS)

Figure 5.17 VCO ti-ansfer characteristic

66

Some of the important observations about this VCO that can be made from the curve in

figure 5.17 are:

1. Operating frequency range (hnear or tuning range of operation):

1.5 MHz to 5 MHz.

2. Voltage range for this frequency range:

1.7V to 4V.

3. Center Frequency = 3.25 MHz.

4. Gain of the VCO: Ko = 1.627 MHz/volt (from linear fit).

5.6 PLL Performance

In order to estimate the frequency range over which the PLL locks, the PLL

performance is observed at different input frequencies varying fi-om 1 MHz to 5 MHz. In

each of these cases, the input, output and the control voltage at the output of filter are

observed. The range of frequencies over which the output locks on to the input signal is

given in Table 5.1, along with the corresponding control voltage at the output of the loop

filter. This range is Ihe normal operating frequency range of the phase locked loop. The

simulated capture behavior is shown for frequencies varying from 1 MHz to 5 MHz,

where the output voltage of the loop filter is plotted against time.

Table 5.1 Range of Frequencies for which Capture Occurs.

Frequency of the input sisnal(MHz)

1.6 2

2.5 3

3.6 4

Control voltage at the output of the loop filter(V)

1.8 2

2.2 2.4 2.6 2.8

Input frequencv = 1 MHz: When the frequency of the input signal is 1 MHz, it

can be seen clearly from Figure 5.18 that the control voltage does not settie down to a

fixed value. Clearly, the output does not lock onto the input (Fig.5.18).

Figure 5.18 Control Voltage for 1 MHz

68

Input frequency = I.6MH7.. From Figure 5.19, it can be seen that the control

voltage settles to a constant value after 25us to a stable value. The input and output

signals are shown for this case in Figure 5.20 that clearly shows that the lock occurs

(Figs.5.19-20).

f

1 •••

1

' i-

-h

i i W:'

...:. i . j j

! ' ! •

M ; : | 1

• 1 •

••- • 1 -- - • :

|....|i-:.[.Lji;.|

Figure 5.19 Control Voltage for Input Frequency of 1.6MHz

..,.ji1]:J. ti^....!i.iL.lJi.L. jTnn-&ri;pfrn"Tpt n j -

••'• , _ ] . , : ; . . . _ ._ i : ' , j •". "

Ftf--^-\Jr-"v--- y-^-U--|--y-i---\—\ --

J ^ J . " • ' ' -

Trf ifiriFTfii^f :;l| j .:M..:::.E|:: -11--- ] --4|---^----V----vi--ij-"y-

Figure 5.20 Input and Output Frequencies for 1.6MHz Input

Input frequency = 2 MHz. At this frequency, the conti-ol voltage settles to a constant

value as the VCO output frequency comes closer to the input frequency, after several

cycle slips (Fig.5.21).

Figure 5.21 Input Frequency of 2MHz

Input frequency = 2.5 MHz.. For this frequency, the settling behavior can be

observed clearly in Figure 4.15. Also, the input and output frequencies are shown. It can

be observed that the output frequency matches that of the input (Fig.5.22-23)

..U.Lj.

•j^

%

: I - i - !

w

^

w^

: . ; _ • , ,

.:.||..:.

1 •

,ili rtir

'•[:-;

w l A A A i A A A i '

Hilj i- iU "liM

Figure 5.22 Control voltage for 2.5MHz input.

:i:;i n ' r r n n n 1 nl n n

L L " 1 L • i ± • L - ' - -

ri'^rnnniinnrilinrf

i i j JliLiJ:±lt-L_:: Figure 5.23 Input and Output Signals for 2.5MHz Input

Input frequencv = 3MH7 This is quite similar to the previous case. The output

voltage of the loop filter clearly settles down to a constant voltage after 70 us (Fig.5.24)

1 j - j - -

W A

1-:

. ,_ |..,_,

/w ' ' r r

W W

•tta= 1' ::-i-:-:-H-:::

\/\A

i:''

AAf

;

- ' ' '

- . : ! : | . - :

..

\ '' : \

^rhF'

- • - ' ' '

.L,li_

---':

•'-;'••[-

Figure 5.24 Control Voltage for a Frequency of 3 MHz

Input frequencv = 3.6 MHz. This is quite similar to the case above. The input and

output frequencies are equal in this case too (Fig 5.25-26).

Figure 5.26 Input and Output Signals for 3.6MHz Input

Input Frequencv = 4 MHz. The settling behavior is very clear in this case too. The

input and output are also shown (Figs. 5.27-28).

Figure 5.28 Input and Output Frequencies for4MHz Input

74

Input freouencv = 4.5 MHz At this frequency il can be observed that the control

voltage does not settle down to a fixed voltage. Hence, it can be inferred that the loop

does not lock at this frequency.

Figure 5.29 Control Voltage for 4.5MHz Input

It can be concluded from the above observations that the capture range of the PLL

is 1.6 M H z - 4 MHz (Fig 5.29).

5.7 Conclusion

The designed circuit components and the overall loop are thus verified to be

working as expected. The capture process occurs for a frequency range of 2.4 MHz.

Some improvements in the design and the future work are discussed in Chapter 6.

CHAPTER 6

CONCLUSIONS AND FUTURE WORK

Phase Locked Loops remain an interesting topic for research, as it covers many

disciplines of electrical engineering such a communications theory, control systems,

signal analysis, analog and digital circuit design and non-linear analysis.

The next step in solving the actual problem is. as mentioned earlier, to observe the

effect of changing different circuit parameters on the estimated capture range. Many

other aspects can be combined lo achieve better performance. For instance, stability

analysis can be performed by taking the loop dynamics into consideration to achieve a

belter working model. Based on this stability analysis, the effect of higher-order loop

filters can be studied to enhance the performance of the PLL. In the design of loop filler,

discrete capacitors and resistors were used. Instead, they can be replaced by MOS

transistors, so that the designed circuit is more practical in nature.

Several imperfections in the phase detector/charge pump circuits, like the

generation of narrow, coincident pulses on both the outputs of the PFD, even when the

input phase difference is zero, may lead to high ripple on the control voltage even when

the loop is locked. This ripple modulates the VCO frequency, sometimes producing a

waveform that is no longer periodic [2]. A study of these non-idealilies would help

understand the consequences and how they affect the system performance.

Finally, one of the most important aspects is the noise analysis. It is necessary lo

accurately characterize the noise performance because each of the components

contributes noise which affects the system in a non-linear fashion. More details about the

sensitive points and parameters of the design can be provided by including noise

consideration.

REFERENCES

1. Behzad Razavi, Design of Analog CMOS Integrated Circuits. New York: McGraw-Hill, 2001.

2. Behzad Razavi, Monolithic Phase-Locked Loops and Clock Recovery Circuits. New York: IEEE PRESS, 1996.

3. Dan H. Wolaver, Phase-Locked Loop Circuit Design. Englewood Cliffs, NJ: Prentice Hall, 1991.

4. Roland E. Best, Phase-Locked Loops- Design, Simulation and Applications. Fourth Edifion, New York: McGraw-Hill, 1999.

5. F. M. Gardner, Phase lock Techniques. Second Edition, New York: John-Wiley and Sons, Inc. 1979.

6. Ulrich L. Rohde, Digital PLL Frequency Synthesizers-Theory and Design, Englewood Cliffs, NJ: Prentice-Hall. Inc., 1983.

7. Jan M. Rabaey, Digital Integrated Circuits - A Design Perspective. Englewood Cliffs, NJ: Prentice-Hall, 1996.

8. Gursharan Reehal, "A Digital Frequency Synthesizer Using Phase Locked Loop Technique." Retrieved February 13* , 2002 from httD://eewww.ene.ohio-state.edu/ie/main/Publications/PLL/reehal thesis.pdf. 1998.

9. H. Hatano, K. Doi, J. Iwamura, "Design of PLL-based clock generation circuits," IEEE Joumal of Solid-State Circuits, vol. 22, pp.255-261, April 1987.

10. Uya I. Novof, John Austin, Ram Kelkar, Don Strayer, Steve Wyatt. "Fully Integrated CMOS Phase-Locked Loop with 15 to 240 MHz Locking Range and ±50ps Jitter,"/EEEJouraa/o/So/id-fta/eCircuiK, vol.30, No.ll,pp.l259-1266. November 1995.

11. Ian A. Young, Jeffirey K.Greason, and Keng L.Wong. "A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors," IEEE Joumal of Solid-Slate Circuits, vol. 27, no. 11, pp. 1599-1606. November 1992.

12. Application Note, Phillips Semiconductor, "An overview of the phase-locked loop," ANI77, December 1988.

13. Eugene R. Hnatek, Applications of Linear Integrated Circuits. New-York: John-Wiley and Sons, 1975.

14. Oscal T-C. Chen, Robin Ruey-Bin Sheen. "A Power-Efficient Wide-Range Phase-Locked Loop." IEEE Joumal of Solid-State Circuits, Vol. 37. no.l, January 2002, pp.51-61.

15. Elizabeth Bradley. "Using Chaos to broaden the capture range of a Phase-Locked Loop," IEEE Transactions on Circuits and Systems-1: Fundamental theory and applications, Vol.40, No.l I, November 1993.

16. Adel S. Sedra and Kenneth C. Smith. Microelectronic Circuits. Fourth Edition. New York: Oxford University Press. 1997.

17. Neil H.E.Weste and Kamran Eshraghian. Principles of CMOS VLSI design-A Systems Perspective. Second Edition. Reading, MA: Addison-Wesley, 1998.

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