Chapter FiveProcessor Types and Instruction SetsDr. Chuck Lillie

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Instruction SetSet of operations the hardware recognizesRepresentation the hardware uses for each operationThe set of operations a processor provides represents a tradeoff among the copst of the hardware, the convenience for a programmer, and engineering considerations such as power consumption

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Program Flow in Computer

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Flowchart to execute assembly language program

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Java Program Execution

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Instruction Set Illustration

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Instruction Formats

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Variable-Length vs Fixed-Length InstructionsVariable-LengthMakes optimal use of memoryRequires complex hardware to decodeFixed-LengthRequires less complex hardwareProcessor can operate at higher speeds Can fetch and decode instruction without examining opcode

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RegistersGeneral PurposeFixed sizeSupports fetch and storeActs as temporary storage facilitySmall number of registers, < 100Usually large enough to hold an integerProcessor does 32 bit arithmetic, registers have 32 bitsNumbered from 0 to N-1

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RegistersProgramming with RegistersOperands stored in general purpose registersPlace results in general purpose registersMust move value to registers and from registersload a copy of X into register 3Load a copyh of Y into register 6Add the value in register 3 to the value in register 6 and place the result in register 7Store a copy of the value in register 7 in Z

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From Essentials of Computer Architecture by Douglas E. Comer. ISBN 0131491792. 2005 Pearson Education, Inc. All rights reserved.Operands from an instruction must come from different banks

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From Essentials of Computer Architecture by Douglas E. Comer. ISBN 0131491792. 2005 Pearson Education, Inc. All rights reserved.Since operands must come from different banks, this presents a problemX and Y must be in separate banksZ and X must be in different banksSo either Y or Z will have to be moved to complete T

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Complex and Reduced Instruction SetsComplex Instruction Set Computer (CISC)Includes many instructions (hundreds)Each instruction can perform an arbitrarily complex computationIntels Pentium is CISCProvides hundreds of instructionsComplex instructions that require a long time to completeInstructions that manipulate graphics in memory, instructions to compute sine and cosine functions

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Complex and Reduced Instruction SetsReduced Instruction Set Computer (RISC)Minimum set of instructions sufficient for all computations, around 32Each instruction performs a basic computationInstructions are fixed sizeExecute instruction in one clock cycleMotorolas MIPS processor, had 32 instructions and each takes only one clock cycle

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From Essentials of Computer Architecture by Douglas E. Comer. ISBN 0131491792. 2005 Pearson Education, Inc. All rights reserved.

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From Essentials of Computer Architecture by Douglas E. Comer. ISBN 0131491792. 2005 Pearson Education, Inc. All rights reserved.Although a RISC processor cannot perform all steps of the fetch-execute in a single clock cycle, an instruction pipeline with parallel hardware provides approximately the same performance once the pipeline is full, one instruction completes on every clock cycleFetch instructionExamine opcodeFetch operandsPerform operationsStore results

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From Essentials of Computer Architecture by Douglas E. Comer. ISBN 0131491792. 2005 Pearson Education, Inc. All rights reserved.

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From Essentials of Computer Architecture by Douglas E. Comer. ISBN 0131491792. 2005 Pearson Education, Inc. All rights reserved.Fetch instructionExamine opcodeFetch operandsPerform operationsStore results

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Other Causes of StallsAny instruction that delays processing or disrupts the normal flowAccesses external storageInvokes a coprocessorBranches to a new locationCalls a subroutine

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From Essentials of Computer Architecture by Douglas E. Comer. ISBN 0131491792. 2005 Pearson Education, Inc. All rights reserved.Delay D subtract E C until C is available

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From Essentials of Computer Architecture by Douglas E. Comer. ISBN 0131491792. 2005 Pearson Education, Inc. All rights reserved.Add a feature to the processor to detect the stallSends the output from Instruction K directly to Instruction K + 1

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Types of OperationsInstructions are divided into basic categoriesArithmetic instructions (integer arithmetic)Logical instructions (also called Boolean)Data access and transfer instructionsConditional and unconditional branch instructionsFloating point instructionsProcessor control instructions

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Data movement instructions for the 8085 microprocessor

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Data Operation instructions for the 8085 microprocessor

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Program Control instructions for the 8085 microprocessor

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Program Counter, Fetch-Execute, and BranchingProgram counter: used to store the location of the next instruction in memoryStart the fetch-execute cycle by getting the address of the next instruction in memory from the program counterOnce the instruction is fetched, update program counter

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Algorithm used to move through the fetch-execute cycleAssign the program counter an intial program address. Repeat forever {Fetch: access the next step of the program from the location given by the program counter.

Set an internal address register, A, to the address beyond the instruction that was just fetched

Execute: Perform the step of the program

Copy the contents of address register A to the program counter

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Subroutine Calls, Arguments, and Register WindowsTwo basic methods to pass parametersStore them in memory, eg, put on a stackCould be slowUse registersFaster, but limited number which may cause conflict with operandsCould use a register windowSubset of registers used to pass parameters

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From Essentials of Computer Architecture by Douglas E. Comer. ISBN 0131491792. 2005 Pearson Education, Inc. All rights reserved.Registers are numbered from 0 through the window size 1Program places the parameters in registers 4 7Subroutine gets the parameters from its registers 0 3xi only available to main program, In only to subroutine

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From Essentials of Computer Architecture by Douglas E. Comer. ISBN 0131491792. 2005 Pearson Education, Inc. All rights reserved.

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From Essentials of Computer Architecture by Douglas E. Comer. ISBN 0131491792. 2005 Pearson Education, Inc. All rights reserved.

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From Essentials of Computer Architecture by Douglas E. Comer. ISBN 0131491792. 2005 Pearson Education, Inc. All rights reserved.

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From Essentials of Computer Architecture by Douglas E. Comer. ISBN 0131491792. 2005 Pearson Education, Inc. All rights reserved.

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