Chapter 7 Sequential Circuits
Transcript of Chapter 7 Sequential Circuits
Chapter 7 Chapter 7 ppSequential CircuitsSequential Circuits
Jin-Fu LiAdvanced Reliable Systems (ARES) Lab.
Department of Electrical EngineeringN ti l C t l U i itNational Central University
Jungli, Taiwan
Outline
Latches & RegistersS qu ncin Timin Di mSequencing Timing Diagram
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Sequencing Combinational logic
Output depends on current inputsp p pSequential logic
Output depends on current and previous inputsOutput depends on current and previous inputsRequires separating previous, current, futureCalled state or tokensCalled state or tokensEx: FSM, pipeline
CL
clk
in out
clk clk clk
CL CL
PipelineFinite State Machine
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Sequencing ElementsLatch: Level sensitive
A.k.a. transparent latch, D latchp ,Flip-flop: edge triggered
A k a master-slave flip-flop D flip-flop D A.k.a. master slave flip flop, D flip flop, D register
Timing Diagrams pch Q
clk clk
QTiming DiagramsTransparentOpaque
D
Flo
Latc Q D Q
OpaqueEdge-trigger
clk
D
Q (latch)
Q (fl )
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Q (flop)
Latches Negative-level sensitive latch
DQ
clk0
1 D
clkQ
Positive-level sensitive latch
Q0
clk
DD
Q1
clk Q
D
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RegistersPositive-edge triggered register (single-phase clock)p )
lk
00DQM D
clk
clk
1Q
Sclk
1S QM
clkclk
Q
master slavemaster slave
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Registers Operations of the positive-edge triggered register g
clk=0
clk=1
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Registers CMOS circuit implementation of the positive-edge triggered registerg gg g
D
Q
clk clk
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Single-Phase Latch Positive active-static latch
-clk
D Q 1. Low area cost2 D i i bili f
clk2. Driving capability of
D must override the feedback inverter
-clk
D Qclk
clk
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-clk
Typical Latch Symbolic Layouts
Vdd
D Q
clk
-clk Q-clk
lk
DQ
clk
lklk clk-clk
Vss
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CVSL (Differential) Style Register The following figure shows latches based on a CVSL structuren V L u u
An N and a P version are shown that are cascaded to form a registerg
-Q
clk
DQQ
clk
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Double-Edge Triggered Register Th f ll i fi h l t h th t b The following figure shows latches that may be used to clock data on both edges of the clock
L t h 1 L t h 2clk Latch 1clk
Latch 2
D -DQ2 -Q2
Q1 -Q1D D
clk clk
D -D
Q1clk
Q2clk
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Q1 Q2
Double-Edge Triggered Register Double-edge triggered register can be implemented by combining Latch 1 & Latch 2 p y gas follows
Latch 2
Q
Q2
-Q2
D
-Q
Q
-Q1
Q1clk
lk Latch 2 enabled
Latch 1clk Latch 1 enabled Latch 2 enabled
Q2=-Q2=low Q1=-Q1=high
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Asynchronously RegisterAsynchronously resettable register
clk t-clk -reset
Q
clk clk-clkclk
-clk -clkclk
D
clk
-reset
Q
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Q
Asynchronously RegisterAsynchronously resettable and settable register g
-clk -reset
Q
clk clk-clkclk
Q
lk
clk
D
-clk -clkclk
-set
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Dynamic Latches & RegistersDynamic single clock latches
clkDDD
clkclk
-Q-clk
DD
-clk-clk
Dynamic single clock registers
D
clk
-Q
-clk
Qclk-clk
D-clkclk
Q
-clk clk-clk clk
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Dynamic LatchesClock active high latch
X QD CLK
D X
Xn QnDn CLK
01
HH
10
01
CLK Q 10
LL 1
Xn-1 Qn-1
Qn-1
Clock active high latch with buffer
D X
CLK -Q
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Dynamic LatchesClock active low latch
D X QD CLK
CLK
D
X Q
Xn QnDn CLK
01
LL
10
01
X Q10
HH
0 Xn-1
Qn-1
Qn-1
Clock active low latch with buffer
CLK
D
X -Q
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Dynamic LatchesClock active high and low latches without feedback
CLK
D
CLK
D X
Q
X Q
The problem of leakage currentAssume that the capacitance of node X is 0.002pF p pand the leakage current I is 1nA
Therefore, T=CV/I=0.002pFx5V/1nA=100usThat is, the latch needs to be refreshed each 100us. Otherwise, the output Q will become hi h
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high
Sequencing Methods Flip-flops2-Phase Latches
Flip-Fl
clk
Tc
Pulsed Latches
ops
Flop
Flop
clk clk
Combinational Logic
φ1
φ
2-Phase Tran Tc/2
tnonoverlap tnonoverlap
atch
φ2
atch
atch
φ1 φ1φ2
nsparent Latche CombinationalL i
CombinationalL iLa
φp
La La
esP
ulsed
Logic Logic
tpw
Half-Cycle 1 Half-Cycle 1
φp φp
Latches
Combinational Logic
Latc
h
Latc
h
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Timing Diagrams
A tpdCombinational
LogicA YContamination and Propagation Delays
Yg
clk clk
tcd
tsetup t
tpd Logic Prop. Delay
tcd Logic Cont. Delay
p g y
FlopD Q
clk
D
setup thold
tpcq
tpcq Latch/Flop Clk-Q Prop Delay
tccq Latch/Flop Clk-Q Cont. Delay
tpdq Latch D-Q Prop DelayQ
clk clk
tccq
tsetup thold
pdq
tpcq Latch D-Q Cont. Delay
tsetup Latch/Flop Setup Time
L t h/Fl H ld Ti
Latc
hD Q
clk
D
tccq
setup holdtpcq
tpdqtcdq
thold Latch/Flop Hold Time
Q
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Max-Delay: Flip-Flops
( )setuppd c pcqt T t t≤ − +
clk clk
sequencing overheadF1 F2Combinational Logic
T
Q1 D2
clk
Tc
tsetupt
Q1 tpd
tpcq
D2
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Max Delay: 2-Phase Latches
Q1 2 3
φ1 φ1φ2
Combinational CombinationalQ2 Q3D1 D2 D3
( )1 2
sequencing overhead
2pd pd pd c pdqt t t T t= + ≤ −
L1
φ
L2 L3
CombinationalLogic 1
CombinationalLogic 2
T
φ1
φ2
Tc
D1 tpdq1
Q1
D2
tpd1
tpdq2
Q2 tpd2
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D3
Max Delay: Pulsed Latches( )setup
sequencing overhead
max ,pd c pdq pcq pwt T t t t t≤ − + −
Q1 Q2D1 D2
φp φp
Combinational LogicL1 L2
Tc
D1 tpdq
Q1
D2
(a) tpw > tsetup tpd
D2
φp
tpw
Q1
D2
(b) tpw < tsetup
Tctpcq
tpd tsetup
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D2
Min-Delay: Flip-Flops
holdcd ccqt t t≥ −clk
CLF1
clk
Q1
clk
D2
F2
D2
clk
Q1 tcdtQ1
D2
cd
thold
tccq
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Min-Delay: 2-Phase Latches
1, 2 hold nonoverlapcd cd ccqt t t t t≥ − −φ
CLQ1
φ1
L1
Hold time reduced by nonoverlap
D2
φ2
L2
Paradox: hold applies twice each cycle, vs. only once for flops
φ1
tnonoverlap
t
only once for flops.
But a flop is made of two latches!
Q1
φ2
tcd
tccq
D2 thold
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Min-Delay: Pulsed Latches
holdcd ccq pwt t t t≥ − +
φHold time increased
CLQ1
φp
L1
by pulse width
φp
D2
L2
Q1
φp tpw
t
thold
tQ1
D2
tcdtccq
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Time BorrowingIn a flop-based system:
Data launches on one rising edgeg gMust setup before next rising edgeIf it arrives late, system failsf , y fIf it arrives early, time is wastedFlops have hard edgesFlops have hard edges
In a latch-based systemData can pass through latch while transparentData can pass through latch while transparentLong cycle of logic can borrow time into nextAs long as each loop completes in one cycleAs long as each loop completes in one cycle
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Time Borrowing Example
φ1
φ2
φ1 φ1φ2La
tch
Latc
h
Latc
h
Combinational Logic CombinationalLogic(a)
Borrowing time acrosshalf-cycle boundary
Borrowing time acrosspipeline stage boundary
(b) atch
atchCombinational Logic Combinational
Logic
φ1 φ2
(b) La La
g Logic
L b ti i t ll b t t l t ithi th l
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Loops may borrow time internally but must complete within the cycle
How Much Borrowing?
Q11 2
φ1 φ2
Combinational Logic 1Q2D1 D2
L1
φ1
L2Combinational Logic 1
( )borrow setup nonoverlap2cTt t t≤ − +
2-Phase Latches
φ1
φ2Tc
tnonoverlap
2
Pulsed Latches
D2
Tc/2 Nominal Half-Cycle 1 Delay
tborrowtsetup
borrow setuppwt t t≤ −
Pulsed Latches
D2
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Clock SkewWe have assumed zero clock skewClocks really have uncertainty in arrival timeClocks really have uncertainty in arrival time
Decreases maximum propagation delayIncreases minimum contamination delayIncreases minimum contamination delayDecreases time borrowing
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Skew: Flip-Flops
F1 F2
clk clk
Combinational Logic
Tc
Q1 D2( )setup skew
e e i e he d
pd c pcqt T t t t≤ − + +
clk
Q1
tskew
tsetup
tpcq
t d
sequencing overhead
hold skewcd ccqt t t t≥ − +Q1
D2
clk
setuptpdq
CLF1
Q1
clk
F2
c
D2
tskew
Q1
clk thold
tccq
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D2 tcd
Skew: Latches
Q1
L1 L2 L3
φ1 φ1φ2
Combinational CombinationalQ2 Q3D1 D2 D3( )2t T t≤
2-Phase Latches
L
φ1
L LLogic 1 Logic 2( )sequencing overhead
1 2 h ld l k
2
,
pd c pdq
d d
t T t
t t t t t t
≤ −
≥ − − +φ2
( )
1 2 hold nonoverlap skew
borrow setup nonoverlap skew
,
2
cd cd ccq
c
t t t t t t
Tt t t t
≥ +
≤ − + +
( )setup skewmax ,pd c pdq pcq pwt T t t t t t≤ − + − +Pulsed Latches
sequencing overhead
hold skewcd pw ccqt t t t t≥ + − +
( )borrow setup skewpwt t t t≤ − +
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Two-Phase ClockingIf setup times are violated, reduce clock speedpIf hold times are violated, chip fails at any speedspeedIn this class, working chips are most importantimportant
No tools to analyze clock skewAn s t nt h ld tim s is t s An easy way to guarantee hold times is to use 2-phase latches with big nonoverlap times
ll h l k ( h h )Call these clocks φ1, φ2 (ph1, ph2)
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Safe Flip-FlopIn class, use flip-flop with nonoverlapping clocks
Very slow – nonoverlap adds to setup timeBut no hold times
In industry, use a better timing analyzerAdd buffers to slow signals if hold time is at riskAdd buffers to slow signals if hold time is at risk
φ2 Qφ1
D X Qφ2 φ1
φφ
φ
φ1
φ
φ2
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φ1φ2
Clock DistributionIn a large CMOS chip, clock distribution is a serious problemu p m
For example,Vdd=5Vdd
Creg=2000pF (20K register bits @ 0.1pF)Tclk=10nsTrise/fall=1nsIpeak=C(dv/dt)=(2000p)x(5/1n)=10AP =C(V )2f=2000px25x100=5WPd=C(Vdd)2f=2000px25x100=5W
Methods for reducing the values of Ipeaknd Pand Pd
Reduce Cl h /f ll
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Interleaving the rise/fall time
Clock DistributionClocking is a floorplanning problem because clock delay varies with position on the chipy p pWays to improve clock distribution
Physical designPhysical designMake clock delays more evenAt least more predictable
Circuit designMinimizing delays using several stages of drivers
Two most common types of physical clocking networks
H-tree clock distributionBalanced-tree clock distribution
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H-Tree Clock Distribution
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clock
H-Tree Clock Distribution
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Source: Prof. Irwin
Balanced-Tree Clock Distribution
clock
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Reduce Clocking PowerTechniques used to reduce the high dynamic power dissipation
Use a low capacitance clock routing line such as metal3. This layer of metal can be, for example, dedicated to clock distribution onlyclock distribution onlyUsing low-swing drivers at the top level of the tree or in intermediate levels
C1 C2CA
Vdd
clkp -clkp
C
Vout
clkn
p
-clkn
p
C3 C4CB
Gnd
n n
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Clock
Power & Ground Distribution
Source: Prof. Irwin
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