Chapter 7 Register Counters

8/12/2019 Chapter 7 Register Counters

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Register, Counters and Memory unit

Chapter 7



A register is a group of flip-flops, each one of which is capable

of storing one bit of information.

An n-bit register consists of a group of n flip-flops capable of

storing n bits of binary information.

Register



When CP=1, then input transfer to Q (A).

Q follows Input as long as CP=1.

CP=0, Q will not changed,even though input is changed

Fig. .1! "-bit Register

Q

Q

Q

Q

"- bit Register



• oad=0, output will

!e the sa"e state.

Fig. .#! "-bit Register with parallel loa$.

A "-bit register with parallel %oa$



• A register capa!le of shifting the !inar# infor"ation held in each cell to its

neigh!oring cell, in a selected direction, is called a shift register

• $he logical configuration of a shift register consists of a chain of flip%flops

in cascade, with the output of one flip%flop connected to the input of the

ne&t flip%flop.• All flip%flops receive co""on cloc' pulses, which activate the shift of data

fro" one stage to the ne&t.

• erial input to eft"ost lip%flop

• erial output to *ight"ost lip%flop

Fig. .! &hift Register

&hift Register



CP+ A- (Cloc' hift

control)A circulate to prevent the

loss of infor"ation./&p+

A+ 0

1+ 0002%!it four cloc' pulse

needed.

After $2, contents of Atransfer to 1.

Fig. .'! &erial transfer from Register A to Register (

&erial transfer from one Register to another



CP+ A- (Cloc' hift control)A circulate to prevent the loss of infor"ation.

/&p+ A+ 0

1+ 000 2%!it four cloc' pulse needed. After $2, contents of A transfer to 1.

&erial transfer from one Register to another



(i$irectional shift register with parallel loa$



Counter

Ripple!

A series connections of complementing FFs.

)utput of each FF connecte$ to the CP of ne*t FF.

&ynchronous Counter! CPs are applie$ to all FFs at the same time



Ripple Counter! (inary Counter

%ogic 1



$he flip%flop transitions indeed follow a se3uence of

states as speciation+

Q changes state after each cloc' pulse.

Q4 complements! Ql goes to 0 5 Q6 = 0.

When Q6 = , Q goes to 0, Q4 is 0.

Q2 complements! Q4 goes fro" to 0.

Q6 co"ple"ents+ Ql. Q2= 5 Q goes fro" to 0.

Q6 is clear if Q2 or Q4 is 0 and Q goes fro" to 0.

Ripple Counter! (C+ Counter 1



Ripple Counter! (C+ Counter 1



Fig. .1! "-bit synchronous binary counter.

A Co"ple"ent+ At each cloc/ pulse

A1 Co"ple"ent+ if Present A=

A# Co"ple"ent+ if Present A1A=

A0 Co"ple"ent+ if Present A#A1A=

&ynchronous Counter! (inary Counter



p

+own

C%2

A1

A#

A0

A"

Q

Q3

Q

Q3

Q

Q3

Q

Q3

For p Counter

p =

4e*t 5 input = Pre6ious output Q

For +own Counter

p =

4e*t 5 input = Pre6ious output Q

&ynchronous Counter! (inary p-+own Counter

Chapter 7 Register Counters

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