Chapter 6 Sequential Logic

Chapter 6Sequential Logic

Combinational circuit outputs depend on present inputs.

Sequential circuit outputs depend on present inputs and the state of the memory elements.

CombinationalCircuit

Memory

OutputsInputs

Sequential Circuit

Sequential Logic

Flip-Flop - a storage (memory) element. A flip-flop circuit has two outputs, one normal form and one complemented. It may haveone or two inputs, depending on type. Clock, preset and clear functions may also be present. One flip-flop stores one binary bit.

R Q

S Q

S R Q Q

1 0 1 00 0 1 00 1 0 10 0 0 11 1 0 0X Y Z

0 0 10 1 01 0 01 1 0

NOR

1) Logic 1 on S sets Q to 1.2) Logic 1 on R resets Q to 0.3) Logic 1 on both S, R produce anindeterminate result.

Q S R Q ( T+1)

0 0 0 00 0 1 00 1 0 10 1 1 Indeterm1 0 0 11 0 1 01 1 0 11 1 1 Indeterm

Characteristic Table

Q

Q

R

CP

S

S QCP

R Q

Clocked RS Flip-Flop

When CLK = 1

S = 0, R=0 HoldS= 0, R=1 Q 0S = 1, R = 0 Q 1S = 1, R= 1 not allowed

0 0 d 1

1 0 d 1

S

R

SR

Q

Q Q(t + 1) = S + RQ SR= 0

SR must equal 0 so that S and Rcannot both be 1 simultaneously

Q = present state Q(t + 1) = next state

Indeterminate states can be considered as don’t cares since either a 1 or a 0 may result after S and R both equal 1.

D

CP

S

Q

Q

Q D Q(t+1)0 0 00 1 11 0 01 1 1

Characteristic Table

D QCP

Q

1

1

D

Q

Q( t + 1) = D

D Flip-Flop

When CLK = 0, the flip-flop holdsWhen CLK = 1 D q Q

0 0 00 1 01 0 11 1 1

Q

Q

K

CP

S

R

J

JK Flip-Flop

J QCP

K Q

Characteristic Table0 0 1 1

1 0 0 1

J

K

Q

Q(t+1) = J Q + KQ

J K q Q(t+1)0 0 0 00 0 1 10 1 0 00 1 1 01 0 0 11 0 1 11 1 0 11 1 1 0

Hold

Reset

Set

Invert

Q

Q

T

CP

S

R

T Flip-Flop

Invert

T q Q(t+1)0 0 00 1 11 0 11 1 0

Hold

Characteristic Equation

1

Q 1Q ( t + 1) = T Q + T Q

T QCP

Q

* Synchronous: behavior can be defined from the knowledge of signals at discrete instants of time. A master clock is used, only change during a clock pulse.

* Asynchronous: behavior depends on the order in which input signals change. Can be changed at any time.

Level Triggering: Flip-Flop sensitive to pulse durationEdge Triggering: Flip-Flop sensitive to pulse transition

(solves feedback timing problems)

1

0Positive edge

Negative edge

Triggering of Flip-Flop

Master-Slave Flip-Flops: Contains two separate flip-flops

S

R

S Q

CP

R QMaste

rS Q

QR

CPSlave

Q

Q

Problem: Instability occurs if output of memory elements (FF’s) are changing while output of combinational circuit that go to the Flip-Flop inputs are being sampled by the clock pulse.

InputsOutputCP FF

Comb.Logic

Propagation delay from Flip-Flop input to output must be greater then clock pulse duration.

Input

Output

CP

S

Y

Q

Output state change occurs on the negative clock transition.

Mealy vs. Moore machines

Control Logic

Register (Flip-flops)

Output Logic

Inputs

Outputs

A collection of flip-flops is called a register.

The value of the flip-flops defines the state of the machine.

Mealy machine:

The output is a function of the state of the machine and of the inputs.

Moore machine:

The output is a function only of the state of the machine.

Moore = Output only a function of the state.

Clock

A synchronous state machine

Control Logic


Output Logic

Inputs

Outputs

Clock

Presume all flip-flops are positive edge-triggered.

1) The controls are “captured” on the positive edge2) It takes a little time (nS) for the flip-flops to settle to the new state3) The new state affects the control logic

4) External inputs are changing, also affecting the control logic5) The next positive edge occurs and the cycle repeats

State Transition DiagramThe state transition diagram is a graphical representation of the machine changes from one state to another in reaction to the inputs.

A state transition diagram is often the first step in the design of a synchronous state machine.

StateName

In/OutIn/Out

A color sequence SSMRed

Blue

Gray

Tan

0/0

0/1

1/10/0

0/0

1/0

1/0

1/0

Red /0

Blue /0

Gray /1

Tan /0

0

0

10

0

1

1

1

Mealy machine Moore machine

When is the output valid?

Control Logic


Output Logic

Inputs

Outputs

ClockSince a Moore machine’s outputs are a function only of the state of the machine, its outputs are always valid except during transitions

Since a Mealy machine’s outputs are a function of the state of the machine and the inputs, its outputs are valid only immediately after a transition.

Most designs will latch (capture) the output of a Moore machine in an output register to provide them to the rest of the system.

Characterizing a SSMRed

Blue

Gray

Tan

0/0

0/1

1/10/0

0/0

1/0

1/0

1/0

Red /0

Blue /0

Gray /1

Tan /0

0

0

10

0

1

1

1

Number of states: 4 Number of flip-flops: 2Number of inputs: Number of outputs: 1 1

Input = 0: Red-Blue-Gray-Tan-Red-…Input = 1: Red-Tan-Blue-Gray-Red-...

State Transition TableThe state transition table is a tabular representation of the machine changes from one state to another in reaction to the inputs. The state transition table has the same information as the state transition diagram.

X=0 X=1

Red Blue/0 Tan/0

Blue Gray/1 Gray/1

Gray Tan/0 Red/0

Tan Red/0 Blue/0

Red

Blue

Gray

Tan

0/0

0/1

1/10/0

0/0

1/0

1/01/0

Inputs define the columns

Stat

es d

efin

e th

e ro

ws

J QCP

K Q

Preset

Clear

PR

CL

Direct Inputs

State DiagramsState: The condition (values) stored in the flip-flops of asequential circuit.Present State: The condition of the flip-flops prior to a clock pulse.Next State: Condition of the flip-flops after a clock pulse

a

d

c

b

1/0 1/1

0/11/0

0/0

0/0

0/0

1/0

state

transition between states which occurs

with a clock pulse.

X/Y x= input which causes transition. y = output during present state.

Contains the same information as a state diagram

Present state Next State

X = 0 X = 1Output X = 0 X = 1

a 0 0 c b 0 0 b 0 1 c b 1 0 c 1 0 d c 0 0 d 1 1 c a 0 1

In general, a state table for m flip-flops will have 2m

rows, one for each state. The next state and output section will have 2n columns each for n inputs.

External outputs can be taken from flip-flop output or from logic gates. If there are no logic gates for output, theoutput columns can be deleted. The output is then read directly from the present state of the flip-flops.

State Table

Goal: reduce the number of flip-flops in a sequential circuit.


X = 0 X = 1Output X = 0 X = 1

a a b 0 0 b c d 0 0 c a d 0 0 d e f 0 1 e a f 0 1 f g f 0 1 g a f 0 1

Equivalent states = same input gives the same output for each state and the transitions go to the same state.In example above state g = state e . . . . .

State Reduction

. . . . . and state f = state d.


X = 0 X = 1Output X = 0 X = 1


State Reduction

e

. . . . . and state f = state d.


X = 0 X = 1Output X = 0 X = 1


State Reduction

edd

State Assignment

Some state assignment schemes can reduce the combinational portion of a sequential circuit. However, thereare no state assignment techniques which guarantee minimization.

Suggestion:1) For counters use the sequence of binary numbers

for state assignments.2) Otherwise, make arbitrary assignments.

Characteristic tables define next state - when the input and present state are known .

Excitation tables define the input conditions required to make a desired transition from a known present state to a a desired next state.

Q S R Q ( T+1)

0 0 0 00 0 1 00 1 0 10 1 1 Indeterm1 0 0 11 0 1 01 1 0 11 1 1 Indeterm

SR Characteristic Table

Q Q(t + 1) S R

0 0 0 d 0 1 1 0 1 0 0 1 1 1 d 0

SR Excitation Table

Flip-Flop Excitation Tables

Q J K Q ( t+1)

0 0 0 00 0 1 00 1 0 10 1 1 11 0 0 11 0 1 01 1 0 11 1 1 0

JK Characteristic Table

Q Q(t + 1) J K

0 0 0 d 0 1 1 d 1 0 d 1 1 1 d 0

JK Excitation Table

Q D Q(t + 1)

0 0 00 1 11 0 01 1 1

D Characteristic Table

Q Q(t + 1) D

0 0 00 1 11 0 01 1 1

D Excitation Table

Goal: obtain a logic diagram or list of Boolean functions which describe a sequential circuit meeting the design specification.

1) Write a word description. Draw a state diagram.2) Construct a state table.3) Perform state reduction.4) Make state assignments.5) Determine number of ff required and assign a letter to each.6) Select type of ff to use.7) Construct circuit excitation and output tables.8) Reduce Boolean functions.9) Draw the logic diagram.

Sequential Design Process

Design a circuit to implement the following state diagram.

a

d

c

b

1/1 1/0

0/0

1/1

1/1

0/1

0/1

0/0

Example

2) Conduct a state table.


X = 0 X = 1Output X = 0 X = 1

a a b 1 1 b c b 0 1 c c d 1 1 d d a 0 0

3) Perform state reduction. None possible.

4) Make state assignments.

a = 0 0 b = 0 1 c = 1 0 d = 1 1

5) Determine number of flip-flops required 4 states required 2 flip-flops (2n = 4)

6) Select flip-flop type. Choose T. (TA, TB)

7) Construct excitation and output tables.

Inputs of combinationalcircuit

Output of combinationalcircuit

Present State Input Next State FF inputs Output A B X A B TA TB Z 0 0 0 0 0 0 0 1 0 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0 1 1 0 1 0 0 1 1 0 0 1 0 0 0 1 1 0 1 1 1 0 1 1 1 1 0 1 1 0 0 0 1 1 1 0 0 1 1 0

aabbccdd

Using: Q Q(t + 1) T

0 0 00 1 11 0 11 1 0

8) Reduce Boolean Functions.

0 0 0 1

0 0 1 0A

B

TA = A B X + A B X

X

TB = B X + AX + A B X0 1 0 1

0 1 1 0A

B

X

1 1 1 0

1 1 0 0A

X

B

Z = B + A X

9) Draw the logic diagram.

T Q

Q

T Q

A BQ

TA A A TB B B

XInput

ZOutputConbinational Circuit

ABX TA

ABX

TB

Z

BX

AX

AX

B

Design a sequential circuit using the following state table:


X = 0 X = 1Output

X = 0 X = 1

0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 1 0 0 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 1 0 0 1 0 1 1 0 0 0 1 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 1 1

3 flip-flop are requires for 5 states. There will be 3 numberedstates (000, 110, 111). Letter the ff A,b, C. Construct an excitation table for RS ff.

Example

Present State Input Next State Flip-Flop Inputs Output A B C X A B C S A R A S B R B S C R C Y

0 0 0 0 d d d d d d d d d d0 0 0 1 d d d d d d d d d d 0 0 1 0 0 0 1 0 d 0 d d 0 00 0 1 1 0 1 0 0 d 1 0 0 1 00 1 0 0 0 1 1 0 d d 0 1 0 00 1 0 1 1 0 0 1 0 0 1 0 d 00 1 1 0 0 0 1 0 d 0 1 d 0 00 1 1 1 1 0 0 1 0 0 1 0 1 01 0 0 0 1 0 1 d 0 0 d 1 0 01 0 0 1 1 0 0 d 0 0 d 0 d 11 0 1 0 0 0 1 0 1 0 d d 0 01 0 1 1 1 0 0 d 0 0 d 0 1 11 1 0 0 d d d d d d d d d d1 1 0 1 d d d d d d d d d d1 1 1 0 d d d d d d d d d d1 1 1 1 d d d d d d d d d d

Use the SR excitation table to complete the circuit excitation table:

Q Q(t +1) S R 0 0 0 d 0 1 1 0 1 0 0 1 1 1 d 0

Reduce Boolean function:

BA

C

X

d d 0 0 0 1 1 0 d d d d d d d 0

CXAB

SA = BX

BA

C

X

CXAB

RA = CX

d d d d d 0 0 d d d d d 0 0 0 1

Others SB = A B XRB = B C + B X S C = XR C = XY = A X

Draw the logic diagram:

S Q

R QACP

S Q

R QBCP

S Q

R QBCP

XInput

Y Output

SA

RA

SB

RB

SC

RC

CP

A

A

B

B

C

Don’t Care States

0 0 1

0 1 1

1 0 1

0 0 0

0 1 0

1 1 0

1 1 1

1 0 0

0/0

0/0

0/0

0/0

0/0

1/0

1/0

1/0

1/1

??

??

??

What about don’t care states?•Self-Correcting: all unused states eventually lead to valid states. (some designs may specify self-correcting in one clock pulse.) •Self-starting: initial state on power up is specified. Usually a master reset input is used. It is customary to provide a master-reset input whose purpose is to initialize the states of all flip-flops in the system. Typically, the master reset is a signal applied to all flip-flops asynchronously before master-reset signal, but some may be set to 1. •Q: What if, because of a noise signal the circuit finds itself in an invalid state? In that case it is necessary to ensure that the circuit eventually goes into one of the valid states so it can resume normal operation.

Don’t Care States

• It was stated previously that unused states in a sequential circuit can be treated as don’t-care conditions.

• Once the circuit is designed, the m flip-flops in the system can be in any of 2 possible states.

• Some of these states were taken as don’t cares conditions.

• The circuit muse be investigated to determine the effect of these unused states. The next state from invalid sates can be determined.

Don’t Care States

0 0 1

0 1 1

1 0 1

0 0 0

0 1 0

1 1 0

1 1 1

1 0 0

0/00/0

0/0

0/0

0/0

0/0

0/0

1/0

1/0

1/0

1/0

1/11/1

0/0

0 0 1

0 0 0

1 0 0 0 1 1

0 1 0

1/1 0/0

0/0

1/1

1/1

1/0

0/00/0

0/0

1/1

Design Problem

Example Problem: Design with T Flip-Flops

0 0 0 0 0 1 1 0 1 1 00 0 0 1 1 0 0 1 0 0 10 0 1 0 0 0 1 0 0 0 0 0 0 1 1 1 0 0 1 0 1 10 1 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 1 0 1 0 1 1 0 0 0 1 0 1 0 00 1 1 1 0 1 0 0 0 1 11 0 0 0 0 1 0 1 1 0 01 0 0 1 0 1 1 1 1 1 01 0 11 0 1 1 1 0 1 1 01 1 11 1 1

Present State Input Next State Flip-Flop Inputs Output A B C X A B C TA TB TC

Unused States

Need3 Flip-Flopsto Get 5 States

0 0 1

0 0 0

1 0 0 0 1 1

0 1 0

1/1 0/0

0/0

1/1

1/1

1/0

0/00/0

0/0

1/1

Don’t Care States ??

1 1 1

1 1 0

1 0 1

BA

C

X

CXAB

0 1 1 0 0 0 0 0 d d d d 1 1 d d

TA = A + BX

BA

C

X

CXAB

1 0 0 0 0 1 0 1 d d d d 1 1 d d

TB = A + B C X + B C X + B C X

A

C

X

CXAB

1 0 1 0 0 0 1 0 d d d d 0 1 d d

TC = AX + CX + A B C X

A

C

X

CXAB

0 1 1 0 0 1 1 0 d d d d 0 0 d d

Z= AX

TQ

Q

TQ

Q

TQ

Q

Prob 6-20 CONTDA

BX

A

BC

X

B

X

B

C

B

XC

A

A

X

CX

TC

C

C

B

A

Z

To Gates

To Gates

To Gates

To Gates

To Gates

To Gates

TB

TA

X

A

*Note Clock Pulseis assumed

Prob CONTINUED

Now, we must analyze circuit to confirm that unused states are in fact “Don’t Cares” Analyzes Procedure is:1) Start w/Logic Diagram2) Formulate FF input Equations3) Derive next state equations using FF characteristics EQ.4) Formulate transition table (state table w/binary #’s)5) Formulate state diagram.

1) Logic Diagram on previous Page2) TA = A + BX QA = A TB = A + BC X + B C X + B C X QB = B TC = AX + CX + A B C X QC = C

3) T F-F Char. EQ: Q(t +1) = TQ + TQ

A = (A + B X) A + (A + BX) A A B X + [ A (B + X) ] AA B X + (A B + A X) A

A B X

B = (A + B C X + B C X + B C X) B + (A + B C X + B C X + B C X) BAB + B C X + [ A (B + C + X) (B + C + X) ( B + C + X) ] BAB + B C X + [ BA (B + BC + BX) (BC + BX) (BC + BX) ]AB + B C X + [B A + A B C + A B X) (BC + BX) (BC + BX)AB + B C X + [A B C + A B X + A B C + A B X + A B C X + A B X) (B C + B X)AB + B C X + A B C X + A B C X

B = A B + A C X + A B C X

A

CCXAB

1

X

B1

1 1 1 1

1

C = (AX + CX + A B C X) C + ( A X + C X + A B C X) CA C X + A B C X +[ (A + X) (C + X) (A + B + C + X) ] C A C X + A B C X + (C A + C X) (C X) (C A + C B + C + C X) A C X + A B C X + ( C A X + CX) ( CA + CB + C + CX)A C X + A B C X + C A X B + C A X + C X A + C X B + CXA C X + A B C X + C A X ( B + 1) + C X A + C X B + C XA C X + A B C X + A C X + A CX + B C X + C X

A

CCXAB

X

B11

1

1

1 1

1

C = CX + A C X + A B X

0 0 0 0 0 1 1 0 0 0 0 1 1 0 0 10 0 1 0 0 0 1 0 0 0 1 1 1 0 0 10 1 0 0 0 1 0 0 0 1 0 1 0 0 0 1 0 1 1 0 0 0 1 00 1 1 1 0 1 0 1 1 0 0 0 0 1 0 01 0 0 1 0 1 1 01 0 1 0 0 1 1 0 1 0 1 1 0 1 0 0 1 1 0 0 0 0 0 01 1 0 1 0 0 1 01 1 1 0 0 0 1 0 1 1 1 1 0 0 0 0

Present State Input Next State Output A B C X A B C

4)

5)

0 0 1

0 0 0

1 1 1

1 0 0 0 1 1

1 0 10 1 0

1 1 0

1/01/1 0/0

0/0

1/00/0

0/0

0/0

1/0

1/1

1/1

1/1

1/0

0/00/0

Unused state are “Don’t cares” since they all go to valid states. Other 5 states producesame state diagram as original.

0/0

Alternate way to get next states for “Don’t Cares”

0 1 1 0

0 0 0 0

d 12 d 13 d 15 d 14

1 1 d11 d10

1 0 0 0

0 1 0 1

d 12 d 13 d 15 d 14

1 1 d11 d10

TA TB

1 0 1 0

0 0 1 0

d 12 d 13 d 15 d 14

0 1 d11 d10

TC

0 1 1 0

0 1 1 0

d 12 d 13 d 15 d 14

0 0 d11 d10

Z

PS Input NS OutputABC X A B C Z1 0 1 0 1 0 1 11 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1

Example: Design a circuit to recognize this bit pattern: … 0 1 1 0 1 … When the position is recognized, return to a starting point (or points). Circuit should be self- starting and self - correcting.

X Y = 1 when pattern is recognized Input

pattern

Sequential circuit

g

h

d

e

b

ba

c

1/0

1/01/00/0

0/0

0/00/0

1/1

1/0

0/0

1/0

1/01/0

0/00/1

a = 1’st digit = 0, correctb = 1’st digit = 1, incorrectc = 2’nd digit correctd = 3’rd digit correcte = 4’th digit correctf = all digits correct pattern recognizedg = unused state.h = unused state.

Present State X = 0 X = 1 X = 1 X = 0 A B C A B C A B C Y Y

Next State Output

a 0 0 0 0 0 0 0 1 0 0 0b 0 0 0 0 0 0 0 0 1 0 0c 0 1 0 0 0 0 0 1 1 0 0 d 0 1 1 1 0 0 0 0 1 0 0 e 1 0 0 0 0 0 1 0 0 0 0f 1 0 1 0 0 0 0 0 1 1 1g 1 1 0 0 0 0 0 0 1 0 0 k 1 1 1 0 0 0 0 0 1 0 0

Date reduction shows b, g, h as equivalent states; however, 3flip-flops are still required.Implement the circuit with JK flip-flops.

Q Q(t+1) J K 0 0 0 d0 1 1 d1 0 d 1 1 1 d 0

Present State Input Next State Flip-Flop Inputs Output A B C X A B C J A K A J B K B J C K C Y

0 0 0 0 0 0 0 0 d 0 d 0 d 00 0 0 1 0 1 0 0 d 1 d 0 d 00 0 1 0 0 0 0 0 d 0 d d 1 00 0 1 1 0 0 1 0 d 0 d d 0 00 1 0 0 0 0 0 0 d d 1 0 d 00 1 0 1 0 1 1 0 d d 0 1 d 0 0 1 1 0 1 0 0 1 d d 1 d 1 00 1 1 1 0 0 1 0 d d 1 d 0 0 1 0 0 0 0 0 0 d 1 0 d 0 d 0 1 0 0 1 1 0 1 d 0 0 d 1 d 01 0 1 0 0 0 0 d 1 0 d d 1 1 1 0 1 1 0 0 1 d 1 0 d d 0 1 1 1 0 0 0 0 0 d 1 d 1 0 d 0 1 1 0 1 0 0 1 d 1 d 1 1 d 0 1 1 1 0 0 0 0 d 1 d 1 d 1 0 1 1 1 1 0 0 1 d 1 d 1 d 0 0

A

C

B d d d d d d d d

1

X

A

C

B

d d d d d d d d

X

1 1 1 11 1 1

KA= B + C + X

A

C

B d d d d d d d d

1

XJB = A C X

A

C

B

d d d d

d d d d

X

1 1 1 1

KB= B + C + X

1 1 1

A

C

B 1 d d 1 d d

XJC = BX + AX

d d

1 d d

A

C

B d d

d d

XKC = X

d d 1

d d

111

A

C

B

X

1 1

Y = ABC

J Q

K QACP

J Q

K QACP

J Q

K Q

ACP

cp

cp

cp

A

A

B

B Y

C

C

CP

X

A Clocked sequential circuit has 2 inputs, X1, and X2, and one output, Z. The output should equal 1 if and only if the inputsagree and have agreed for an even non-zero (2,4,6, …) numberof clock pulses since the last pulse when they disagreed.

Convert the two inputs into a single input, D, that equals 1 when X1 & X2 disagree.

X1

X2

d Z

CLK

A

B

1/0

1/00/0

0/1

2 states: How many F-F? (1)

0 0 1 0 1 d0 1 0 0 0 d1 0 0 1 d 11 1 0 0 d 1

A Input A Output FF InputsNS

1 0d d J = D

1 0d d K = 1

D

A

D

A1 0d d K = AD

D

A

J Q

K Q

ACP

cp

X1

X2 Z

1

Prepare a state diagram for a sequential circuit whose output, Z, equals 1 if and only if input sequence has either 1001 or 11as its most recent subsequence.

A B

D C

1/1

0/0

1/0 0/0

1/0

0/0

0/0 1/1

One’s

1&0

1 & 0 & 0

A single-input, single-output clocked sequential circuit is toproduce an output of 1 coincident with a Ø - input, provided that the Ø - input is immediately preceded by at least two consecutive 1-inputs

A C

B

0/0

0/1

1/0

0/0 1/0

1/0

A = 00B = 01C = 10

PS Input NS Outputs A B X A B JA KA JB KB Z

0 0 0 0 0 0 d 0 d Ø0 0 1 0 1 0 d 1 d Ø 0 1 0 0 0 0 d d 1 00 1 1 1 0 1 d d 1 01 0 0 0 0 d 1 0 d 11 0 1 1 0 d 0 0 d 0 1 1 0 d d d d d d d1 1 1 d d d d d d d

A

B

0 0 1 0

d d d d A

B

1 0 d d

d d d d

A 0 0 d d

0 1 d d

JA= BX KA = X

B

X

KB = 1

A 1 0 d d

0 0 0 0

B

X

Z = AX

B

J Q

K B

A

J Q

K B 1

Try different state assignment:

PS Input NS Outputs A B X A B JA KA JB KB Z

1 1 0 1 1 d 0 d 0 01 1 1 0 1 d 1 d 0 0 0 1 0 1 1 1 d d 0 00 1 1 0 0 0 d d 1 00 0 0 1 1 1 d 1 d 10 0 1 0 0 0 d 0 d 0 1 0 0 d d d d d d d1 0 1 d d d d d d d

A

d d 0 1

1 0 d dJA= X

X

A

0 1 d d KA = X

X

d d d d

B B

A

d d d d JB = X

X

1 0 d d

B

A

0 0 1 0 KB =BX

X

d d d d

B

Z=AX

B

J Q

K B

A

J Q

K B

X

State Equations

Sometimes called “Next-State Equations”- A(t + 1) = (AB + AB + AB)X + Abx

Next State of a F-F Boolean Functions specifying present state

condition that make the next state of the Flip-Flop be 1.

(that is, if this function = 1, the next clock pulse will cause the output, 1, of the flip-flop to be 1]

- Can be derived from a State Table or Logic Diagram- State equations plus output function(s) fully specify a sequentialcircuit.

State Equation Derivation

- From a state table:

Next State Output

Present State x = 0 x = 1 x = 0 x = 1

AB AB AB y y

0 0 0 0 0 1 0 00 1 1 1 0 1 0 0 1 0 1 0 0 0 0 11 1 1 0 1 1 0 0

Read off next-state columns for A, Alternating from input Ø to input 1 and put directly into K-Map

1

1 1 1

0 0 0 1 1 1 1 0

0

1A

1

0 0 0 1 1 1 1 0

0

1A

11

1

A( t + 1) = Bx’ + (B + x’) A = Bx’ + (Bx’)’ A

a)B( t + 1) = A’x + (A’ + x) B = Ax + (Ax’)’ B

a)

Form of Rs flip-flop: q(t + 1) = S + R Q

State Equation Derivation

- Form a logic Diagram:

R Q’

S Q

R Q’

S Q

1

2

3

4

x’A

xA’

xB’

x’B

A

A’

B

B’

CP

- For flip - flop B: R = AX S = A X

-Substitute into RS F-F characteristic equation: Q(t + 1) = S + RQ

Gives B(t + 1) = Ax + (Ax) B(which is same as got with state table derivation)

Use of state Equations

- Have to use when doing analyses, such as checking validity of design that used “Don’t Cares”

- Convenient for design when circuit is alrady specified in this form or when the equations are easily derived from the state table. -- Easy eith D flip-flops

-- Sometimes convenient with JK flip-flops -- Possible with RS and T flip-flops but requires

considerable algebraic manipulation.

State Reduction: Another Method

PS NS Output X=0 X=1

A d c 0b f h 0c e d 1d a e 0e c a 1f f b 0g b h 1h c g 1

b

c

d

e

f

g

h

d- fc -h

a b c d e f g

- Go thru & set up a table- If intersection of too states is at an “x”, theycannot be equal; Put an xin that block.- Continue passes thru table until nothing left to cross out- Blocks with no X reflectequal States.

Example: a b iff d f and c h

a c because outputs differ

Chapter 6 Sequential Logic

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Transcript of Chapter 6 Sequential Logic