Chapter 5 Transistor

8/6/2019 Chapter 5 Transistor

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OBJECTIVES

After stu dying th e ma ter ial in th is cha pter , you will be able to describe and/or a na lyze:

th e need for biased a nd signa l sta bilizing circuitry,

comm on-emitt er am plifier circuit s u sing volta ge divider bias ing,

comm on-emitt er a mplifier circuits using em itter biasing,

comm on-emitt er am plifier circuit s u sing volta ge feedback biasing,

RC coupled mu ltista ge amplifiers,

direct coupled mu ltista ge amplifiers, and

tr oubleshooting pr ocedures for t ra nsist or circuits.

In t he previous chapter you st udied the bipolar t ra nsistor a nd learned how to make a simple

am plifier circuit. Our study was limited, however, in tha t we a ssumed a n ideal tra nsistor a nd

considered only single-sta ge amplifiers. In th is chapt er, we will consider t ra nsist or limita tions

and multistage amplifier circuits.

Q-POINT INSTABILITY CAUSED BY BETA ____________________________________

Becau se man ufacturer s can not produce tr an sistors with a pr ecise beta value and becau se beta a lso

chan ges with environment al condit ions, th e exact value for beta is unknown. The typical beta, given

on data sheets, is an approximation. The actual beta for the individual transistor can range from

min us 50% to plus 100% of the typical beta given by th e man ufactu rer . Exa mple 5.1 shows how the

acceptable range of beta is calculated.

EXAMPLE 5.1

161

TransistorCircuits5

5.1 INTRODUCTION

If a transistor has a typical beta of 150, what is the acceptable range of beta for the

transistor?


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EXAMPLE 5.1 cont inu ed

A transistor with a typical beta of 150 is considered good if its actual beta is within the range

of 75 t o 300.

The beta of a tr ansistor a lso varies with chan ges in temperat ure. Figure 51 shows a graph

of beta versus tempera tu re. For a n operational temperat ure of0C, the beta of the 2N3904 is

140, an d at a t empera tu re of 100C, th e beta is 220.

In order for a tr an sistor amplifier circuit to be useful, th e circuit must be stable and predictable.

With no signal applied to the amplifier circuit, the amplifier is in the quiescent state. At

quiescence, the voltage across the transistor (VCE) and the current through the transistor (IC)

should be constant. When the signal is applied to a class-A amplifier, the signal will cause

variations around the quiescent point, also referred to as the Q-point. It is the function of the

bias circuit to hold the circuit stable at the designed Q-point. Example 5.2 shows how the

base-biased am plifier is not effective at holding th e Q-point consta nt with chan ges in beta.

EXAMPLE 5.2

240

200

160

120

0 20 40 60 80 100

Beta

Temp

FIGURE 51 Beta versus temperature

Step 1. Calculate the minimum beta:

min = typical (typical 50%) = 150 (150 50%) = 75

Step 2. Calculate the ma ximum beta :

max = typical + (typical 100%) = 150 + (150 100%) = 300

Calculate the values ofIc and VCE for the transistor amplifier in Figure 52, assuming

th e tra nsist or has a beta of (a) 100 an d (b) 180.

Step 1. Calculate IC and Vc for a beta equal t o 100.

IB = VRb/ R b = 9.3 V/930 k = 10 A

Ic = Ib = 100 10 A = 1 mA

VRc = Ic R c = 1 mA 5 k = 5 V

Vc = Vcc VRc = 10 V 5 V = 5 V

162 Chapter 5 Transistor Circuit s


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THE VOLTAGE DIVIDER ____________________________________________________

A simp le volta ge divider circuit can be used t o provide referen ce volta ge. Two resis t ors connected

in series can provide an y volta ge level below th e supply volta ge at t he junction of th e tw o resis tors

by adjusting the ratio of the resistors. If the junction point is connected to other circuitry, the

volta ge at th e junction ma y drop becau se of th e loading effect of th e add ed circuitr y. However,

if th e resist an ce of the adde d circuitr y is high compa red t o the resist ors in t he volta ge divider,

th e voltage load ing may be negligible. Exa mple 5.3 illust ra tes h ow a lightly load ed volta ge divider

circuit can maintain a near constant output voltage.

EXAMPLE 5.3

Step 2. Calculate IC and Vc for a beta equal t o 180.

IB = VRb/ R b = 9.3 V/930 k = 10

Ic = Ib = 180 10 A = 1.8 mA

VR c = Ic R c = 1.8 mA 5 k = 9 VVc = Vcc VRc = 10 V 9 V = 1 V

VCC = 1 0 V

Rc5 kRb

930 k

RL

5 k

FIGURE 52 Base-biased amplifier

Calculate t he volta ge at t he junctions ofR 1 and R 2 for both circuit s shown in Figur e 53

an d deter mine t he percent age of cha nge in voltage caused by adding th e load.

Step 1. Ca lculat e th e volt age at th e test point for th e circuit in Figu re 53(a). The circu it

is an u nloaded volta ge divider, and th e volta ge at t he tes t point can be calcula te d

by using th e volta ge divider form ula.

Vout = Vin R 2/(R 1 + R 2) = 12 V 2 k/x0 k + 2 k) = 2 V

Step 2. Calculate the voltage at the test point for the circuit in Figure 5 3(b). The

para llel equivalent resista nce (REQ) of R 2 and the load resistor must first be

calculat ed before the volta ge divider form ula can be us ed.

REQ = R 2 || RL = 2 k || 20 k = 1.82 k

Vout = Vin REQ/(R 1 + REQ )

Vout = 12 V 1.82 k/(10 k + 1.82 k) = 1.85 V

5.1 INTRODUCTION 163


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The volta ge divider circuit in Figu re 53(b) can be considered a light ly loade d volta ge divider

because the load resistor is t en t imes the resistance ofR 2. The load causes t he voltage at the

jun ction of th e volta ge divider t o drop by 7.5%. Loads with highe r re sist an ce will caus e a sm aller

drop in volta ge, an d loads with lower r esista nce will cause a great er dr op. A good rule of th um b

is to consider t he volta ge divider light ly load ed if th e load is ten t imes or great er t he valu e of th e

par allel resist or (R 2 in t his case). For light ly loaded volta ge dividers, the volta ge at th e junction

of th e divider can be appr oximat ed using t he simple volta ge divider form ula.Figure 53(b) shows th at the conventional curren t thr ough R 1 divides, and a port ion of the

current flows through R 2 while the remainder flows through the load resistor. If the voltage

divider is lightly loa ded, most of th e cur ren t will flow th rough R 2, and less tha n 10% of the curr ent

will flow through the load.

The am plifier circuit sh own in Figur e 54(a) use s volta ge divider bia sing. This met hod of bias ing

ha s proven t o be a popula r way to design bipolar t ra nsist or a mplifiers. The circuit counter actsth e effects of th e uncert ain ty of beta . For DC bias an a lysis, th e circuit can be simp lified as shown

in Figure 54(b) becau se th e capacitors are considered open t o the DC bias curr ent s.

The nam e voltagedividercomes from th e fact t ha t t he base volta ge is provided by a volta ge divider

form ed by R b1 and R b2. The voltage at th e junction ofR b1 and Rb2 holds the base voltage const an t.

The circuit is always designed so th e base current (IB) is less than 10%ofth e current flowing th rough

R b2. Therefore, the volta ge divider is es sent ially not loaded by th e bas e curr ent flow.

Since th e volta ge divider form ed by R b1 and R b2 is light ly load ed, th e base volta ge (VB) can be

easily calculated by using the simple voltage divider formula. The base/emitter junction is

forwar d-biased. Therefore, the emitt er volta ge (VE) will be one junction drop different than the

5.2 VOLTAGE DIVIDER BIASING

Step 3. Calculate t he percent of cha nge in voltage caused by loading t he volta ge divider

circuit.

% = V/V 100%

V

= 2 V 1.85 V = 0.15 V% = 0.15 V/2 V 100% = 7.5%

12 V

R1

10 k TP= 2 V

R2

2 k

(a)

IR1

12 V

R110 k

TP = 1.85 V

IRLR22 k

RL20 k

(b)

IR2

FIGURE 53 Voltage divider circuit



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base voltage. Once th e voltage on t he emitt er is kn own, the emitt er current (IE) can be easily

calculat ed u sing Oh ms la w, since R e is connected between the emitter and ground. The collector

current (IC) can be approximated, since it is almost th e sam e as t he emitt er current . With the

collector cur ren t kn own, th e collector volta ge (VC) can be calculated.

The preceding paragraph gave the procedures for calculating all of the bias voltages and

currents for a voltage divider biased amplifier. Note that the calculations were completely

independent of the beta of the transistor. This means the voltage divider biased amplifier will

ma intain a consta nt Q-point (IC will be const an t) even with la rge changes in bet a. The circuit

design does depend on a minimum beta, but we can be sure the engineer designed the circuit for

the minimum beta of the transistor. Example 5.4 will show you how easy it is to calculate the

bias volta ges and cur ren ts for a volta ge divider biased a mplifier circuit .

EXAMPLE 5.4

VCC

= 1 0 V

Rc5 k

Rb146 k

RL5 kRe

1 k

Rb210 k

FIGURE 55 Voltage divider biased amplif ier circuit

VCC

= 10 V

Rc

5 k

RL

5 kRe1 k

Rb1

46 k

Rb2

10 k

(a)

VCC= 10 V

(b)

Rb1

46 k

Rb2

10 kRe

1 k

Rc

5 k

FIGURE 54 Voltage divider biasing

Calculate VB, VE, IE, IC, VC, and VCE for the amplifier circuit in Figure 55.

Step 1. Calculate t he base volta ge (VB). Since th e bas e volta ge divider is light ly loaded,

we can use t he simple volta ge divider form ula.

5.2 VOLTAGE DIVIDER BIASING 165


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Volta ge divider bias ing use s cur re nt -mode feedback to st a bilize th e circuit. The cur ren t flowing

th rough th e emitt er r esistor causes nega tive feedback and st abilizes th e circuit. Volta ge divider

biasing is a pra ctical way to ma ke th e bias circuitr y independent of beta . This appr oach is not

th e only means of sta bilization, but it is one of th e most popular.

The pr ice paid for independen ce from beta is a decrease in signa l voltage gain. Fortu na tely, these

lower voltage gains ar e predictable. The input impedance is also affected, but it increases, an d in

most cases this is a plus. We will discuss each of these parameters and then look at some examples.The size and th e type of resist an ce in th e emitt er leg ha s a grea t effect on the operat ion of th e

voltage divider amplifier. There are five types of resistances in the emitter leg, each of which is

defined in the following list. As you continue with the chapter, use this list to make sure you

understand the type of emitter resistance being discussed.

r 'e is the inter na l signal resista nce of th e base/emit ter jun ction (r'e = 25 mV/IE).

R e is an extern al emitt er resistor th at opposes signa l curr ent (AC) an d bias

curr ent (DC).

R E is an extern al emit ter r esistor th at only opposes bias curren t (DC).

5.3 SIGNAL PARAMETERS IN VOLTAGE DIVIDER CIRCUITS

VB = Vcc R b2/(R b1 + R b2)

VB = 10 V 10 k/(46 k + 10 k) = 1.8 V

Step 2. Calculate th e emit ter volta ge (VE). The base/emitter junction is forward-biased.

The circuit is using a silicon NPN transistor, so the base must be 0.7 V morepositive tha n th e emitter.

VE = VB VBE

VE = 1.8 V 0.7 V = 1.1 V

Step 3. Calculate t he emitter current (IE) and collector curr ent (IC). Ohms la w can be

used to calculate the emitter current, since RE(total) is connected between the

emitter a nd ground.

IE = VE/ RE(total) (RE(total) = R e in th is case.)

IE = 1.1 V/1 k = 1.1 mA

IE IC(Base curren t is sma ll; th erefore, IE is approxima tely equa l to IC.)

IC 1.1 mA

Step 4. Calculate th e collector voltage. With t he collector curr ent known, th e volta gedrop across R c can be calculated. If th e volta ge across R c is subtra cted from the

supply voltage (VCC), th e volta ge on t he collector can be foun d.

VRc = Ic R c = 1.1 mA 5 k = 5.5 V

Vc = Vcc VRc = 10 V 5.5 V = 4.5 V

Step 5. Calculate the collector to emitt er voltage (VCE). The voltage across the t ransistor can

be calculated byfinding the difference in voltage between the collector and the emitter.

VCE = VC VE

VCE = 4.5 V 1.1 V = 3.4 V



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r e is the tota l signa l (AC) resist an ce in th e emitt er leg an d is equal to r'e plus R e.

RE(total) is the t ota l bias (DC) resista nce in th e emitt er leg an d is equa l to RE plus R e.

INPUT IM PEDANCE ________________________________________________________

The genera l form ula for inpu t impeda nce is z in = rb || re. Resistance rb is the equivalent signal

resist an ce to groun d on t he base leg, an d re is the equivalent signa l resistan ce to ground on the

emitter leg. Figure 56(a) shows a voltage divider biased amplifier circuit. From the perspective

of the signal genera tor, resistors RB1 and RB2 appear in parallel as shown in Figure 56(b).

Remem ber th e power supply bus is at signal ground. This para llel combina tion is shown a s rb in

Figu re 56(c).

The pa th th rough th e reverse-biased base/collector junction is considered an open. Figure

56(b) shows that the values ofr'e and R e ar e seen th rough the forward-biased base/emitter

junction. The r esista nce re is the ser ies equivalent ofr'e and R e as s hown in F igur e 56(c). The

signal resista nce (re) in the emit ter leg mu st be mu ltiplied by th e valu e of bet a as shown in Figur e

56(c). Exa mple 5.5 sh ows h ow inpu t impedan ce of a volta ge divider bias ed a mplifier can be

calculat ed using circuit va lues.

EXAMPLE 5.5

VCC

RcRb1

Re

RLRb2

(a)

zin Rb1 Rb2

(b)

Re

r'e

r R Rb b= ||b1 2

zin rb re

r r' R e e e= +

(c)

FIGURE 56 Input impedance of t he voltage divider circuit

Assum e a beta of 100 and calculat e the in put impedan ce of th e circuit in Figure 57.

VCC = 10 V

Rc

5 k

RL5 kRe

1 k

Rb146 k

Rb2

10 k

FIGURE 57 Voltage divider biased amplif ier circuit

5.3 SIGNAL PARAMETERS IN VOLTAGE DIVIDER CIRCUITS 167


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Step 1. Calculate t he biased emitter current . The biased emitter current is needed to

calculat e th e value ofr'e.


VB = 10 V 10 k/(46 k + 10 k) = 1.8 V

VE = VB VBE

VE = 1.8 V 0.7 V = 1.1 V

IE = VE/RE(total) (RE(total) = R e in th is case.)

IE = 1.1 V/1 k = 1.1 mA

Step 2. Calculate the signal resistance of the base/emitter junction.

r'e = 25 mV/IE = 25 mV/1.1 mA = 23

Step 3. Draw an equivalent circuit showing how R b1, R b2, R e, and r'e appear from the

perspective of the signal generator. The equivalent circuit is shown in Figure

58.

Step 4. Calculate t he signal resista nce in th e base leg (rb).

rb = R b1 || R b2 = 46 k || 10 k = 8.2 k

Step 5. Calculate t he signal resistance in the emitter leg (re).re = r'e + R e = 23 + 1 k = 1023

Step 6. Multiply the emit ter leg signa l resistan ce times bet a. (Assum e beta equa ls 100.)

re = 100 1023 = 102.3 k

Step 7. Draw the simplified equivalent circuit showing the base signal r esista nce in

paral le l with the emit ter pa th s ignal res is tance. The equivalent circu i t is

shown in F igure 59.

Step 8. Calculate t he circuit inpu t impeda nce by finding th e par allel equivalent of th e

signal base resistance and t he signal emitt er pat h resistan ce.

z in = rb || re = 8.2 k || 102.3 k = 7.6 k

zinR R

b b1 2

46 k 10 k

r'

R

e

e

23

1 k

FIGURE 58 Input impedance equivalent circuit

zin rb8.2 k

102.3 k

re

FIGURE 59 Simplified equivalent circuit



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Two point s should be n oted. First , if th e value ofR e is large in compa rison to th e value ofr'e,

then r'e can be dropped from t he calculat ion. Second, note th at beta is still in the equat ion, but

by exam ining Examp le 5.5, you can see th at th e signa l base r esista nce (rb) is the main influence

on input impedan ce. Becau se of th is, changes in beta do not h ave a dr am at ic effect.

VOLTAGE GAIN OF THE VOLTAGE DIVIDER BIASED AM PLIFIERThe general formula for the voltage gain of the common emitter amplifier is A v = rc/ re, where

re is the signa l resist an ce in the emitt er leg an d rc is th e signal res ist an ce in th e collector leg. In

th e base biased circuit, the only signal resista nce in the emit ter leg is r'e. In t he voltage divider

circuit, the signal resist an ce in th e emitt er leg (re) is equa l to r'e plus R e, wher e R e is equal to the

un bypassed resist an ce in the em itter leg. The signal resista nce in the collector leg rc is equal t o

R c in para llel with RL. Example 5.6 shows how the voltage gain of a circuit can be calculated

from circuit component values.

EXAMPLE 5.6

Calculate t he volta ge gain of th e circuit in F igure 510 .

Step 1. Calculate t he signa l resista nce in the collector leg.

rc = R c || RL = 5 k || 5 k = 2.5 k

Step 2. Calculate th e signa l resistan ce of th e base/emit ter jun ction.


VB = 10 V 10 k/(46 k + 10 k) = 1.8 V

VE = VB VBE

VE = 1.8 V 0.7 V = 1.1 V

IE = VE/ RE(total) (RE(total) = R e in th is case.)

IE = 1.1 V/1 k = 1.1 m

r'e = 25 mV/IE = 25 mV/1.1 mA = 23

Step 3. Calculate t he signal resistance in the emitter leg.

re = r'e + R e = 23 + 1000 = 1023 or 1.023 k

Step 4. Calculate t he volta ge gain (A v).

A v = rc/ re = 2.5 k/1.023 k = 2.44

VCC = 1 0 V

R

R

R

C

L

e

5 k

5 k

1 k

Rb146 k

Rb2

10 k2 Vp-p

FIGURE 510 Voltage divider biased amplif ier

5.3 SIGNAL PARAMETERS IN VOLTAGE DIVIDER CIRCUITS 169


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The value ofr'e has little affect on the voltage gain of the circuit as long as R e is much larger

than r'e. The volta ge gain is great ly redu ced, but t he gain is predicta ble becau se it is indep enden t

ofr'e. In t he following sections you will lear n te chniqu es to regain s ome of th e lost ga in an d still

have circuit stability.

Once the volta ge gain of an am plifier is known, the outpu t signa l can be easily calculated by

mu ltiplying the input signal by th e volta ge gain. It should be noted th at t he out put signa l swing

is limited by the power supply voltage and the Q-point. A good rule of thumb to follow for

estimating th e maximum peak-to-peak signal swing is t o calculate the voltage across the

tra nsistor a t quiescence (VCE) and multiply this value by t wo. If the calculated outpu t signal

exceeds th is value, clipping will occur on th e peak s of th e out put signa l. Exa mp le 5.7 shows how

to calculate the output signal a nd t he ma ximum outpu t swing.

EXAMPLE 5.7

Since th e out pu t signa l (4.88 Vp-p) is less than t he calculated ma ximum output swin g (6.8 Vp-p ),

th e out put signal will not be clipped.

There a re thr ee variat ions of the voltage divider biased amplifier: the u nbypassed, t he fully

bypassed, and the split emitter. The bias circuitry on all th ree variat ions functions t he sa me.

The difference is in the signal par am eters . We will exam ine each varia tion and work an example

of each.

UNBYPASSED VOLTAGE DIVIDER BIASED AM PLIFIER ________________________

The circuit in F igure 511 is the unbypassed voltage divider biased am plifier . This is t he

sam e circuit we ha ve studied in th e previous sections. Making two as sum ptions will simplify

the circuit calculations. First, no value is given for the beta of the transistor in the circuit.

Rather than wasting time looking it up, let us assume beta equals 100. One hundred is a

reasonable guess of beta for low and medium power transistors. Second, the unbypassed

resistor in the emitt er (R e) is large compa red t o r'e, so r'e will be negligible. These assumptions

perm it us to use a pra ctical appr oach to calculate t he bias an d signa l para met ers of th e volta ge

divider am plifier circuit u sing component va lues. The an swer s ma y not be precise becau se of th e

5.4 VARIATIONS OF VOLTAGE DIVIDER BIASED AM PLIFIERS

Calculate t he out put s ignal and th e maximu m output swing for th e circuit in Figur e 510 .

Step 1. Calculate t he output signal.

Vout = Vin A v = 2 Vp-p 2.44 = 4.88 Vp-p

Step 2. Calculate VCE. The valu e ofVE was calcula ted in E xample 5.5 and equa ls 1.1 V.

The value ofVc needs t o be calculat ed.

VRc = Ic R c = 1.1 mA 5 k = 5.5 V (IE Ic was calculat ed in Exa mple 5.5.)

Vc = Vcc VRc = 10 V 5.5 V = 4.5 V

VCE = Vc VE = 4.5 V 1.1 V = 3.4 V

Step 3. Calculate t he ma ximum outpu t swing.

maximum Vout p-p = 2 VCE = 2 3.4 V = 6.8 Vp-p



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assumptions made, but they will be close enough to use in troubleshooting. Example 5.8

demonstr at es this approach.

EXAMPLE 5.8

VCC = 1 6 V

R

R

R

C

L

e

4 k

10 k

1.5 k

Rb2

15 k

Rb150 k

FIGURE 511 Unbypassed voltage divider biased amplifier

Analyze the circuit in Figure 511 . Calculat e (a) th e DC bias volta ges for VB, VE, Vc, and

VCE, an d (b) th e signal volta ge gain (A v), input impedan ce (z in ), out put impedan ce (zout ),

and the approximat e maximum signal output voltage swing.

Step 1. Calculate the DC biased voltages and currents.


VB = 16 V 15 k/(50 k + 15 k) = 3.7 V

VE = VB VBE = 3.7 V 0.7 V = 3 V

IE = VE/RE(total) = 3 V/1.5 k = 2 mA (RE(total) = R e in th is case.)

IC Ie = 2 m

VRC = IC R c = 2 mA 4 k = 8 V

Vc = Vcc VRC = 16 V 8 V = 8 V

VCE = Vc VE = 8 V 3 V = 5 V

Step 2. Calculate the signal input impedance.

R b = R b1 || R b2 = 15 k || 50 k = 11.5 k

re R e = 1.5 k (R e is large compa red t o r'e.)

z in = rb || re

z in = 11.5 k || 100 1.5 k

z in = 10.7 k

Step 3. Calculate t he output impedance.

zout = R c = 4 k

Step 4. Calculate t he volta ge gain.

rc = R c || RL = 4 k || 10 k = 2.86 k

A v = rc/ re

A v = 2.86 k/1.5 k = 1.9

Step 5. Calculate the maximum outpu t signal swing. An approximat ion of the out put

peak-to-peak s ignal swing equals 2 VCE.

VCE = 5 V

Therefore:

Maximum out put swing = 2 5 V = 10 Vp-p

5.4 VARIATIONS OF VOLTAGE DIVIDER BIASED AMPLIFIERS 171


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THE FULLY BYPASSED AM PLIFIER __________________________________________

The voltage divider biased amplifier using a n unbypassed emitt er r esistor (R e) is stable and

predictable but h as a great ly redu ced volta ge gain wh en compa red t o th e base biased am plifier.

The volt age gain of th e base bias ed am plifier is in the r an ge of 50 to 500, but th e volta ge gain ofth e un bypassed volta ge divider biased circuit is in th e ra nge of 2 to 10. In this section we will

examine a circuit that retains the bias stability but has high voltage gain.

The circuit in Figure 512 is identical to the circuit in Figure 511 , except t ha t a capa citor ha s

been added that bypasses the emitt er resistor (RE). The capa citor is an open for DC bia s, hen ce,

the biased curr ents and voltages ar e un chan ged by t he addition of the bypass capacitor. The

circuit ret ains good Q-point sta bility, but th e volta ge gain is grea tly increased.

Note the bypassed emitt er resist or is called RE with a capital E subscript. This denotes th at

th e resistor will exist for th e DC biased curr ent bu t will appea r as a sh ort for th e signa l cur ren t.

An unbypassed emit ter r esistor will be denoted as R e an d will exist for both biased cur ren t s (DC)

an d signal current s (AC).

The volta ge gain is equa l to th e rat io ofsigna l resista nce in th e collector leg to signa l resista nce

in the emit ter leg (A v = rc/ re). In th e unbypassed circuit, the signal resist an ce in the em itt er legis equal to r'e plus the signal emitt er resist or. The bypass capacitor short s out t he emitt er resistor

for th e signa l, leaving th e signa l resistan ce in the em itt er leg equal to r'e. With only th e value of

r'e in th e emitter leg, the voltage gain retu rns to the high voltage gain obta ined with t he base

biased circuit.

The addition of the bypass capacitor will cause a decrease in input impedance. The output

impedan ce will not be affected. Exam ple 5.9 illustr at es how signal values can be calculat ed for

the fully bypassed amplifier.

EXAMPLE 5.9

VCC = 1 6 V

RL

10 k

RC4 k

R

R

b

b

1

2

50 k

15 k

R

E

1.5 k

FIGURE 512 Bypassed voltage divider amplifier

Calculate t he input impedan ce, out put im pedan ce, and th e volta ge gain for th e circuit inFigure 512 .

Step 1. Calculate r'e.


VB = 16 V 15 k/(50 k + 15 k) = 3.7 V

VE = VB VBE = 3.7 V 0.7 V = 3 V

IE = VE/RE(total) = 3 V/1.5 k = 2 mA (RE(total) = RE in th is case.)

IC Ie = 2 mA

r'e = 25 mV/IE = 25 mV/2 mA = 12.5



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The circuits in Examples 5.8 and 5.9 are identical except for the addition of the bypass

capacitor. The addit ion of th e bypass capacitor ma kes a dr am at ic change to the volta ge gain a nd

inpu t im peda nce. The volta ge gain goes up from 1.9 to 232, an d th e input imped a nce goes down

from 10.7 k to 1.13 k. The increase in volta ge gain is generally considered a plus th at would

probably out weigh th e disadvant ages of lowering the input impedan ce.H owever, th e volta ge gain

is now dependent on r'e, which ma kes it less predictable. The inpu t impedan ce is not only lower

but now is dependent on r'e and , which makes it less predicta ble th an it was in the un bypassed

circuit. Signal distortion is another disadvan ta ge of th e fully bypassed circuit. Figure 513 shows

an exam ple of signal distort ion th at is easily seen when th e out put signa l has a large swing.Th e

distortion is caused by fluctuations in r'e an d directly a ffects th e volta ge gain of the a mplifier.

The fluctua tions in r'e ar e cau sed by th e wide var iat ions in emitt er current . On the positive swing

of the input, the emitter curren t increases, cau sing r'e to decrea se an d th e volta ge gain to increase.

On th e negative swing of th e input , th e emitter cur ren t decreases, causing r'e to increase and th e

volta ge gain t o decrea se.

The fully bypass ed circuit is us ed in low cost circuit ry wher e the h igh volta ge gain r educes th e

nu mber of sta ges needed, ther efore, cut tin g cost. The price paid for th is lower cost is distortion,

un predictable volta ge gains, an d input impeda nces th at fluctu at e with cha nges in environmen ta l

conditions an d device par am eters.

Input 0 V

Output 0 V

100 mV

10 V

p-p

p-p

FIGURE 513 Signal distor tion

Step 2. Calculate t he input impedance.

rb = R b1 || R b2 = 50 k ||15 k = 11.5 k

re = r'e = 12.5 (RE is bypassed.)

z in = rb || re = 11.5 k || (100 12.5 ) = 1.13 kStep 3. Calculate t he output impedance.

zout = R c = 4 k


rc = R c || RL = 4 k || 10 k = 2.9 k

A v = rc/ re = 2.9 k/12.5 = 232

5.4 VARIATIONS OF VOLTAGE DIVIDER BIASED AMPLIFIERS 173


14/42

THE SPLIT-EMITTER AM PLIFIER ____________________________________________

The split-emitter amplifier is a compromise between the fully bypassed and the unbypassed voltage

divider am plifier. Figur e 514 shows a split-emitter am plifier. The resistor in th e emitt er leg has

been split into two parts: R e and RE. Resistor RE is bypassed with a capa citor an d is considered t o

be zero ohm s when calculat ing signal par am eters. Resistor R e is un bypassed an d mu st be consider ed

when calculating signal parameters. The total value of the DC resistance (R e + RE) in t he emitterleg is the sa me a s it was in th e circuits in Figures 511 an d 512, an d th e DC curr ent s an d voltages

ar e also the sa me. Exam ple 5.10 will show th e differences in signal par am eters.

EXAM PLE 5.10

V

R

R

CC

e

E

= 1 6 V

100

1.4 k

R

R

b1

b

50 k

15 k

2

Rc

4 k

RL10 k

FIGURE 514 Split -emitter voltage divider amplif ier

Calculate the input impedance, output impedance, and voltage gain for the circuit in Figure

514.



VB = 16 V 15 k/(50 k + 15 k) = 3.7 V

VE = Vb Vbe = 3.7 V 0.7 V = 3 V

IE = VE/RE(total) = 3 V/1.5 k = 2 mA (RE(total) = R e + RE.)

IC Ie = 2 mA

r'e = 25 mV/IE = 25 mV/2 mA = 12.5


rb = R b1 || R b2 = 50 k || 15 k = 11.5 k

re = r'e + R e = 12.5 + 100 = 112.5 z in = rb || re = 11.5 k || (100 112.5 ) = 5.7 k


zout = rc = 4 k


rc = R c || RL = 4 k || 10 k = 2.9 k

A v = rc/ re = 2.9 k/112.5 = 26



15/42

The split-emitter am plifier ha s values of voltage gain a nd inpu t im pedance between t hose of the

fully bypassed and the unbypassed circuits. The predicta bility of the signal param eters is also

between th e oth er two circuits. The am ount of th e emitter resistor left un bypassed determines t he

voltage gain and predictability of the circuit. Because the designer has the ability to control voltage

gain a nd signal par am eter predicta bility, the split-emitter voltage divider circuit ha s become a

popular circuit in electronic systems.

SUMM ARY OF VOLTAGE DIVIDER BIASING _________________________________

In order for t he t ra nsist or a mplifier to be a pr actical circuit, it is n ecessar y to use a biasing circuit

th at will sta bilize the Q-point . In order to mak e the Q-point st able, the DC collector curr ent mu st

be independent of beta. This can be accomplished by using voltage divider biasing. There are three

var iat ions of volta ge divider biasin g circuit s: th e unbypassed circuit with volta ge gains in the ra nge

of 2 to 10 but with excellent signal parameter predictability, the fully bypassed circuit with voltage

gains in th e range of 50 to 500 but with unpredictable signa l para meters, an d th e split-emitt er circuit

with voltage gains in the range of 5 to 50 with good signal parameter predictability.

AM PLIFIER

Figure 515 shows circuits usin g emitt er bias for st abilization. The base is conn ected t o ground

th rough a rela tively low resista nce (R b). The base/emitter is forward biased by a negative power

supply (VEE) connected t o th e emitt er resist or (R e). Since the base current is small, the voltage drop

across the base resistor (R b) is negligible, and the base is considered to be at zero volts. The

forward-biased base/emitter junction drops to 0.7 V, so the emitter is at 0.7 V. This means the

current th rough the emit ter is deter mined by the value of th e negative supply an d the value of th e

emitt er resistor. Since the em itter curr ent is independent from changes in beta, th e circuit obta ins

st ability. One disadvantage of th e emitt er biased a mplifier is the need for a n emit ter su pply volta ge

(VEE). Exa mple 5.11 shows how the DC volta ge of th e emitt er biased a mplifier can be ca lcula ted.

EXAM PLE 5.11

VCC

= 1 5 V

Rc6.8 k

Re12 k

Rb

1 k

VEE = 15 V

FIGURE 515 Emit ter b iased amplif ier

5.5 EM ITTER BIASED AM PLIFIER

Calculate t he DC voltage VB, VE, and VC of the circuit shown in Figure 515.

Step 1. Determine t he base voltage. The base is a t zero voltage because the curr ent

through R b is consid ered negligible.

VB = 0 V

5.5 EMITTER BIASED AMPLIFIER 175


16/42


Figure 516 shows the same emitter biased amplif ier with an input signal and a load

connected. The signa l para met ers ar e calculated usin g th e same procedur e as the volta ge divider

amplifier. The emitter can be fully bypassed for high voltage gain or partly bypassed, which

reduces the gain but improves predictability and reduces distortion. Example 5.12 shows how

the signal para meters can be calculated.

EXAM PLE 5.12

Vcc

= 15 V

RL

10 k

Rc

6.8 k

RE

11.5 k

Re

500

VEE = 15 V

Rb 1 k

FIGURE 516 Emitter biased amplifier with split emitter

Step 2. Determine the emitter voltage. The base/emitter of the NPN transistor is

forwa rd biased, so th e emitt er mu st be 0.7 V negat ive with r espect to the base.

VE = 0.7 V

Step 3. Calculate t he collector curren t.IE = (VEE VBE)/R e = (15 V (0 .7 V))/12 k = 1.2 mA

(The negative sign can be dropped.)

IC IE = 1.2 mA

Step 4. Calculate the collector voltage.

VRc = IC R c = 1.2 mA 6.8 k = 8.2 V

Vc = Vcc VRc = 15 V 8.2 V = 6.8 V

Calculate the input impedance, output impedance, and voltage gain for the circuit in Figure

516 .


IE = 1.2 mA (Calculated in Example 5.11.)

r'e = 25 mV/IE = 25 mV/1.2 mA = 20.8


rb = R b = 1 k

re = r'e + R e = 20.8 + 500 = 520.8 (r'e is small and ma y be disregar ded.)

z in = rb || re = 1 k || (100 521 ) = 981



17/42


EEDBACK BIASED AM PLIFIER

Figure 517 shows circuits using voltage feedback for stabilization. Note that there is not a

resistor in the emitter leg. Voltage divider biasing using current-mode feedback is normally

preferred over voltage-mode feedback. However, for low voltage power supplies or when maxi-

mu m outpu t volta ge swings ar e necessar y, voltage-mode feedback ma y be preferr ed.Figure 517(a) shows a circuit opera tin g from a 4 V supply. A resist or (R b) is connected between

the collector and base. The base current is controlled by the voltage dropped across R b, which is

equa l to th e collector-to-bas e volta ge. If th e collector curr ent in crea ses, th e volta ge on th e collector

will decrease, reducing the voltage across R b. A reduced voltage across R b causes less base

curren t, which th en causes t he collector curren t t o decrea se. The opposite is also tr ue. A decrea se

in collector cur ren t caus es th e collector volta ge to increa se, which increas es the bas e cur ren t an d

causes t he collector curren t t o rise. The volta ge across t he tr an sistor (VCE) stabilizes a t a pproxi-

ma tely 2 V, and the rema ining supply voltage is dropped a cross R c. The voltage gain of the

amplifier is the same as the fully bypassed voltage divider circuit and can be calculated using

th e formula Av = rc/ re. Since there is no emitter resist or in th e circuit, re = r'e cau sing the volta ge

gain to be high. The input impedan ce is equal toR b divided by th e volta ge gain plu s one in par a llel

with r'e times beta [z in = (R b/ A v + 1) || (r'e )] . The reason R b appears t o be much sma ller tha nits actual size is because as the voltage goes up on the base end ofR b, the voltage is forced down

on the collector end ofR b. Millers t heorem sta tes th at th e effective impeda nce of a component

in t he n egative feedback loop of an am plifier is equa l to th e actu al impeda nce of the component

divided by th e volta ge gain plus one. The ma in adva nt age of th e circuit in Figur e 517(a) is its

ability to opera te wit h a low supply volta ge.

The circuit in Figure 517(b) uses volta ge-mode feedback. The second resist or in th e base circuit

(R b2) permit s a port ion of th e cur rent flowing th rough Rb1 to bypass the base. This permit s the circuit

V

Rcc

c

= 4 V

2 k200 k

RbRL10 k

V

Rcc

c

= 1 0 V

4.3 k43 k

6 k

R

R

b

b

1

2

RL

50 k

(a) (b)

FIGURE 517 Voltage-mode feedback amplif iers

5.6 VOLTAGE-M ODE FEEDBACK BIASED AM PLIFIER


zou t = R c = 6.8 k


rc = R c || RL = 6.8 k || 10 k = 4 kA v = rc/ re = 4 k/521 = 7.7

5.6 VOLTAGE-MODE FEEDBACK BIASED AMPLIFIER 177


18/42

to operate with a higher value of collector-to-emitter voltage (VCE). The circuit can be designed for

ideal midpoint biasing, permitt ing m aximum output signal swings. This type of voltage-mode

feedback is often used to drive power amplifier stages when maximu m swing is ofu tm ost import an ce.

In order to obtain the gain an electronic system needs, it is often necessary to connect amplifiers in

series. When am plifiers ar e connected in ser ies, they are s aid t o be cascaded. Figure 518 shows a

two-stage cascaded amplifier circuit. The two stages are both voltage divider biased amplifiers.

One met hod for coupling tr an sistor st ages t ogeth er is by using coupling capacitors bet weenst ages. This m eth od of coupling is called RC, or r esist an ce-capa citor, coupling. Coupling capa ci-

tors a ct like an open for biased curr ent s but a re a short for signal curr ent s. Becau se of th is, th e

biased circuitry in each sta ge is independent . The biased cur ren ts a nd volta ges can be calculat ed

in th e sam e man ner u sed for a single-st age am plifier.You simp ly consid er each sta ge individua lly.

The signal para meter s of a m ultista ge amplifier are easy to calculate if you rem ember t he

following facts. The input impedance of th e tota l circuit is equa l to th e input impedance of th e

first st age. The outpu t impeda nce of th e total circuit is equa l to th e out put im peda nce of th e fina l

stage of the system. The voltage gain of the total circuit is equal to the product of the individual

st ages. The outpu t signa l from the first st age will see th e input im peda nce of th e second stage as

its load resistan ce.

EXAM PLE 5.13

5.7 M ULTISTAGE RC COUPLED AM PLIFIERS

Ana lyze th e circuit in F igure 518 .

Step 1. Ana lyze each sta ge independent ly for t he biased volta ges.

First sta ge:

VB = Vcc R b2/(R b1+R b2) = 16 V 22 k/(37 k + 22 k) = 6 V

VE = VB VBE = 6 V 0.7 V = 5.3 V

IE = VE/RE(total) = 5.3 V/1.9 k = 2.8 mA

VCC

= 16V

Rc820

C3

RL

2.2 k

Re

82

C5RE

180

Rb112 k

Rb22.7 k

C2

Rc1.8 k

Re

100

C4R

E

1.8 k

Rb137 k

C1

Rb222 k

FIGURE 518 RC coupled ampli fier



19/42


YPASS CAPACITORS

Up to this point we have assu med th e capa citors in th e circuits to have zero impedan ce (Xc) for

signal curr ents and infinite impedance for biased currents. The impedance of a capacitor is

5.8 COUPLING AND BYPASS CAPACITORS

VRC = IC R c = 1.8 k 2.8 mA = 5 V

VC = VCC VR C = 16 V 5 V = 11 V

VCE = VC VE = 11 V 5.3 V = 5.7 V

Second s ta ge:VB = Vcc R b2/(R b1 + R b2) = 16 V 2.7 k/(12 k + 2.7 k) = 2.9 V

VE = VB VBE = 2.9 V 0.7 V = 2.2 V

IE = VE/RE(total) = 2.2 V/262 = 8.4 mA

VRC = IC R c = 820 8.4 mA = 6.9 V

VC = VCC VRC = 16 V 6.9 V = 9.1 V

VCE = VC VE = 9.1 V 2.2 V = 6.9 V

Step 2. Calculate the input impedance an d output impedance of each sta ge. Assume

beta t o equal 100 for both tr an sistors.

First stage:

rb = R b1 || R b2 = 37 k || 22 k = 13.8 k

r'e = 25 mV/IE = 25 mV/2.8 mA = 9

re = r'e + R e = 9 + 100 = 109

z in = rb || re = 13.8 k || (100 109 ) = 6 k

zou t = R c = 1.8 k

Second s ta ge:

rb = R b1 || R b2 = 12 k || 2.7 k = 2.2 k

r'e = 25 mV/IE = 25 mV/8.4 mA = 3

re = r'e + R e = 3 + 82 = 85

z in = rb || re = 2.2 k || (100 85 ) = 1.7 k

zout = R c = 820

Step 3. Calculate t he volta ge gain of each st age.

First stage:

rc = R c || RL = 1.8 k || 1.7 k = 874 (RL = z in of next stage.)

A v = rc/ re = 874 /109 = 8

Second s ta ge:

rc = R c || RL = 820 || 2.2 k = 597

A v = rc/ re = 597 /85 = 7

Step 4. Calculate t he input impedan ce, out put impeda nce, an d volta ge gain of th e total

am plifier circuit.

z in = z in of first s ta ge = 6 k

zout = zou t of last st a ge = 820 A v(total) = AV1 AV2 = 8 7 = 56

5.8 COUPLING AND BYPASS CAPACITORS 179


20/42

dependent on its capa cita nce and t he frequency of th e signal and is expressed as Xc = 1/(2Fc).

Any size capacitor will exhibit some ohms of impedance at any frequency. Engineers design

circuits so Xc is relatively small at the lowest operating frequency. Normally, technicians will

not have to calculate the size of the capacitors, but it is helpful to have a rule of thumb to

determine the approximate size. As a rule, Xc, at the lowest frequency, should be equal to

one-tent h or less oft he series impeda nce being driven by th e signa l pa ssin g th rough th e capa citor.

The signal passin g thr ough t he input coupling capa citor is driving z in of th e first sta ge of the

circuit, and the impedance of the coupling capacitor should be one-tenth of z in . The coupling

capacitor between st ages should ha ve an impeda nce of one-tent h ofz in of th e sta ge being driven.

The outpu t coupling capacitor should ha ve an impedan ce of one-tent h ofRL .

The purpose of the emitter capacitor is to bypass signal currents to ground. The parallel

combin at ion ofREan d the bypass capa citor should be one-tent h ofr'e for th e fully bypas sed circuit

or one-tenth ofre (r'e + R e) for t he split-emitt er circuit. Exam ple 5.14 will demonstr at e how this

ru le of thu mb can be used t o calculate th e size of coupling an d bypass capa citors. It should be

emphasized that the procedure to be used in Example 5.14 will result in estimated values that

perm it th e technician to select capa citors for experimen ta l circuits. En gineers use other calcu-

lat ion methods th a t resu lt in sma ller capa citor valu es th a t save money on comm ercially produced

circuits.

EXAM PLE 5.14

The results in Table 51 show the minimum size capacitor using our rule of thumb for

calculation. The next larger standard size capacitor can be used to construct the circuit. Since

Calculate t he size of th e coupling and bypass capacitors needed in th e circuit in Figur e

518 if th e lowest s igna l frequ ency to be am plified is 300 Hz.

Step 1. Determ ine the series resis ta nce being driven by ea ch capa citor. In Exam ple 5.13,

the input impedance an d th e value of signal resistance in the emit ter leg (re)

was calculated for each stage. These values are listed as the driven resistance

in Table 51.

TABLE 51

Capacitor Driven resistance XC(max) Capacitor value

C1 6 k (zin Q1) 600 0.9 F

C2 1.7 k (zin Q2) 170 3.1 F

C3 2.2 k (RL) 220 2.4 F

C4 109 (re Q1) 10.9 49 F

C5 85 (re Q2) 8.5 63 F

Step 2. Calculate t he ma ximum impeda nce of th e capa citor by ass um ing the capa citive

reactan ce (Xc) to equal one-ten th of the driven resist an ce value shown in Table

51.Step 3. Usin g 300 Hz, calcula te t he valu e of each capa citor using th e following formu la.

The calculation for the first capacitor is shown. Table 51 shows the calculat ed

values for all capacitors for the circuit shown in Figure 518 .

C1 = 1/(2 Xc F) = 1/(2 600 300 Hz) = 0.9 F



21/42

coupling a nd bypass capa citors with larger capacitan ce values will fun ction fine, often circuits

will use the same value for all coupling capacitors.

AM PLIFIERS

Capacitor coupled (RC coupled) amplifiers are popular because each stage has its own inde-

pendent ly biased circuit. Fluctu at ions in t he DC opera ting point in one stage is not am plified by

the next st age. Occasiona lly, however, it is necessary t o have an amplifier th at is capable of

am plifying DC curr ent s an d volta ges. In order to couple a DC signa l from one sta ge to the next,

it is n ecessa ry to rem ove th e coupling capa citor a nd conn ect th e output of one st age directly to

the input of the next. Emitter-bypass capacitors are removed; thus, the DC signal gain will be

the sa me as t he dynamic signal gain.

Figure 519 shows a t wo-stage direct coupled am plifier. The first s ta ge uses em itter biasing.

With no input signal, the 4.3 k emitt er resist or conn ected t o th e negative 5 V supply sets th e

emitter and collector current ofQ1 to 1 mA. The 1 mA of collector current flowing through Q1

causes a 15 V drop across the 15 k collector resis tor s ett ing th e collector volta ge at 5 V. The

second st age uses a P NP t ra nsist or, an d th e bias volta ge on th e base is held const an t a t 5 V by

the output of the first stage. The emitter ofQ2 is conn ected to a 10 V supply thr ough a 4.3 k

emitter resistor. Since 4.3 V will be dropped across the emitter, the emitter current and collector

curr ent ofQ2 will equal 1 mA. The 1 mA of collector current flows through the 20 k collector

resistor ofQ2, dropping 20 V. This causes t he outpu t to be zero volts a t quiescence.

One adva nt age of DC coupling is the high inpu t impeda nce of th e second st a ge. The high input

impeda nce is a resu lt of th e absence of base resistors at t he input oft he second sta ge.This reduces

loading on the first sta ge and perm its a h igher volta ge gain. Exam ple 5.15 shows how th e direct

coupled amplifier can be analyzed.

EXAM PLE 5.15

Q2

Vout

Rc2

20 k

Re2

4.3 k

Q1

Re14.3 k

Vin

20 V 10 V

5 V 20 V

Rc1

15 k

FIGURE 519 Direct coupled ampli fier

5.9 DIRECT COUPLED AM PLIFIERS

For th e circuit in Figur e 519 , calculat e VB, VE, VC, VCE, z in , zout , an d A v for each tra nsist or.

Then calculate z in , zout , and A v for t he t otal circuit.

Step 1. Calculate t he DC volta ge for t he first sta ge.

VB = 0 V (Assu me t he inp ut signa l ha s zero DC offset.)

VE = VB VBE = 0 V 0.7 V = 0.7 V

5.9 DIRECT COUPLED AMPLIFIERS 181


22/42


Direct coupled amplifiers have the advantage of being able to amplify DC voltages. However,

in orde r to am plify DC, coup ling capa citors and bypas s cap acitors mu st be rem oved. The rem oval

of coupling capacitors mea ns t ha t st ages cann ot be individually biased, an d an y Q-point dr ift in

one stage will be amplified by the next stage. The removal of the bypass capacitor causes the

gain of each st age to be low. The syst em will requ ire more st a ges to obtain t he need ed gain. Even

IE = (5 V (0 .7 V))/4.3 k = 1 mA

IE IC

VRc = Ic R c1 = 1 mA 15 k = 15 V

VC = VCC VRc = 20 V 15 V = 5 VVCE = VC VE = 5 V (0 .7) V = 5.7 V

Step 2. Calculate t he DC volta ge for t he second st age.

VB = VC of first st a ge = 5 V

VE = VB + VBE = 5 V + 0.7 V = 5.7 V (PN P tr an sistor VBE is added.)

IE = (10 V 5 .7 V)/4.3 k = 1 mA

IE IC

VRc = Ic R c = 1 mA 20 k = 20 V

VC = VCC VRc = 20 V (20 V) = 0 V

VCE = VC VE = 0 V 5.7 V = 5.7 V

Step 3. Calculate the input impedance an d output impedance for each st age. Assumebeta t o equal 100 for both tr an sistors.

First sta ge:

r'e = 25 mV/IE = 25 mV/1 mA = 25

re = r'e + R e = 25 + 4.3 k = 4.3 k (r'e is t oo sm all t o consider.)

z in = re = 100 4.3 k = 430 k

zout = R c = 15 k

Second sta ge:

r'e = 25 mV/IE = 25 mV/1 mA = 25

re = r'e + R e = 25 + 4.3 k 4.3 k (r'e is t oo sm all t o consider.)

z in = re = 100 4.3 k = 430 kzout = R c = 20 k

Step 4. Calculate t he volta ge gain of each st age.

First sta ge:

rc = R c || RL = 15 k || 430 k = 14.5 k (RL = z in of second st a ge (430 k).)

A v = rc/ re = 14.5 k/4.3 k = 3.37

Second sta ge:

rc = R c = 20 k (No load resistance connected.)

A v = rc/ re = 20 k/4.3 k = 4.65

Step 5. Calculate z in , zout , and A V(total) for t he t otal am plifier circuit.

z in = z in first sta ge = 430 kzout = zout last st age = 20 k

AV(total) = AV1 A V2 = 3.37 4.65 = 15.7



23/42

though direct coupled amplifiers have these disadvantages, they still are used in high quality

circuits wh ere low frequen cy an d DC a mplificat ion a re r equired.

Another way t o obtain DC a nd low frequency a mplificat ion is t o use a capacitor coupled

am plifier an d chop (tu rn ing the signa l off an d on at a high frequen cy) th e DC an d low frequ ency

signa ls so th a t t hey can be pass ed by th e coupling cap a citors. Chopper circuits will be discus sed

in a future chapter.

NG TRANSISTOR CIRCUITS

Troubleshooting transistor circuits can be divided into two areas: troubleshooting the circuit for

correct bias voltages, and troubleshooting the circuit for correct signal responses.

BIAS TROUBLESHOOTING __________________________________________________

If th e sta ges are capa citor coupled, th e procedu re used in tr oubleshooting single-st a ge circuit s

can be ap plied. Ea ch st age in a capa citor coupled am plifier is biase d indep enden tly, an d th ere fore,troubleshooting the biased circuitry is done one stage at a time. In direct coupled amplifiers, the

biased voltage on the base is the collector voltage of the previous stage. Troubleshooting the

biased circuit becomes a mu ltista ge problem.

SIGNAL TROUBLESHOOTING _______________________________________________

Signal troubleshooting is performed by inserting a signal from a signal generat or thr ough a

capacitor into the circuit, and then tracing the signal through the system. In multistage

am plifiers, remem ber, the load on one sta ge is th e input impedan ce of th e next. So when t he gain

of a st age is not a s estim at ed, it m ay be becau se th e next st age is loading it down. This can be

checked by disconnecting the next stage and replacing it with a resistor equal to its input

impeda nce. Open capa citors can cau se signal problems while not affecting t he biased volta ges.The bypass capa citor in t he emit ter leg, if it is open, will cause t he volta ge gain of th e sta ge to

go down. Open coupling cap acitors can be det ected by noting th a t t he signa l is not being coupled

from one st age t o the next. On e of the best ways t o check for open capa citors is to bypass t hese

capacitors with a known good capacitor. If the circuit returns to proper working order, the

capacitor needs r eplacing.

5.10 TROUBLESHOOTING TRANSISTOR CIRCUITS

5.10 TROUBLESHOOTING TRANSISTOR CIRCUITS 183


24/42


25/42

Voltage Divide r Biased Amplif iers

1. Calculate and record VB , VE, VC, z in , zout , A v, and maximum output voltage swings

with out dist ortion for each circuit in F igure 520.

Circuit a:

VB = _____ VE = ____ VC = _____

z in = _____ zout = _____ Av = _____

Maximum output voltage swing = _____

Circuit b:

VB = _____ VE = _____ VC = _____

z in = _____ zout = _____ Av = _____


Circuit c:

VB = _____ VE = _____ VC = _____

z in = _____ zout = _____ Av = _____


2. For a minimum frequency of 1 kHz, calculate the minimum capacitor size for each

capacitor in t he circuit in Figure 520 .

C1 = _______ C2 = _______ C3 = _______ C4 = _______

C5 = _______ C6 = _______ C7 = _______ C8 = _______

12 V

8.2 k

Rc

8.2 k

RL

3.0 k

Re

91 k

Rb1

10 F

27 k

RB2

(a) (c)(b)

+

+

20 mVp-p

+

10 F

2N3904

12 V

8.2 k

Rc

8.2 k

RL

3.0 k

RE

91 k

Rb1

10 F

27 k

RB2

+

+

20 mVp-p

+

10 F

2N3904

12 V

8.2 k

Rc

8.2 k

RL

300

Re

91 k

Rb1

10 F

27 k

RB2

+

+

20 mVp-p

+

10 F

2N3904

22 F

+

+

22 F

2.7 k

RE

FIGURE 520

PRE-LAB 5.1

PRE-LAB 5.1 185


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3. S im u la t e a n d r e cor d VB , VE, VC, z in , zou t , A v, and maximum output voltage swings

without distortion for each circuit in Figure 520 .

Circuit a:

VB = _______ VE= _______ VC= _______

z in = _______ zout = _______ A v = _______

Maxim um outpu t volta ge swing = ________

Circuit b:

VB = _______ VE= _______ VC= _______

z in = _______ zout = _______ A v = _______


Circuit c:

VB = _______ VE= _______ VC= _______

z in = _______ zout = _______ A v = _______




27/42

Voltage Divide r Biased Amplif iers

I. Objec tiv e

To an alyze and const ru ct th ree var iations of volta ge divider biased a mplifiers.

II. Test Equipm en t

(1) sine wave generator

(1) dual tr a ce oscilloscope

(1) 12 V power supply

III. Compo ne nts

Resist ors: (1) 200 , (1) 620 , (1) 820 , (1) 3.9 k, (1) 5.6 k, (1) 8.2 k, (1) 39 k

Ca pacitors: (2) 10 F a nd (1) 22 F

Tra nsist ors: (1) 2N3904

IV. Pro cedu re

1. Calculate and record VB , VE, VC, z in , zout , Av, an d ma ximum outpu t volta ge swing with out

distortion for each circuit in Figure 521.

Circuit a:

VB = _____ VE = _____ VC = _____

z in = _____ zout = _____ Av = _____

Maximum output voltage swing = _____Circuit b:

VB = _____ VE = _____ VC = _____

z in = _____ zout = _____ Av = _____


Circuit c:

VB = _____ VE = _____ VC = _____

z in = _____ zout = _____ Av = _____


V

R

R

cc

c

= 12 V

3.9 k

5.6 k

L

Re

820

Rb1

39 k

Rb2

8.2 k2 kHz

(a) (b) (c)

200

620

RE

Re2 kHz

Rb2

8.2 k

Rb1

39 k

V

R

R

cc

c

= 12 V

3.9 k

5.6 k

L

RE

820 2 kHz

Rb2

8.2 k

Rb1

39 k

V

R

R

cc

c

= 12 V

3.9 k

5.6 k

L

FIGURE 521

LAB 5.1

LAB 5.1 187


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2. Constr uct each circuit in Figure 521 and m easur e the values ofVB, VE, VC, z in , zout , Av,

and maximum output voltage swing without distortion. Set the input signal frequency

to 2 kHz and th e signal ma gnitu de as needed.

Circuit a:

VB = _____ VE = _____ VC= _____

z in = _____ zout = _____ A v = _____Maximum output voltage swing = _____

Circuit b:

VB = _____ VE = _____ VC= _____

z in = _____ zout = _____ A v = _____


Circuit c:

VB = _____ VE = _____ VC = _____

z in = _____ zout = _____ A v = _____


V. Poin ts to Discuss

1. Ana lyze and discuss th e percent of difference in calculat ed and mea sur ed values.

2. Explain the difference in voltage gain (Av) am ong th e th ree circuits.

3. Explain the difference in input impedance (z in) am ong the t hr ee circuits.

4. Why were zout an d the DC volta ge readings approximat ely th e sam e for all thr ee circuits?



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Multistage Amplif ier

1. Calculate an d record all values listed below for th e amplifier circuit in Figure 522 .

Stage 1:

VB = _____ VE = _____ VC = _____

Av = _____ z in = _____ zout = _____

Stage 2:

VB = _____ VE = _____ VC = _____

Av = _____ z in = _____ zout = _____

Total Circuit:

Av = _____ z in = _____ zout = _____

2 . For a minimum frequency of 1 kHz, calculate the minimum capacitor size for each

capacitor in t he circuit in Figure 522.

C1 = _______ C2 = _______ C3 = _______ C4 = _______

C5 = _______

3. Simulate and record VB , VE, VC, Av, z in , and zout , for t he a mp lifier circuit in Figur e 522.

Stage 1:

VB = _____ VE = _____ VC = _____

Av = _____ z in = _____ zout = _____

18 V

56 k

10 F+

+

20 mVp-p

+

3.9 k

6.2 k

RL

2N3904

10 F

+

22 F 1.2 k

15 k 200

56 k

+

22 F

10 k

2N3904

100

910

++

10 F

3.6 k

FIGURE 522

PRE-LAB 5.2

PRE-LAB 5.2 189


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Stage 2:

VB = _____ VE = _____ VC= _____

Av = _____ z in = _____ zout = _____

Total Circuit:

Av = _____ z in = _____ zout = _____



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Multistage Amplif ier

I. Objec tiv e

To an alyze a mult ista ge amplifier to determin e

the bias a nd signal values at test points.

II. Test Equipm en t

(1) sine wave generator

(1) dual-trace oscilloscope

(1) 12 V power supply

III. Compo ne nts

Resist ors: (1) 100 , (1) 180 , (1) 680 , (1) 820 , (2) 3.9 k, (3) 8.2 k, (2) 39 k

Ca pacitors: (3) 2.2 F a nd (2) 10 FTra nsist ors: (2) 2N3904

IV. Pro cedu re

1. Calculate an d record all values listed below for th e amplifier circuit in Figure 523 .

Stage 1:

VB = _____ VE = _____ VC = _____

Av = _____ z in = _____ zout = _____

Stage 2:

VB = _____ VE = _____ VC = _____

Av = _____ z in = _____ zout = _____

Total Circuit:

Av = _____ z in = _____ zout = _____

VCC

= 12

39 k3.9 k 39 k

3.9 k

2.2 F

2.2 F

10 F

2.2 FQ1

Q2 2N39042N3904

10 F

8.2 k

8.2 k

820

RL

8.2 k

680

180 100

2 kHz

100 mV

FIGURE 523

LAB 5.2

LAB 5.2 191


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2. Const ru ct th e circuit in Figure 523 an d meas ur e the values listed below for th e am plifier

circuit.

Stage 1:

VB = _____ VE = _____ VC= _____

Av = _____ z in = _____ zout = _____

Stage 2:

VB = _____ VE = _____ VC= _____

Av = _____ z in = _____ zout = _____

Total Circuit:

Av = _____ z in = _____ zout = _____

V. Poin ts to Discuss

1. Explain any differen ces between calculated and measu red values.

2. Explain why z in of th e first s ta ge equals z in of th e t ota l circuit.

3. Explain why zout of th e last st age equals zout of the tota l circuit.

4. Explain why input impedan ce of th e second st age affected th e volta ge gain of th e first

stage.

5. The tota l volta ge gain of th is circuit could be obta ined by using a single-st age am plifier.

Explain th e advan ta ges of using two stages.



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5.1 Introduct ion

1. Why is it necessary to sta bilize th e bipolar tra nsistor amplifier against changes in beta?

a. Beta changes with temperatu re.

b. Beta chan ges with cha nges in coupling capacitors.

c. Beta is different am ong transistors of the sam e type.

d. Both a and c.

2. The typical beta of a tr an sistor should be considered to be ________.

a. +50% and 50%

b. +50% and 100%

c. +100% and 50%

d. +100% and 100%

3. If beta chan ges, how will th e lack of bias sta bility show up in an am plifier circuit?

a. The collector volta ge will change.

b. The collector curr ent will change.

c. The emitter curren t will chan ge.

d. All of th e above.

5.2 Voltage Div ider Biasin g

4. In volta ge divider biasin g, why is th e volta ge at t he junction ofR b1 and R b2 considered

to be independent of the t ra nsistor base curren t?

a. The base curr ent does not flow through R b1 or R b2.

b. The base curr ent is small in compar ison to the bleeder current t hrough R b1 and

R b2.

c. Only th e emitt er curr ent ha s an effect on the cur ren t flow th rough R b1 and R b2.

d. The coupling capa citor blocks base curren t th rough the volta ge divider.

5. In volta ge divider biased amplifiers, th e difference in volta ge between the emitter an d

base is always _____.

a . 0 V

b. 0.2 V

c. 0.7 V

d. 2 V6. In voltage divider biased amplifiers, once the DC emitt er voltage is calculated, the

quiescence collector curr ent can be a pproxima ted by dividing th e emit ter volta ge by

_____ .

a. the resistance in the base leg

b. the resistance in the emitter leg

c. th e resist an ce in th e collector leg

d. the resistance of the load

QUESTIONS

QUESTIONS 193


34/42

7. In volta ge divider bias ed am plifiers, th e collector volta ge is calculat ed by _____.

a. mu ltiplying the collector cur rent t imes the collector resistor

b. mu ltiplying th e collector cur rent t imes the load resistor

c. adding the base voltage and the emitter voltage

d. subt ra cting th e volta ge dropped across th e collector resistor from the supply

voltage

5.3 Sign al Paramete rs in Voltage Div ider Circuits

8. Volta ge divider biased am plifiers are beta independen t, but wha t is th e price paid for

this independence?

a. loss of sta bility

b. low outpu t impedance

c. loss of volta ge gain

d . both a and c

9. When calculating input impedance, the two base resistors (R b1 and R b2) appear in________ with ea ch oth er.

a . ser ies

b. series/para llel

c. paral le l

d. opposing series

10. The dyna mic resista nce of the base/emitt er junction is in __________.

a. series with the signal resistance in the base leg

b. para llel with the signal resistan ce in the base leg

c. para llel with the signal resistance in the emitt er leg

d. series with the signal resistance in the emitter leg

11. The output impedan ce of th e comm on emitter am plifier is equal to _______.

a. th e collector resist or

b. the load resistance

c. th e collector resistor in para llel with the load resista nce

d. th e collector resist or tim es beta

5.4 Variation s of Voltage Divide r Biase d Amplif iers

12. Which type of volta ge divider biased amplifier has th e highest inpu t impeda nce?

a. fully bypassed

b. split-emitter

c. unbypassed

d. a l l the same

13. Which type of volta ge divider biased amplifier has th e highest outp ut impeda nce?

a. fully bypassed

b. split-emitter

c. unbypassed

d. a l l the same



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14. Which type of volta ge divider biased am plifier has t he highest volta ge gain?

a. fully bypassed

b. split-emitter

c. unbypassed

d. a l l the same

15. Which type of volta ge divider biased am plifier has t he least distort ion?

a. fully bypassed

b. split-emitter

c. unbypassed

d. a l l the same

5.5 Emitter Biase d Amplif ier16. The quiescent base volta ge of th e emitt er biased a mplifier is norma lly ______.

a . 0 V

b. 0.7 Vc. 2 V

d. Vcc

17. A disadvan ta ge of th e emitter biased am plifier when compa red to th e volta ge divider

biased amplifier is the emitter biased amplifier requires ______.

a. tra nsistors with higher beta

b. two power supply voltages

c. higher value ofVcc

d. none of the above

18. The volta ge gain of th e emitt er bias ed am plifier is ________.

a. dependent on beta

b. calculat ed using th e same general form ula as th at u sed for the volta ge divider

biased a mplifier

c. equal to rc

d. always higher th an th at of th e volta ge divider biased am plifier

5.6 Voltage -Mode Feedba ck Bia sed Amplif ier

19. Volta ge-mode feedback biased am plifiers are par ticular ly suita ble for operations with

______.

a. high frequency signals

b. low volta ge power suppliesc. circuits requiring an exceedingly high input impeda nce

d. circuits requiring an exceedingly low output im pedan ce

20. The input impedan ce of a volta ge-mode feedback biased a mplifier is affected by th e

_______.

a. wat ta ge value of th e collector resistor

b. am plifier volta ge gain

c. resistance of the feedback resistor

d. both b and c

QUESTIONS 195


36/42

5.7 Multistag e RC Coupled Amplifiers

21. Why is it importan t to know the input impedances of each st age in a multistage

amplifier?

a. The total input impedan ce is th e product of each stages input im pedan ce.

b. The volta ge gain of a sta ge is affected by th e input impeda nce of th e next sta ge.

c. The input impedan ce of a sta ge is th e load resista nce on the previous sta ge.

d. Both b and c.

22. What is one of th e main advan ta ges of using coupling capa citors between sta ges?

a. They permit the multista ge am plifier to pass DC signals.

b. They permit th e bias circuitr y in each stage to be independent.

c. They bypass the emitter resistor and increase the gain.

d. Both b and c.

23. The tota l volta ge gain of a m ult ista ge amplifier is equal to the ________.

a. sum of each sta ges volta ge gain

b. product of each sta ges volta ge gain

c. first stage voltage gain

d. last stage voltage gain

24. The input impedan ce of th e total mu ltista ge amplifier is equa l to th e ________.

a. sum of each sta ges input impeda nce

b. product of each stages input im pedan ce

c. first sta ge input impedance

d. last sta ge input impedance

25. The out put im pedan ce of th e total mu ltista ge amplifier is equa l to th e ________.

a. sum of each sta ges out put impeda nce

b. product of each stages out put impeda nce

c. first sta ge outpu t impedanced. last stage output impedance

5.8 Coupling and Bypass Capacitors

26. The size ofcoupling an d bypas s capa citors is one of th e ma in factors det erm inin g _____.

a. low frequen cy cutoff

b. voltage gain

c. current gain

d. high frequency cutoff

27 . If the inpu t im pedan ce of the second st age is 1 k, the coupling capacitor connectingthe first st age to the second st age should have an Xc of ap pr oxima te ly _____ for t he

lowest frequen cy to be am plified.

a . 1

b. 10

c. 100

d. 1 k

e. 10 k



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5.9 Direct Couple d Amplif iers

28. Direct coupled amplifiers ha ve an a dvant age over RC coupled amplifiers in tha t th ey

can amplify ______.

a. larger signals

b. high frequency signals

c. smaller signals

d. low frequency signals

29. Direct coupled am plifiers ar e pa rt icular ly sus ceptible to _________ problems.

a . ga in

b . saturat ion

c. DC drift

d . impedance

5.10 Troubleshooting Transistor Circuits

30. The collector of Q1 in Figure 524 mea sur es appr oximat ely 20 V DC.

a. The circuit is functioning corr ectly.

b. Capacitor C2 is shorted.

c. Capacitor C2 is open.

d. Resistor R 1 is open.

31. The collector of Q2 in Figure 524 mea sur es 13.8 V DC.


b . Transis tor Q2 is open between th e collector an d th e emitt er.

c. Capacitor C5 is shorted.

d. Resistor R 8 is shorted.

32. The DC voltage at th e junction of resist ors R 4 and R 5 in F igure 524 is zer o volts.


b . Transis tor Q1 ha s a collector to emitt er short .

40 mVp-p

VCC = 20 V

R1128 k

R38 k R6

66 k

R83 k

RL3 k

Q1 C2

C1

C3Q2

R220 k

R1.8 k

5

C4 C5

R715 k

R4

200

R101.2 k

R9300

FIGURE 524

QUESTIONS 197


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c. Capacitor C4 is open.

d. Resistor R 2 is shorted.

33. The signal volta ge gain ofQ2 in Figure 524 is approxima tely two times th e calculated

gain.


b. Capacitor C3 is open.


d. Capacitor C5 is open.

34. The signal volta ge gain ofQ1 is approximately three.


b. Capacitor C4 is open.


d. Capacitor C2 is open.

1. For the circuit in Figure 525 , find :

Vc = ____________ VB = ______________ VE = ____________ A v = ___________

VCE = ____________ z in = ______________ zout = ____________ Vout = __________


Vc = ____________ VB = ______________ VE = ____________ A v = ___________

VCE = ____________ z in = ______________ zout = ____________ Vout = __________

PROBLEM S

VCC = 1 8 V

2 k

800 8 k

30 k

RL3 k20 mVp-p

FIGURE 525



39/42


Vc = ____________ VB = ____________ VE = ____________ A v = ___________VCE = ____________ z in = ____________ zout = ____________ Vout = __________

4. What is t he largest signal that can be accommodated a t the input of the circuit in

Figure 527 before t he outpu t begins to clip?

5. If the lowest frequen cy of opera tion is to be 100 Hz, select a valu e for C1, C2, and C3 in

th e circuit in F igure 527.

C1 = _________ C2 = __________ C3 = __________

6. For th e circuit in Figure 528, find:

Vc = ____________ VB = ______________ VE = ____________ A v = ___________

VCE = ____________ z in = ______________ zout = ____________ Vout = __________

VCC

= 18 V

2 k30 k

8 k800

RL

3 k20 mVp-p

FIGURE 526

V = 18 VCC

2 k

100

700

30 k

8 k

RL3 k

C3

C1

C2

20 mVp-p

FIGURE 527

PROBLEMS 199


40/42

7. Find th e values requ ested below for th e circuit in Figure 529.

Stage 1:

VB = ____________ VE = _____________ VC= ____________

Av = ____________ z in = _____________ zout = ___________

Stage 2:

VB = ____________ VE = _____________ VC= ____________

Av = ____________ z in = _____________ zout = ____________

Total Circuit:

Av = ____________ z in = _____________ zout = ____________

8. If the lowest frequency of opera tion is to be 1 kHz, select a value for C1, C2, C3, C4, and

C5 in th e circuit in F igure 529.

C1 = _________ C2 = __________ C3 = __________

C4 = _________ C5 = __________

V

R

cc

L

= 1 2 V

3.3 k

6 k

2 k300

5.3 k

50 mVp-p

VEE= 12 V

FIGURE 528

VCC = 1 2 V

R8

390

C3Q2

R9

22

RL

1 k

C5R10

220

R72.7 k

C4

R4

82

Q1 C2

R67.4 k

R31 k

R118 k

C1

R212 k

R51.2 k

20 mVp-p

FIGURE 529



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9. Find th e values requ ested below for th e circuit in Figure 530.

Stage 1:

VB = ____________ VE = _____________ VC = ____________

Av = ____________ z in = _____________ zout = ___________

Stage 2:

VB = ____________ VE = _____________ VC = ____________

Av = ____________ z in = _____________ zout = ____________

Total Circuit:

z in = ____________ zout = _____________ A v = ____________

16 V 8 V

Vin 7.4 k

Vout

3.6 k

1.65 k

16 V8 V

Q1

6 k

Q2

FIGURE 530

PROBLEMS 201


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Chapter 5 Transistor

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