Chapter 5 Physics of MOSFET and MOSFET Modelingstaff.utar.edu.my/limsk/VLSI Design/Chapter 5... ·...

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Chapter 5

Physics of MOSFET and MOSFET Modeling ____________________________________________

5.0 Introduction A tremendous advantage of silicon technology used to fabricate the electronic device is the presence of a high quality silicon dioxide, which can be formed on silicon. It has high degree of perfection that silicon has overtaken germanium, which was the initial choice for transistors. Also owing to perfection of Si-SiO2 interface makes it the reason that bipolar devices have been replaced by field effect device in many applications.

5.1 Effects of Bias Voltage There are three important regimes when the MOS capacitor is under voltage biasing VG. These are accumulation, depletion, and inversion modes (refer to Fig. 5.1).

Accumulation Mode: Using p-type semiconductor as an illustration, if the negative bias voltage i.e. VG < 0 is applied between the metal and semiconductor, the Fermi energy level of the metal is raised by an amount eVG and the valence band of the semiconductor bends toward the Fermi level. This would cause the hole to accumulate at the surface near the oxide.

Depletion Mode: If the positive bias voltage i.e. VG > 0 is applied to the metal with respect to the p-type semiconductor, the Fermi level of the metal is lowered by an amount eVG. This would cause the valence band of the semiconductor to move away from the Fermi level of the metal. As a result, the hole depletes into the bulk as such that the hole concentration near the interface would fall below the concentration value in the bulk semiconductor.

Inversion Mode: If the positive bias voltage i.e. VG >> 0 is further increased, eventually the conduction band of the semiconductor comes closer to the Fermi level. As a result, electron density near the interface surface starts to increase. Further increase of bias voltage would cause the conduction band of the semiconductor to bend further and crosses to the Fermi level of the metal. In this condition, the density of electron increases very high and the semiconductor at the interface is inverted into n-type semiconductor.

5 Physics of MOSFET and MOSFET Modeling

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Figure 5.1: The energy band diagrams of three biased voltage conditions of an ideal p-type

MOS device


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When the surface potential qФS, which is potential difference of the intrinsic energy level at the interface with the intrinsic energy level in the bulk, is zero, it implies flat-band condition. For p-type MOS, when qФS is a positive, it implies depletion mode. When qФS is a positive value and larger than 2qφF then inversion occurs. When qФS is a negative value, it implies accumulation.

Similar explanation is applied to n-type MOS device. The energy band diagram of the p-type MOS device under inversion condition is shown in Fig. 5.2. Notice that inversion occurred when the surface potential is twice the Fermi potential, which follows equation (5.1).

FS q2)inv(q φ=Φ (5.1)

Figure 5.2: The energy band diagram of p-type MOS device at inversion condition

The Fermi potential at the bulk Fqφ is

=φ

i

AF

Nln

q

kT

n (5.2)


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where NA is the acceptor doping concentration for p-type semiconductor, ni is the intrinsic carrier concentration and kT/q is the thermal voltage. Substituting equation (5.2) into equation (5.1) yields equation (5.3).

i

AS

Nln

q

kT2)inv(

n=Φ = 2φF (5.3)

5.2 Threshold Voltage Threshold voltage Vt is defined as the gate voltage VG needed to induce sufficient number of charge carrier in the channel for conduction. It is the minimum applied gate voltage to induce inversion of the channel for conduction. To find the threshold voltage Vt, one needs to understand how the voltage is drop across the MOS capacitor.

Fig. 5.3 shows the MOS structure with a voltage VG applied to its gate. Applying Kirchhoff’s voltage law, the gate voltage VG is

VG = Vox + Vs (5.4)

Figure 5.3: Charge density, electric field, and electrostatic potential of MOS in inversion

mode

Equation (5.4) is an ideal equation without considering the trapped charge within the oxide that alters the electric field and the differences in the electrical


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characteristics of the gate and substrate materials. Thus, a term flat-band voltage is used to account these effects, which is

Vfb = ( ) ( )oxox

SG QQC

1 +−φ−φ f (5.5)

where ( )SG φ−φ is the work function difference between gate and substrate and

is also approximately equal to ( )SG φ−φ ≈

−

2i

poly,DA NNln

q

kT

n for an n-type

polysilicon gate with p-substrate. If the poly gate is a p-type, then the work

function difference between gate and substrate is ( )SG φ−φ ≈

A

poly,A

N

Nln

q

kT . The

work function is derived from

+∆Φ=φ

i

A

n

Nln

q

kT for p-type material and

−∆Φ=φ

i

D

n

Nln

q

kT for n-type material. ∆Φ is a work function constant.

Qf is the fixed surface charge density at the oxide-silicon interface and Qox

is the trapped charge within the oxide. Re-writing equation (5.5), it becomes

Vfb = ox

ox

2i

poly,DA

C

QQ

n

NNln

q

kT +−

− f (5.6)

Equation (5.4) shall then be modified to VG = Vfb + Vox + VS (5.7) The voltage drops across oxide Vox is Vox = Eox.dox. At semiconductor-oxide interface, the surface charge QS is also equal to charge on oxide Qox, which is

εsEs = εoxEox. Qox is also equal to Qox = CoxVox = ox

oxox

d

V ε. Thus, Vox is equal to

Vox = ox

oxSS dE

εε

. Re-writing equation (5.6), it becomes

VG = Vfb + VS + εS S

ox

E

C (5.8)


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For charge balancing, QS = Qox = Qdep, where depletion charge Qdep is equal to

Qdep = qNAddep. The depletion thickness ddep is equal to ddep = 2/1

A

SS

qN

V2

ε. At

inversion, VG = Vtn and VS = 2φF, ddep becomes maximum value. Thus, the maximum depletion charge Qdepmax is equal to ( ) 2/1

FASqN4 φε and surface electric

field ES is ES = S

FAS

S

maxdep Nq4Q

εφε

=ε

. Substituting expression ( ) 2/1FASqN4 φε to

replace εSES in equation (5.8), the threshold voltage equation becomes oxFASFtn C/qN42VV φε+φ+= fb (5.9)

or oxSFtn C/Q2VV +φ+= fb (5.10)

If the substrate of the MOSFET is biased with a voltage VSUB then the threshold voltage Vtn is redefined as oxSUBFASFtn C/)V2(qN22VV +φε+φ+= fb (5.11)

The equation shows that the threshold voltage increases with positive VSUB bias since the surface potential is increased by a value VSUB.

Under normal processing conditions, the flat-band voltage is negative and usually yields a negative threshold voltage. For CMOS switching circuits that use a positive power rail, a positive threshold voltage is needed. This is accomplished by performing a threshold adjustment ion implant with a dose giving the number of implanted ion. This modifies the equation to for the value of the threshold voltage. Implanting acceptor ions into the substrate is equivalent to introducing additional bulk charge at the surface; the implant thus induces a positive shift. The equation to follow for the ion implant adjustment is

( )ox

IoxSubFASFtn C

qDC/V2qN22VV ±+φε+φ+= fb (5.12)

where DI is the dosage, the number implanted ion per unit area.


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If there is no substrate voltage VSUB, in which sometime is called zero body bias then equation (5.11) becomes oxFASFtno C/)2(qN22VV φε+φ+= fb ,

where Vtno is the threshold voltage without the substrate voltage or body bias voltage. The equation (5.11) can be re-written in terms of Vtno and substrate voltage as

( )FSUBFOX

AStnotn 2)V2(

C

qN2VV φ−+φ

ε+= (5.13)

The term OX

AS

C

qN2ε is denoted as gamma γ, which is called bulk threshold

parameter. Equation (5.13) clearly shown that as the VSUB voltage increases the threshold voltage of the device increases. Rewriting equation (5.13), it becomes ( )FSUBFtot 2)V2(VV φ−+φγ±= (5.14)

The positive sign is used to denote n-MOS transistor and negative sign for p- MOS transistor.

In order to eliminate the effect of parasitic npn or pnp transistor of the n-MOS transistor and p-MOS transistor, the substrate of the p-MOS transistor, which is an n-type semiconductor, is usually biased with VDD voltage, whilst the substrate of n-MOS transistor, which is p-type semiconductor, is biased with VSS voltage i.e. zero volt.

By Kirchhoff’s voltage law, the source voltage VS and substrate voltage

VSUB relationship is –VS+VS-SUB+VSUB = 0. Equation (5.14) therefore can be written as one equation for p-MOS transistor and one for n-MOS transistor. They are ( )FSUBSSFtpotp 2)VV2(VV φ−−+φγ−= − (5.15)

( )FSUBSSFtnotn 2)VV2(VV φ−−+φγ+= − (5.16)

With substrate of p-MOS transistor biased with VDD, and source and substrate are tied together, the VSUB-S is equal to zero. Therefore, the threshold voltage of p-MOS transistor is ( )FDDFtpotp 2)V2(VV φ−+φγ−= (5.17)


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With the substrate of n-MOS transistor biased with VSS and source and substrate are tied together, VS-SUB is equal to zero. Therefore, the threshold voltage of the n-MOS transistor is ( ) tnoFFtnotn V2)2(VV =φ−φγ+= (5.18) One can see that Vtp of p-MOS transistor is lower than Vtpo, whilst the Vtn of n-MOSFET is same as Vtno for the substrate biased condition mentioned above.

5.3 MOSFET A MOSFET is a MOS transistor and is essentially consist of a MOS capacitor and two diffused or implanted regions that serve as ohmic contacts to an inversion layer of free charge carriers with the semiconductor-silicon dioxide interface. Figure 5.4 illustrates the 2-D structure of an n-MOSFET.

Figure 5.4: A 2-D structure of an n-MOSFET

Gradual Channel Approximation Model and Constant Mobility Approximation Model can be used to study the characteristics of MOSFET. The model is used to study how the conduction channel of the MOSFET is changed by the horizontal electric field generated by the drain to source voltage VDS and how the conducting channel is modulated by the vertical electric field generated by the gate to source voltage VGS. This is done by studying the drain to source current IDS versus drain to source voltage VDS characteristic for different applied gate to source voltage VGS and the transconductance of the device, which is the study of IDS current changes with the change of VGS voltage. These two studies are connected with the physical studies of the linear and saturation regions of


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the drain to source characteristics with various gate-to-source voltage VGS. Based on this understanding, one has to look at the two dimensional Poisson’s equation in order to understand the actual conduction mechanism of current from drain to source via the inverted channel.

There are two electric field components present in MOSFET when it is in operation. These fields can be represented by the two dimensional Poisson’s equation that has one horizontal field EX and one vertical field EY.

∂∂

∂∂

ρε

E

X

E

YX Y

S

+ = − (5.19)

Gradual Channel Approximation Model is true only if ∂∂E

XX is very small and

constant so that the Poisson’s equation can be approximated as

∂∂

ρε

E

YY

S

≈ − (5.20)

The vertical electric potential of the conduction channel with thickness δd is

given as∂∂ δE

Y

E

dY Y= .

( )

q/kTd

VV

Y

E2ox

2tGS

2

s

oxY −

εε

=∂

∂ (5.21)

On the other hand, the variation of horizontal electric field can be approximated as

∂∂E

X

V

LX DS= 2 (5.22)

where L is the channel length and VDS is the voltage between drain and source of the MOSFET. Here, it is assumed that the field strength changes gradually from a small value near the source to a value of the order VDS/L near the drain.

The mobilities of the electron and hole µn, µp of the MOSFET are not the same as the mobility in the semiconductor bulk moving into the crystal lattice. Knowing the electrons or holes are moving on the surface between the semiconductor and oxide interface, their mobilities are very much depending on


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the surface impeding collision and ionized impurity scattering. However electrons and holes moving not closed to the interface would have a higher mobility. One also has to consider the influence of horizontal electric field resulted from drain to source voltage. Thus, there is an effective mobility µ for both hole and electron.

If the drain-to-source voltage is small, the effective channel length and

carrier charge will be more or less uniform from the source to drain and effective mobility will be essentially the same for all x values. However, one cannot ignore the effect of gate voltage on the mobility. As the gate-to-source voltage increases, the electron is moving closed to the interface. The effect of scattering will be more. Thus mobility decreases which can be observed from equation (5.23).

)VV(1 tGS

0n −θ+

µ=µ (5.23)

where µ0 is constant and θ is the mobility degradation parameter. It can be shown that the effective mobility µn of electron is about 0.6 of the bulk mobility at (VGS – Vt) = 4V to about 0.5 for (VGS – Vt) = 13V.

In the VLSI design, the mobility is always taken ratio of 2:1 for electron and hole. 5.3.1 Current-Voltage Characteristics The surface interface potential above threshold regime is equal to Vs(x) = ( ( ))2φF V x+ , where V(x) is the channel potential at position x along the channel in the direction from source to drain. However, from Gradual Channel Approximation Model, one can say that V(x) is equal to zero at the source side because the source and the substrate are normally shorted together and biased at VSS for an n-MOSFET. Thus, V(x) is equal to the drain-to-source voltage VDS at the drain side. This shall mean that the gate voltage with respect to source VGS is equal to

)x(V2C

)x(QVV F

ox

sGS +φ++= fb (5.24)


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Qs(x) is the surface charge, which is consisting of free electron charge Qn(x) and fixed charge acceptors in the depletion region QDEP(x). Therefore, the surface charge of is given by equation (5.25).

Qs(x) = Qn(x) + QDEP(x) (5.25)

From Constant Mobility Approximation Model, the electron mobility µn is constant and there is only drift and negligible diffusion, the drain-to-source current IDS can be calculated from current density Jn = qµnnE after ignoring the diffusion portion. Indeed drift current is required to be considered since the drain is reversed biased with respect to source.

Using the channel geometry of the current flow shown in Fig. 5.5, drain-to source-current IDS is made of summation of all small rectangular current elements with surface area Wdy across the channel of thickness dx for the whole channel length L.

Figure 5.5: Channel geometry showing the flow of current IDS analysis

Thus drain to source current can be calculated equation (5.26).

∫∫∫ −=−=)x(y

0

nynyDS dyJWdydwJI

µ−

−= ∫ dy)y,x(n)y,x(qdx

)x(dVW

)x(y

0

sn

(5.26) where the second expression of equation (5.26) is equal to effective mobility of the electron µn , which is equation (5.23). Knowing that the threshold voltage is


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Vt = 2φF +Vfb +ox

DEP

C

Q and nsOXFGS V)x(V)x(VV2V ++++φ= fb after inversion with

mobile ion density ns, the surface free charge density per unit area ns(x) in x-direction is

[ ] [ ]q

2)x(VN2)x(VV2V

q

C)x(n FAS

FGSox

S

φ+ε−−−φ−= fb (5.27)

Substituting equation (5.27) into IDSdx = qµnnsWdV(x) and integrating the equation with the boundary conditions for V x x( ) =0 = 0 and V x x L( ) = = VDS and x = 0 to x = L, IDS, it yields the drain to source equation (5.22).

DSDS

FGSoxn

DS V2

V2VV

L

CWI

−φ−−µ

= fb

( ) ( )[ ]

φ−φ+ε

− 2/3F

2/3FDS

ox

AS 22VC3

qN22 (5.28)

At pinch-off condition where nS = 0 andV x x L( ) = = VDS = VDSSAT, equation (5.28) is equal zero for V(x) = VDS. Solving the quadratic equation for VDS shall yield,

ε+−φ−==

2ox

ASFGSDSSATDS C

qNV2VVV fb

ε−

+−AS

2oxGS

qN

C)VV(211 fb

(5.29) Beyond pinch-off, the drain current IDS essentially remain constant but it may be complicated by channel modulation and other effects. 5.3.2 Linear Region For very small drain to source voltage where VDS << (VGS-Vfb-2φF) andVDS F<< 2φ , equation (5.28) can be simplified to equation (5.30) and expanding the Taylor’s series for the second term.

−−

µ=

2

VV)VV(

L

CWI

2DS

DStGSoxn

DS (5.30)

This is the equation for the linear region of the MOSFET’s characteristics.


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5.3.3 Saturation Region After pinch-off, IDS is assumed to be constant. It is true only if the doping concentration is low and the oxide thickness is thin. The term in equation (5.29) involving N CA ox/ 2 can be ignored and terms involving N CA ox/ can be retained. This gives the shall mean that

VDSSAT = ( ) 2/1GS

ox

ASFGS VV

C

qN22VV fbfb −

ε−φ−− (5.31)

If the voltage drops across the oxide is negligible, then at strong inversion the quantity (VGS – Vfb) is equal to VGS - Vfb ≅ 2φF. Based on the above assumption, equation (5.31) can be simplified as VDSSAT = tGS VV − (5.32) After substituting equation (5.31) into equation (5.29),

( ){2

)VV()VV(2VV

L

CWI

2tGS

tGFGSoxn

DSSAT

−−−φ−−

µ= fb

( ) ( )[ ]

φ−φ+−ε

− 2/3F

2/3FtGS

ox

AS 22VVC3

qN22 (5.33)

Since the current does not change with VDS in this equation, further simplification can be done once pinch-off occurred. i.e. N CA ox/ is small such

that VT ≅ Vfb + 2φF. The equation (5.33) shall be simplified to

( )

−

−−µ

=2

)VV(VV

L

CWI

2tGS2

tGSoxn

DSSAT (5.34)

= 2tGS

oxn )VV(L2

CW−

µ

This is the equation for the saturation region of the MOSFET characteristics.

A typical ideal characteristic curve of an n-MOSFET is shown in Fig. 5.6. The curve shows three regions of the characteristic, which are the linear, saturation, and cut-off regions. The MOSFET device will be turned of if the VGS voltage is less than the threshold voltage Vt. Note also that the dotted line is a line denotes that VDS = VGS – Vt. This is a dividing line that determines the


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operational condition of the MOSFET. It is also the line showing the pinch-off the current. If the condition is VDS < VGS – Vt, then the MOSFET is in linear region or at time it is referred as triode region. This is the region that the MOSFET device would work as a digital logic device. If the condition is such VDS > VGS – Vt then the MOSFET is in saturation region. This is the region that the MOSFET device works as an amplifier device.

Figure 5.6: Characteristic curve of MOSFET

5.3.4 Drain Conductance and Transconductance Having defined the equations for linear and saturation regions of the MOSFET, the next two important parameters of MOSFET to be defined are the drain conductance and the transconductance. The drain conductance gD is defined as

gI

VDDS

DS V Cons tGS

==

∂∂

tan

)VV(L

CWtGS

oxn −µ

= (5.35)

Drain conductance is also equal to equation (5.30) if the term VDS is moved to the left-hand side of the equation as denominator.

The transconductance gm at saturation region is defined as


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)VV(L

CW

V

Ig tGS

oxn

ttanconsVGS

DSATTm

DS

−µ

=∂

∂=

=

(5.36)

5.3.5 Cut-off Frequency The cut-off frequency fmax of the MOSFET device is defined as the maximum operating frequency of the MOSFET when it is in saturation with the assumption that the mobility of the carrier is constant. Thus, the cut-off frequency for p-MOS transistor is defined as

fmax=g

Cm

GS2π (5.37)

where CGS is the gate to source capacitance, which estimated to be oxide capacitance per unit area multiplies by area WL. Thus, the gate to source capacitance is WLCC oxGS = .

fmax 2

tGSp

GS

m

L2

)VV(

C2

g

π−µ

=π

= (5.38)

For the short channel device, the cut-off frequency is assumed to depend on the transit time ttr of the carrier in the channel. Thus,

fmax =1

2πt tr

(5.39)

where by ttr is also approximately equal to the channel length L divided by carrier saturation velocityνs . i.e. trr = L/Vs.

5.4 Non-Ideal Effects Owing to scaling of integration, many physical parameters of the material are no longer can be considered ideal parameters. Phenomenon such as hot electron, reaching saturation velocity, prominent interface scattering etc are dominating at small device structure. The non-ideal effects for MOSFET to be considered are sub-threshold, channel length modulation, mobility variation, velocity saturation, ballistic effects, short-channel effects, narrow channel effect etc.


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5.4.1 Sub-Threshold Conduction The ideal current-voltage characteristic of MOSFET shows that there is no conduction current when the gate to source voltage VGS is less than or equal to the threshold voltage Vt i.e. VGS ≤ Vt. However, in reality there is a sub-threshold current flows caused by the surface of semiconductor develops into a light doped n-type material joining the n-type drain and source for the case of n- MOSFET. Owing the way that drain is biased, there is also a small amount of drift current is being registered before the channel is switched on. The ideal and experimental current characteristics of MOSFET are shown in Fig. 5.7.

Figure 5.7: The ideal and experimental drain current of a MOSFET

Upon the gate to source bias and when the surface potential ΦS is less than 2φF, the Fermi level is closer to conduction band. Thus, it causes the p-type material near the oxide interface turns into lightly doped n-type. This would expect some conduction between n+-source and drain through this inverted n-type substrate. The condition for φF <ΦS < 2φF is known as weak inversion.

The various energy band diagram of a MOSFET during accumulation, and weak inversion are shown in Fig. 5.8.

The sub-threshold current IDS-Sub can be proved to be equal

( )

−−

η−

µ=− kT

qVexp1

kT

VVqexp

q

kT

L

WCI DStGS

2

oxnSubDS (5.40)


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where µn is the electron mobility, Cox is the gate capacitance per unit area, W is the channel width, L is the channel length, Vt is the threshold voltage of the MOS, and η is the sub-threshold parameter related to the sub-threshold swing S which is the gate voltage change needed to raise the sub-threshold current by one decade following the relation S = ηVT (ln 10). The sub-threshold parameter η is given by

η = +1C

CD

ox

(5.41)

where CD is the depletion channel capacitance per unit area.

Figure 5.8: Energy band diagrams of n-MOSFET showing accumulation and weak

inversion modes

5.4.2 Channel Length Modulation As the drain to source voltage VDS exceeds VDSSAT, the drain to source current IDS is independent of the VDS. In reality there is a shortening of the channel ∆L, which is supported by the excess voltage ∆VDS = (VDS - VDSSAT).

The depletion width at drain WD is governed by equation

A

DSFSD qN

]V2[2W

+φε= . The incremental change in depletion length which is also

equal to ∆L, is equal to


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[ ]DSSATFDSDSSATFA

S V2VV2qN

2L +φ−∆++φ

ε=∆ (5.42)

The drain current I DS

' with channel modulation taken in account shall be what is shown in equation (5.38).

IL

L LIDS DSSAT

' =−

∆ (5.43)

The result shows that there is an increase of output conductance of the device as the drain to source VDS exceeded the saturated drain to source voltage VDSSAT. 5.4.3 Mobility Variation In reality there are two factors influencing the mobility of carrier in MOSFET. The increase of gate voltage forces the carrier to move closer to the interface whereby the roughness and oxide impurities cause higher degree of scattering on the carrier due to coulumbic interaction. The effective mobility of the carrier decreases as its drift velocity Vdrift approaches saturation limit. Figure 5.7 shows the results of deviation of ideal drain current characteristic due these effects.

For a small electric field, the mobility is constant with respect to drift velocity. At high electric field, the mobility is no longer constant and will be degraded until it reaches zero when the drift velocity of the carrier reaches its saturation velocity.

The relationship between the inversion charge mobility and transverse

electric field is usually measured experimentally. The effective transverse electric field Eeff for electron is defined as

E Q QeffS

DEP n= +

1 1

2ε (5.44)

However, for hole with mobile charge Qp, equation (5.39) has to be modified slightly to

E Q QeffS

DEP p= +

1 1

3ε (5.45)


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The effective inversion mobility can be determined from the channel conductance as a function of gate voltage. The effective inversion mobility µeff is defined as

µ µeffeffE

E=

−

00

1 3/

(5.46)

where µ0 and E0 are experimentally determined constants. Based on equation (5.41), the experimentally results of electron mobility versus effective transverse electric field at inversion is shown in Fig. 5.9.

The linear drain to source current equation, equation (5.25)

−−

µ=

2

VV)VV(

L

CWI

2DS

DStGSoxn

DS should be modified to equation (5.47) by

adding in the scattering effect of mobility, which is equation (5.23) and (5.46).

[ ]

−−

⋅

−θ+µ

=−

2

VV)VV(

E

E

)VV(1L

CWI

2DS

DStGS

3/1

o

eff

tGS

oxoDS (5.47)

Figure 5.9: Experimental results of electron mobility versus effective transverse electric

field at inversion

Many other non-deal characteristics of the MOSFET device such as narrow width effect, hot electron, energy band-gap narrow etc are not covered in this chapter. Students are advised to read for self knowledge improvement.


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5.5 Parasitic Components of MOSFET MOSFET is normally used for switching and voltage gain. There are number of parasitic components associated with the structure. It contains parasitic resistance and capacitance that affects the circuit operation. These components cannot be eliminated especially in high-speed device operation. We shall discuss these two components in detail. 5.5.1 Parasitic Resistance The resistance of MOSFET is not linear as we can see from the output characteristic of the MOSFET, despite the fact, the term linear time-invariant LTI is used to provide information about the drain to source flow. Since the resistance is not linear, therefore, the resistance Rn is depending on the point where it is taken. Using n-MOS transistor as an example, the non linear

resistance is governed by Rn = DS

DS

dI

dV, which is the reciprocal of conductance

shown in equation (5.30). i.e.)VV(WC

LR

ntGSoxnn −µ

= . The saturation resistance

Rn is obtained from equation 2

ntGSoxn

DSn )VV(WC

LV2R

−µ= . Since the digital

electronics works in linear region, therefore, the linear equation is used for calculating the drain to source resistance Rn or Rds. Since the logic voltage is either VDD or VSS, the VGS voltage or VSG voltage is equal to VDD. Thus, turn-on resistance Rn is equal to

)VV(WC

LR

ntDDoxnn −µ

= (5.48)

and

( )ptDDoxp

pVVWC

LR

−µ= (5.49)

5.5.2 Parasitic Capacitance MOSFET has a number of parasitic capacitances. They are shown in Fig. 5.10. These capacitances are function of voltage and dimensions. CDB and CSB are


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depletion capacitances due to pn junction of the MOS transistor. The other three

capacitance CGS, CGD, and CGB are related to MOS capacitance COX = OX

OX

d

WLε.

Figure 5.10: Capacitance of MOSFET

In VLSI or semiconductor physics, MOS capacitance is usually expressed in

farad per unit area. By default COX is equal to OX

OX

d

ε. The gate to backward

capacitance CGB is equal to COXWL. CGB is also called gate capacitance CG at cut-off region, which is gate capacitance at zero gate-to-source voltage.

Figure 5.11 illustrates the relationship of gate-channel capacitance with respect to various gate to source voltage.

Figure 5.11: Gate-channel capacitance as the function of gate-source voltage


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Based on the results, it shows that the capacitance CGS and CGD are

approximately equal to GBC3

2 and 0 respectively for saturation region. For triode

region, the capacitance CGS and CGD are approximately equal to GBC2

1and GBC

2

1

respectively at zero bias, which is OXC2

1 . Please note the capacitance mentioned

in this paragraph has unit of farad.

Based on capacitance distribution of a MOS transistor shown in Fig. 5.10, the linear time-invariant model of the MOS transistor shall be as shown in Fig. 5.12.

Figure 5.12: The linear time invariant model of a MOS transistor

Source and drain capacitance CS and CD are respectively equal to CS=CGS+CSB and CD=CGD+CDB. These capacitance values are used partially to determine the switching times of the MOS transistor device.

In linear operation, which is the operation for digital device, CGS and CGD

are equal to half of CG, which is WLC2

1OX⋅ as illustrated in Fig. 5.11. The

depletion capacitance CSB and CDB are respectively equal to the sum of bottom capacitance and sidewall capacitance of the drain or source of the device. They are calculated by approach discussed in the following paragraph.

The drain or source structure of the MOS transistor is shown in Fig. 5.13(a). You can view the drain and source as a rectangular tray with a bottom plate of side W by X and side wall of W by xj and X by xj. Its corresponding bottom structure and side-wall structure are shown in Fig. 5.13(b) and Fig. 5.13(c) respectively.


- 107 -

Figure 5.13: (a) Drain/source structure of MOS transistor (b) bottom structure and (c) side-

wall structure

The capacitance Cn of the source or drain of the n-MOSFET is equal to the sum of bottom capacitance Cbot and the side wall capacitance Csw. Cn = Cbot + Csw (5.50) The bottom capacitance Cbot is equal to CjXW, where Cj is the junction capacitance per unit area, X is the length of the drain or source. Cn is also equal to CDB or CSB values.

The side wall capacitance Csw of W side is equal to CswL = CjswW (5.51) where Cjsw is junction capacitance per unit area multiplied by the thickness xj of drain or source i.e. Cjsw = Cjxj. The total side wall is (2W+2X). Therefore, the total side wall capacitance is Csw = Cjsw(2W+2X) = CjswP, where P is the


- 108 -

perimeter of the drain or source. The total capacitance of the drain or source Cn is Cn = CjbotXW + Cjsw(2W+2X) (5.52) The capacitance shown in equation (5.52) is the zero voltage bias capacitance. This is the value usually used to model the timing of the MOS transistor since zero voltage bias has the maximum capacitance.

Junction capacitance at time is called as depletion capacitance. The junction capacitance Cj of the n-type source or drain with the p-type substrate is

based on equation 2/1

Rbi

AS

)VV(2

NqC

+ε

=j . If we denote Co as the zero bias voltage

junction capacitance, then 2/1

Rbi

AS

)VV(2

NqC

+ε

=j becomes

bi

R

o

2/1

bi

R

R

AS

V

V1

C

V

V1

V2

Nq

C

+=

+

ε

=j (5.53)

where Vbi =

2i

DA

n

NNln

q

kT and VR denotes built-in potential and bias voltage

respectively. In general equation (5.53) can be written as

m

bi

R

om

V

V1

CC

+

=j (5.54)

where m denotes grading parameter and is a value less than one. For m =1/2 denotes abrupt or step junction, whereas m = 1/3 denotes gradual junction and etc. Com denotes the junction capacitance at zero bias voltage for an m graded junction.

Usually, we take the side-wall junction of the drain/source of the MOS transistor as a linearly graded junction, whilst the bottom junction of the drain/source of the MOS transistor has the abrupt junction. Thus, their grading parameter m are 1/3 and 1/2 respectively. Combining equation (5.52) and


- 109 -

equation (5.54), the drain/source capacitance of the MOS transistor follows equation (5.55).

3/1

bis

R

2/1

bi

R

Rn

V

V1

)XW(2C

V

V1

WXC)V(C

+

++

+

=

w

jsw

bot

jbot (5.55)

Since the output changes from V1 to V2 and vice versa, the average drain/source capacitance Cnavg is equal to

+

⋅++

+

⋅−

= ∫∫2

q

2

1

V

V3/1

bis

R

RV

V2/1

bi

R

R

12Rnavg

V

V1

dV)XW(2C

V

V1

dVWXC

)VV(

1)V(C

w

jsw

bot

jbot (5.56)

Let R

V

V2/1

bi

R12212/1 dV

V

V1

WXC

)VV(

1WXC)V,V(K

2

1

⋅

+

⋅−

= ∫

bot

jbotjbot and

R

V

V3/1

bi

R12213/1 dV

V

V1

)XW(C2

)VV(

1)XW(2C)V,V(K

2

1

⋅

+

+⋅

−=+⋅ ∫

sw

jswjsw . Equation (5.56) shall

become Cnavg(VR) = WXC)V,V(K 212/1 jbot + )XW(2C)V,V(K 213/1 +⋅jsw .

For m grading parameter,

R

V

Vm

bi

R1221m dV

V

V1

1

)VV(

1)V,V(K

2

1

⋅

+

⋅−

= ∫

sw

(5.57)

The integration result of equation (5.57) yields equation (5.58).

+−

+

−+−=

+−+− )1m(

bi

1

)1m(

bi

2

12

bi21m V

V1

V

V1

)VV)(1m(

V)V,V(K

(5.58)


- 110 -

where Km(V1,V2) is called linear time-invariant factor LTI. Usually the bias voltage V2 and V1 are respectively equal to VOH and VOL. Therefore, equation (5.58) is equal to

+−

+

−+−=

+−+− )1m(

bi

OL

)1m(

bi

OH

OLOH

biOHVOLm V

V1

V

V1

)VV)(1m(

V)V,V(K

(5.59)

5.6 Junction Leakage Current The pn junctions formed by the drain to bulk and source to bulk interfaces in a MOS transistor introduce leakage current that is often important in high-performance circuit design. Consider the drain of a MOS transistor shown in Fig. 5.14 is reverse biased by drain-to-source voltage.

Figure 5.14: Drain of the MOS transistor under reverse biased condition

The junction leakage current IR is equal to

IR = Io + Igen (5.60) where Io is the reverse saturation current and Igen is the re-generation current. The re-generation current is equal to

−+

τ≈ 1

V

V1

2

dqAnI

bi

DSdepMinigen (5.61)


- 111 -

Usually the reverse saturation current is very small that can be ignored. The reverse bias current of the drain-to-substrate junction is equal to

−

+

τ≈ 1

V

V1

2

dqAnI

m

bi

DSdepMiniR (5.62)

where m is grading factor.

The switching model of the MOS transistor taken into account the parasitic capacitance, resistance, and leakage current shall be shown in Fig. 5.15.

Figure 5.15: An n-MOS transistor switching model

5.7 Scaling Theory of MOSFET In order to achieve higher density logic integration, the approach is to develop sub-micron size device structures. Effects which are negligible in large MOS transistor become distinct and extremely important when the transistor dimensions are reduced. Scaling theory provides a general guide to make MOS transistor smaller. It is not possible or desirable to follow every aspects of the theory. However, it remains a useful metric for measuring progress in device physics especially the simulation or prediction of the behavior of the device with smaller dimension.

Scaling theory deals with the question of how the device characteristics are changed as the dimensions of the device are reduced in an idealized well-defined manner. Scaling theory is ideal ignoring many small-device effects that govern the performance of MOS transistor. It is often desirable to adhere to the large device models for simplicity but modify the parameters to account for the more important changes in the transistor parameters. Scaling of the device to smaller dimension affects parameters such as threshold voltage and mobility.


- 112 -

Smaller channel length decreases the threshold voltage. Narrower device increases threshold voltage. Small channel length increases horizontal electric field that causes the MOS transistor to operate with saturation velocity. This reduces the drain current of the device. High electric field means high energetic carrier that can enter the oxide to become trapped charge and affects the threshold voltage of the MOS transistor.

The drain and source of the MOS transistor are usually much heavily

doped than the bulk. Couple with high electric field, hot ion tunneling is unavoidable. This issue causes leakage. In order to resolve this problem, lightly doped drain LDD approach is adopted for the design of small dimension MOS transistor.

Several schemes can be constructed from scaling rules shown in Fig. 5.16.

S is the dimensional scaling factor and k is factor by which voltages are scaled. One of the earlier scaling methodologies is based on constant-field scaling, which keep electrical field constant. In this method S is makes equal to k. This approach is theoretical viable that has to increase the speed, reduction of voltage swing and capacitance. It is being used to scale to 1.0µm. Scaling to 1.0µm is in fact closed to constant-voltage scaling, which is by making k = 1. In this approach voltage swing stays the same, but device current increases due to increase of oxide capacitance Cox. Since drive current increases roughly as the square of supply voltage, constant-voltage produces more speed improvement than constant-field scaling.

Parameters Variables Scaling Factor

Dimensions W, L, dox, xj 1/S Potentials Vds, Vgs 1/k Doping concentration NA, ND S2/k Electric field E S/k Current Ids S/k2 Gate delay tdelay k/S2

Figure 5.16: Generalized scaling theory for MOS transistor

Using constant-voltage approach and considering a MOS transistor with a channel width W and a channel length L such that the channel area is A = LW and introducing the concept of a scaling factor S >1, a new scaled device is

created with reduced dimensions W’ and L’ where S

WW ' = and

S

LL' = . The

reduced scaled area A’ is equal to 2

'

S

AA = . Similarly, the oxide thickness is


- 113 -

S

dd ox'

ox = . Thus, the reduced oxide capacitance is oxox

ox'ox SC

dSC =

ε⋅= . Similarly,

the reduced process parameter SKK ' = and device parameter is β=β S' .

Threshold voltage 'tV and drain-to-source voltage 'DSV are to be scaled. With all

parameters being scaled down, the scaled down drain current is S

II D'

D = .

5.8 MOSFET Modeling In this section, we shall discuss the model parameters for various type of model used for VLSI design and simulation. The center of modeling targets at the PSPICE model of the CMOS. Note the SPICE is the acronym for Simulation Program with Integrated Circuit Emphasis. It is originated from University of California at Berkeley. PSPICE is one of the many commercial SPICE derivatives that have been developed by MicroSim Corporation.

Modeling is written equation that relates voltage and current to predict the behavior of a single device and consequently the behavior of a complete circuit. Three generation of model shall be introduced. They are model 1, semi-empirical model 3 for greater than 2µm device and BSIM4 model for less than 2µm device down to 90nm simulation. 5.8.1 MOSFET Level 1 Level 1 SPICE model of MOSFET implements the Schichman-Hodges model, which is based on the square law, long-channel expression derived earlier in this Chapter. It does not handle short-channel effect. The set of equation relating the current and voltage characteristics termed as model 1 equation was first developed in 1952 by William Shockley. The level 1 equations are modified from equation (5.11), (5.28), and (5.29) that includes channel shortening effect λ discussed in the earlier part of this chapter. The equations are oxSUBFASFt C/)V2(qN22VV +φε+φ+= fb (5.63)

( )DS

2DS

DStGSoxn

DS V12

VV)VV(

L

CWI λ+

−−

µ= (5.64)

( ) ( )DS

2tGS2

tGSoxn

DSSAT V12

)VV(VV

L

CWI λ+

−

−−µ

= (5.65)


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= ( )DS2

tGSoxn V1)VV(

L2

CWλ+−

µ

If there is no substrate voltage VSUB, in which sometime is called zero body bias then equation (5.63) becomes oxFASFto C/)2(qN22VV φε+φ+= fb , where Vto is

the threshold voltage without substrate voltage or body bias voltage. The equation (5.63) can be re-written in terms of Vto and substrate voltage and etc as

( )FSUBFOX

AStot 2)V2(

C

qN2VV φ−−φ

ε+= (5.66)

The term OX

AS

C

qN2ε is denoted as gamma γ, which is bulk threshold parameter.

Equation (5.67) shall be ( )FSUBFtot 2)V2(VV φ−−φγ±= (5.67)

The ± sign is used to denote one for n-MOS transistor and one for p-MOS transistor. In order to eliminate the effect of parasitic npn or pnp transistor of the n-MOS transistor and p-MOS transistor, the substrate of the p-MOS transistor, which is n-type semiconductor, is usually biased with VDD voltage, whilst the substrate p-MOS transistor, which is p-type semiconductor, is biased with VSS voltage i.e. zero volt. Equation (5.67) therefore can be written as one equation for p-MOS transistor and one for n-MOS transistor. They are ( )FSSUBDDFtpotp 2)VV2(VV φ−−+φγ−= − (5.68)

( )FSUBSFtnotn 2)V2(VV φ−+φγ+= − (5.69)

W/L is the aspect ratio, one of the parameter used to determine the current capability of the MOS transistor. OXnCµ is named as process

transconductance parameter K. L

WCOXnµ is denoted as device transconductance

β. Equation (5.30) and (5.34) can be re-written as

( )DS

2DS

DStGSDS V12

VV)VV(I λ+

−−β= (5.70)


- 115 -

( )DS2

tGSDSSAT V1)VV(2

I λ+−β= (5.71)

This model is accurate only if the device has large parameter values. It is not accurate especially for small channel device. 5.8.2 MOSFET Level 2 The level 2 model is a geometry-based model, which uses detailed-device physics to define its equation. To obtain more accurate model for drain current, it is necessary to eliminate the assumption made in gradual channel approximation analysis. The channel depletion thickness dependents on the channel voltage instead gradually change. It also handles effects due to velocity saturation, mobility degradation, and drain-induced barrier lowering DIBL. The drain to source current IDS is following equation (5.72) after adding in the substrate voltage VSUB.

DSDS

FGSeff

DS V2

V2VV

L

KI

−φ−−= fb

( ) ( )[ ]−φ−−φ+γ− 2/3

SUBF2/3

SUBFDS V2V2V3

2 (5.72)

where Leff is the effective channel length that follow equation Leff = L-2LD. L is being the physical length of oxide and LD is the length of the overlapping oxide with drain and source.

At saturation IDS = IDSSAT, VDS = VDSSAT = VG – Vt, equation (5.72) becomes

( )tGStGS

FGSeff

DSSAT VV2

VV2VV

L

KI −

−−φ−−= fb

( ) ( )[ ]−φ−−φ+−γ− 2/3

SUBF2/3

SUBFtGS V2V2VV3

2 (5.73)

The zero substrate voltage threshold voltage Vto is equal to

Vto = FFOX

TGC 22

C

qNφγ+φ+−φ (5.74)


- 116 -

where φGC is equal to gate to channel work function and NT is the trap surface density. level 2 is better than level 1 but its accuracy is still not sufficient to achieve good agreement with experiment results especially for short-channel and narrow width device. Owing to this problem, a number of semi-empirical corrections have to be added. Some of these corrections are discussed in Section 5.4, the non-ideal effect of MOS transistor. The corrections added are variation of mobility with electric field, variation of channel length in saturation mode, saturation of carrier velocity and sub-threshold correction. 5.8.3 MOSFET Level 3 MOSFET Level 3 is a semi-empirical model and was developed for simulation of short-channel MOS transistor down to 1.0µm channel length. The equation for level 3 is similar to MOSFET level 2 except the linear equation is expanded using Taylor’s series to the manageable order. The short channel effect and small geometrical effect like narrow width effect are added to the model. Thus, the linear drain current equation is

DSDSB

tGSeff

OXSDS VV

2

F1VV

L

WCI

+−−

µ= (5.75)

where FB = n

SUBF

S FV24

F+

+φ

γ. It is dependent on bulk depletion charge on three

dimensional geometry of MOS transistor. Parameters µS and FS are influenced by short-channel effect. The surface mobility µS dependent on gate voltage is given by

)VV(1 tGS

S −θ+µ=µ (5.76)

5.8.4 BSIM4 Model BSIM4 model is developed by University of California at Berkeley. It is the abbreviation for Berkeley Short-Channel IGFET. This model is basically derived from level 3 and it is analytically simple. The parameters are normally extracted from experimental data that makes this model one of the most popular SPICE MOSFET model. Currently BSIM3 model (denoted as Level 49) is denoted as version of BSIM and is widely used by foundry to accurately model the behavior of the deep-submicron MOSFET. It contains over 200 parameters. The majority of which are related to the modeling of second-order effect. The


- 117 -

effects due to channel shortening, non-uniform lateral doping effect and the change of threshold voltage caused by drain-induced barrier lowering DIBL are taken into considerations. Thus, this affects the mobility, threshold voltage and the effective channel length of the device. The threshold voltage formula is now equal to ( ) DIBL,tNULD,tSCE,tSUB2FSUBF1tot VVVV2)V2(VV ∆+∆+∆+γ−φ−−φγ±=

(5.77) where ∆Vt,SCE is the reduction due to channel effect. ∆Vt,NULD is due to non-uniform lateral doping effect. ∆Vt,DIBL is due to drain-induced barrier lowering DIBL effect. 5.8.5 SPICE Software There are many SPICE softwares available in the market. Among them are WINSPICE, AIMSPICE, LTSPICE, HSPICE, and PSpice. One can also use WinSpice to perform simulation of any MOSFET circuits, bipolar junction transistor circuits, and etc. An example of the WINSPICE program script is shown in Fig. 5.17. The simulation is done for a MOSFET device of L=1.0µm and W=10.0µm using 1.0um Level 3 models for the CMOS Circuit Design, Layout, and Simulation specified in file “cmosedu_models.txt”. The drain current ID versus drain-to-source voltage VDS plot specified for VDS voltage ranges from 0 to 1.0V with 1.0mV interval and gate-to-source voltage VGS ranges from 0 to 1.0V in 0.25V interval. *** SPICE Circuit File of MOS 02/27/09 *#destroy all *#run *#let id=-i(vds) *#plot id vds d s DC 0 vgs g s DC 0 .dc vds 0 1 1m vgs 0 1 0.25 *Important .options scale=50nm *ground the source Vs s 0 DC 0 M1 d g s 0 N_50n L=1 W=10 .include cmosedu_models.txt .END

Figure 5.17: The WinSpice script of the characteristics of an MOSFET


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The results of simulation for the output characteristic of the MOS transistor are shown in Fig. 5.18.

Figure 5.18: WinSpice simulation result of output characteristic of an n-MOS transistor

Exercises 5.1. Find the work function difference for an n-type polysilicon gate n-MOS

transistor that has poly gate doping concentration and substrate doping concentration of 1.5x1019cm-3 and 1.0x1015cm-3 respectively.

5.2. The work function difference between Al-SiO2-p-type silicon MOS

transistor is -0.15V given concentration of p-type is 1.0x1012cm-3 and the work function of Al is 4.28V. Calculate the value of the work function constant ∆Φ for the device.

5.3. If the thickness of the oxide for the Al-SiO2-p-type silicon MOS is 600A0

, the flat-band potential is -0.87V, and the concentration of p-type semiconductor is 5.0x1016cm-3, calculate the threshold voltage Vt of the MOS.

5.4. A MOS capacitor has an aluminum gate and p-type substrate with doping

concentration 5.0x1016cm-3. Its oxide thickness is 450Ao

and cross sectional area is 1x10-2cm2. Calculate the oxide capacitance.


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5.5. Consider an n-MOS transistor with gate width W = 10µm and gate length L = 1.5µm and oxide capacitance Cox = 10-7F/cm2. In the linear region for a fixed VDS = 0.1V, the drain current is found to be 40µA for VGS = 1.5V and 80µA for VGS = 2.5V respectively. Calculate the threshold voltage Vt and mobility µn of this MOSFET.

5.6. An n-MOS transistor has effective mobility of 750cm2/V-s, channel

length L of 1.0x10-4cm, threshold voltage Vt of 1.5V, and gate voltage VG 3.0V for a small signal application. Calculate the cut-off frequency using constant mobility model and the case of having short-channel effect where the saturation velocity of the carrier is 107cms-1.

5.7. Consider an n-MOS transistor has channel width W = 8µm and channel

length L = 0.5µm and is made of process where process transconductance K = 180µA/V2, Vtn = 0.7V and VDD = 3.3V. Calculate the linear drain to source resistance.

5.8. Consider an n-MOS transistor that is characterized by oxide thickness

80o

A , substrate doping concentration 1.2x1015cm-3, doping concentration of n-type poly gate 1x1019cm-3, fixed oxide 1x1011x1.602x10-19Ccm-2 and receiving acceptor ion implant dosage of 2x1012cm-2 for threshold adjustment.

(i) Calculate the threshold voltage of this MOS transistor at room

temperature. (ii) If the substrate of this MOS transistor is biased with 1.0V, what is

the ion implant dosage required to maintain same threshold voltage? 5.9. An n-MOS transistor has the following information: Oxide thickness dox

= 1000

A , substrate doping concentration NA = 8x1014cm-3, zero bias substrate threshold voltage Vtno = 0.6V and mobility µn = 580cm2/V-s. Calculate the process transconductance K and bulk-threshold parameter γ of the device.

5.10. A step graded pn junction has doping concentration NA= 8x1014cm-3 and

ND = 7x1019cm-3 respectively. (i) Find the built in potential Vbi. (ii) Find the depletion thickness ddep. (iii) Find the value of zero-bias junction capacitance Cj0.


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Bibliography 1. John P. Uyemura, “Chip Design for Submicron VLSI: CMOS Layout and

Simulation”, Thomson, 2006. 2. John P. Uyemura, “Introduction to VLSI Circuits and Systems”, John

Wiley & Sons, Inc. 2002. 3. Etienne Sicard and Sonia Delmas Bendhia, “Basics of CMOS Cell

Design”, TATA McGraw Hill, 2006. 4. Sung-Mo Kang and Yusuf Leblebici, “CMOS Digital Integrated Circuits

Analysis and Design”, third edition, McGraw Hill, 2005. 5. Jasprit Singh, "Semiconductor Device", McGraw Hill Inc. 1994. 6. Robert F. Pierret, "Semiconductor Fundamentals", Volume I Modular

Series on Solid State Devices, second edition, Addison-Wesley Publishing Co. 1989.

7. John P. Uyemura, “CMOS Logic Circuit Design”, Kluwer Academic Publishers, 2002.

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