73

CHAPTER -4

STUDY OF COMMON MODE VOLTAGE IN 3-LEVEL INVERTER FED INDUCTION MOTOR DRIVE USING SPACE VECTOR MODULATION

4.1. INTRODUCTION

Multilevel inverters [51] have attracted much interest from the

researchers especially in applications involving high voltage and high

power such as the utility and large motor drive applications (Peng, 2000).

This increased recognition of MLI is due to the limitations of the

conventional 2-level output inverters in handling high power

conversions. The MLI can be developed by either using multiple 3-phase

bridges or by increasing the number of switching devices per phase, in

order to increase the number of levels. The concept of MLI involves in

utilizing an array of series switching devices to perform the power

conversion in a small increase of voltage steps by synthesizing the

staircase voltage from several levels of DC capacitor voltages (Skvarenina,

2002; Soto and Green, 2002; Rodriguez et.al., 2002).The advantages of

MLI are the dv/dt stresses on the switching devices are reduced due to

the small increment in voltage steps, reduced electromagnetic

compatibility (EMC) when operated at high voltage (Skvarenina, 2002),

smaller rating of semiconductor devices (Lai and Shyu, 2002) and better

feature of output voltage in term of less distortion, lower harmonics

contents and lower switching losses (Feng and Agelidis, 2004; Peng,

2000).

74

As the numbers of levels are increased, the amount of switching

devices and other components are also increased tremendously, making

the inverter becoming more complex and costly. This is one of the

disadvantages of MLIs. A complicated controller with a proper gate drive

circuit is needed to control and synchronize the switching devices.

Higher number of levels also means that the numbers of DC capacitors

used are substantial, which could cause voltage imbalance among the

DC capacitors that may results in overvoltage in one or more of the

switches [51].

This chapter presents the 3-level neutral point clamped inverter

structure with 3-phase IM as load. In this proposed work, the inverter

bridge is made using MOSFET devices and controlled by using space

vector modulation. The gating signals have been generated using PIC µ-

controller and it is added with additional auxiliary circuit. For the

generation of gating signals, the space vector diagram of the 3-level NPC

inverter is considered. The measurement of phase voltage, line voltage

and CM voltage is done. The working of the 3- level Inverter fed IM is

satisfactory for the rated 3-phase voltage of 415V. Simulation is done

using MATLAB/SIMULINK software and the experimental results are

compared with simulation results. For experimentation 450 V DC is used

as an input to the 3-phase inverter circuit. In order to protect the

switching devices of the inverter circuit, Undeland snubber circuit is

used.

75

4.2. LITERATURE SURVEY

The MLIs are started with 3-level inverter which is introduced by

Nabae et al. [6, 39]. Since then considerable research has been done in

this area with different modulation schemes, each of which has its own

advantages and disadvantages. The MLIs have found wide acceptability

in adjustable speed IM drive applications because of less distortion in

the inverter output voltages [39, 45]. Since the MLIs have many

switching states, the inverter output voltage is closer to sinusoidal

voltage which tends to reduce CM voltage, EMI, harmonics voltages and

less dv/dt stress on the devices when compared to 2- level inverter.

MLIs are considered as the best alternative in high-power medium-

voltage power control. The important structures of MLIs are (1) diode-

clamped inverter (neutral-point clamped) (2) capacitor-clamped inverter

(flying capacitor) and (3) cascaded multi cell with separate DC sources.

Fig. 4.1[17, 38] shows a schematic circuit diagram of one phase leg of

inverter with different numbers of levels.

Fig.4.1.One phase leg of an inverter (a) 2- level, (b) 3- level, and (c) n- levels.

As the number of levels of the inverter increases, the output voltages

have more steps which generate a staircase waveform. There are several

76

modulation schemes adopted for MLIs; they are multilevel sinusoidal

pulse width modulation (SPWM), multilevel selective harmonic

elimination and space-vector modulation (SVM).

4.2.1. Multi-level (3-Level) NPC inverter Fig.4.2 shows the 3- level NPC inverter connected to 3-phase IM [6,38

& 39]. The system is constituted with DC supply, and a 3- level voltage

source inverter, based on MOSFETs as devices. Each arm contains four

MOSFETs, four anti-parallel diodes and two neutral clamping diodes.

The inverter is feeding a 3- phase IM. In Fig.4.2 “0” indicates the neutral

point with respect to the DC source. (S1a, S4a), (S1b, S4b), (S1c S4c), are the

main inverter devices operating as switches for PWM and (S2a S3a), (S2b,

S3b), (S2c, S3c) are auxiliary devices to clamp the output terminal

Fig.4.2. Power circuit diagram of 3- level inverter.

potentials to the neutral point potential, together with (D1a–D3c). SVM

method is applied for the inverter circuit (Fig.4.2). In order to obtain the

desired 3-level voltages, the inverter must ensure complementarities

77

between the pairs of switches; (S1a, S3a) and (S2a, S4a). Output terminal

potentials of the conventional 2-level inverter vary between (+Vdc/2) and

(-Vdc/2), but in the NPC-3-level inverter the potentials vary between

(+Vdc/2) and (0) or (-Vdc/2) and (0). The 3- level “NPC” Inverter is shown

in Fig.4.2 consists of two capacitors in series and uses center tap as the

neutral [17, 62]. Each phase leg of 3-level inverter has two pairs {2(m-1)}

switching devices, (m=level=3). The center of each device pair is clamped

to neutral through clamping diode [62]. The DC bus capacitors need to

be connected in series to get the midpoint that provide the zero voltage at

the output. The switching state of the 3- level inverter and its output is

as shown in Table 4.1[38, 39 and 62].

Table- 4.1 Switching states of a 3- level inverter (x= a, b or c)

Switching

states S1x S2x S3x S4x SxN

P ON ON OFF OFF Vdc/2

O OFF ON ON OFF 0

N OFF OFF ON ON -Vdc/2

4.3. GENERATION OF SVM SCHEME FOR NPC 3 - LEVEL INVERTER

4.3.1. Basic Principle of 3- level Inverter There are 3 kinds of switching states P, O and N in each phase, so

there will be 27 {mp, where m= the no. of levels and p= the no. of phases

(33)} switching states in 3-phase 3- level inverter. The output space vector

78

is identified by combination of switching states P, O, N of the three legs.

For example, in the case of P, O, N the output terminals a, b and c have

the potentials Vdc/2, 0, and –Vdc/2 respectively. By using the space

vector diagram shown in Fig 4.3[62], the basic principles of the simplified

SVM method can be easily understood.

Fig.4.3. Space vector diagram of a 3- level inverter

The modulating command voltages of a 3-phase inverter are always

sinusoidal and therefore they constitute a rotating space vector V*. Fig.

4.4 shows a convenient way to calculate the reference vector V* by using

the adjacent vectors V1 and V2 to satisfy the average output demand. Va

and Vb are the components of V* aligned in the directions of V1 and V2

respectively.

79

Fig.4.4. Calculation of reference vector V*

In each switching period, the required (sampled) reference voltage

vector is realized by using two directly adjacent active vectors; their duty

ratios are determined in such a way that the real output voltage vector,

when averaged over one switching cycle, coincides with the reference

vector. The two active vectors occupy only part of a switching cycle, the

rest has to be filled out by using null vectors and is called null-vector

time. Considering the period ‘ Tc’ during which the average output

should match the command voltage. Time intervals ‘ta’ and ‘tb’ satisfy the

command voltage but time to fills up the remaining gap for ‘Tc’ with zero

or null vectors.

V* = Va + Vb (4.1) V* = V1(ta/Tc) + V2(tb/Tc) + (V0 or V7)(t0/Tc) (4.2) Ta = (Va/V1) Tc (4.3) Tb = (Vb/V2) Tc (4.4) T0 = Tc – (ta + tb) (4.5)

V0 or V7 are chosen to minimize switching. Ts = 2 Tc = 1/fs

Where fs = Switching frequency.

80

4.3.2. Calculation of reference voltage vector In this section, the procedure for calculation of the reference voltage

vector for the simplified 3- level space vector PWM method is described .

The magnitude and direction of the reference voltage vector V* can be

found with the help of adjacent vectors whose magnitude and direction

are already known. If the reference voltage vector V* lies in the region as

shown in Fig. 4.3, the adjacent switching states (PNN) and (PON) can be

used to evaluate the magnitude and direction of vector V*. Fig.4.4 shows

the adjacent vectors Va and Vb which can be used for this purpose. Fig.

4.5 shows the simplification in calculating the reference vector V*. From

Fig. 4.5, the following expression can be obtained [62].

Fig. 4.5. Simplification in calculation of reference vector V*

Vb/2 = V* sinc (4.6)

Vb = 2 V* sinc (4.7) Va/2 = V* sin (30 – c) (4.8) Va =2 V* sin (30 - c ) (4.9) Space vector calculation and vector location:-This section determines the

magnitude and direction of the reference voltage vector V*.

81

The simplification of the expression for space vector leads to

V* = 2/3 (Vas + a Vbs + a2 Vcs) [33] (4.10) a = e j2π/3 (4.11) a2 = e j4π/3 (4.12)

Vas, Vbs and Vcs are the stator phase voltages of 3-phase balanced system.

The parameters a and a2 can be interpreted as unit vectors assigned to

the respective bs and cs axes of the machine, and the reference axis

corresponds to Vas axis. Using the three phase to two phase

transformation, the three phase modulation waves are converted into

magnitude (V*) and direction (α) with the help of the expression obtained

for space vector.

4.4. GATE DRIVE CIRCUIT

Fig.4.6. Gate drive circuit

The gate drive circuit is shown in Fig. 4.6. Only the outermost twelve

voltage vectors of the 3-level space vector diagram are considered for the

generation of gating signal since the other voltage vectors are redundant.

Table 4.2 shows [62] the switching sequence of 3-phase 3-level inverter,

82

in which the outermost voltage vectors are listed. The selection of the

voltage vectors are taken vertically from Table 4.2 for the 12 switching

state vectors. The switching pattern of the devices is drawn manually

which is as shown in Fig. 4.7. Here “a1”, “a2” represents the switching

pattern of first leg (a-phase) top switches and for the bottom devices of

the first leg the inversion of the signal is taken respectively ( ā1 & ā2). In

the similar way “b” and “c” phases is also shown as in Fig.4.7.

PIC16F877 µ-controller was used for the generation of gating signals. Six

gating signals were generated by using the µ-controller for the top side

devices and for the bottom side the inverted signals of the top side (using

7404 hex inverter) signals were used. Hence the total 12-gating signals

are recorded using the MSO is as shown in Fig.4.7 (a). The PIC 16F877 µ-

controller program for generation of gating signal is given in Appendix-4.

Table- 4.2.Switching Sequence of 3-level inverter

Phase Outermost Voltage Vector

a 0 P P P P P 0 N N N N N

b P P 0 N N N N N 0 P P P

c N N N N 0 P P P P P 0 N

83

Fig.4.7. Gating signal generation (switching pattern drawn manually)

84

Fig.4.7(a). Gating signal generation obtained from MSO

The high voltage of the inverter is isolated from the low voltage gating

signals by using the opto-isolator. The opto-isolator (6N139) is used since

its isolation voltage is 5kV. The output of 6N139 is fed to the gate of the

corresponding switching devices of the 3-level inverter bridge. The opto-

isolators are supplied with separate DC power supply for isolation

purpose. Necessary interface circuits are provided. 2SK962 power

MOSFETs were used with anti-parallel fast recovery diodes. The

Undeland snubber circuit was used for reducing the voltage stress on the

devices. Fig. 4.7(b) shows the phase to fictitious middle point voltage pole

voltages, (Analog Ch1.Vao, Analog Ch2. Vbo, Analog Ch3. Vco.) and the 12

digital gating pulses are also shown (D1-D12). The pole voltages and the

digital pulses are captured at the same instant of time which is useful for

verifying the pole voltages.

85

Fig.4.7 (b).Pole voltages (phase-to-fictitious middle point voltage) Analog Ch1.Vao, Analog Ch2. Vbo, Analog Ch3. Vco.

Digital gating pulses D1-D12.

4.5. SNUBBER CIRCUIT FOR 3 - LEVEL INVERTER

The Undeland snubber [35] is proposed to use due to its merits such

as less number of components, better efficiency and less voltage

unbalance. Fig.4.8. (a-b) shows an undeland snubber circuit for the 3-

level NPC inverter one leg top side and bottom side[35].

Fig 4.8.(a-b). snubber circuit.

86

The snubber circuit consists of components which includes turn off

capacitor “Cs” for dv/dt limitation, and turn on inductor “Ls” for di/dt

limitation. The capacitor “Co” for over voltage clamping and snubber

energy recovery normally about ten times larger than “Cs”, resister “Rs”

for resetting snubber inductor and capacitor and diodes. Such a simple

circuit Undeland snubber [35] has been used for 3-level inverter

circuits. Fig. 4.9 shows the 3- level inverter with complete snubber

circuit. Fig 4.10(a-b) shows the experimental setup photographs of the 3-

level NPC inverter and its control circuit.

Fig. 4.9. The 3- level inverter with complete snubber circuit

87

Fig. 4.10(a) Photograph of practical 3-level NPC Inverter Bridge

Fig. 4.10(b) Photograph of LISN & converter circuit and IM.

4.6. SIMULATION MODEL OF 3-PHASE 3-LEVEL NPC INVERTER

Simulation is carried out using MATLAB/ SIMULINK software. Fig.4.11

Shows SIMULINK model for 3-level inverter fed IM drive SIMULINK model

also includes CM equivalent circuit with bearing model for measurement

of shaft voltage and bearing current. Method used in modeling of high

frequency IM and CM equivalent circuit parameters is as in the reference

88

[30]. Simulation is done for the IM output voltages like phase voltage,

line voltage and the CM voltage. Here 450V DC link voltage is applied as

an input to 3-level NPC inverter circuit with suitable modulation index.

Three level diode clamped SPWM inverter Fed ASD

S ource Impedence

Cb Zb

Rb

Csr

CsfCg

Parasitic Capasitive model

Discrete,Ts = 5e-005 s.

powergui

v+

-

v+

-

A

B

C

B1

B2

Subsystem

Neutral Voltages

g DS

g DS

g DS

g DS

g DS

g DS

g DS

g DS

g DS

g DS

g DS

g DS

Va

Vb

Vc

Van

Vbn

Vcn

A

B

C

Measurement

Line voltage1

[L3c]

[L3a]

[L2d]

[L2b]

[L1d]

[L1b]

[L2c]

[L2a]

[L3d]

[L3b]

[L1c]

[L1a]

[L3b]

[L3a]

[L2d]

[L2c]

[L2b]

[L2a]

[L1d]

[L1c]

[L3d]

[L3c]

[L1b]

[L1a]

i+

-

Common mode voltage

C2

C1

Bearing voltage

Bearing current

Conn1

Conn2

Conn3

5 HP motor equivalent circuit1

L1a

L1c

L1b

L1d

L2a

L2c

L2b

L2d

L3a

L3c

L3b

L3d

180 degree pulses

Fig.4.11.Simulink model of 3-Level NPC inverter fed IM.

89

4.7. RESULTS

4.7.1. Simulation results of 3-phase 3-level NPC inverter

(a)

(b)

(c)

Fig.4.12.(a) Phase voltage (b) Line voltage (c)CM voltage

90

4.7.2. Experimental results of 3-phase 3-level NPC inverter

Fig.4.13.DSO recorded waveform. Ch.1.200: 1 Phase voltage. (2v/Div) Ch 2: 200 : 1 CM voltage (1v/DIV) Ch 4: 1 : 1 Bearing current using

the current probe

Fig.4.14.DSO recorded waveform. Ch.1.200 : 1 Phase voltage.(2v/Div) Ch.2.200 : 1 Line voltage.(2v/Div) Ch 3: 200 : 1 CM voltage

91

Table-4.3: Simulated Values

Parameters

Voltage(V)

Phase voltage Refer Fig 4.12(a)

320Vpeak

Line voltage Refer Fig 4.12(b)

550Vpeak

Common mode voltage Refer Fig 4.12(c)

155Vpeak

Table-4.4. Experimental Values

Parameters

Voltage(V)

Phase voltage Refer Fig.4.13

314Vpeak

Line voltage Refer Fig. 4.14.

543Vpeak

Common mode voltage Refer Fig. 4.14.

135Vpeak

The simulation is done on 3-phase 3-level NPC inverter connected to

3-phase IM load using the MATLAB/SIMULINK software and the motor

voltages like phase voltage, line voltage and the CM voltage are identified

and measured. The wave forms are as shown in Fig.4.12. The values of

the phase voltage, line voltage and the CM voltage of the simulated

results are shown in Table 4.3.

92

The 3-phase IM was connected as a load to the inverter with input DC

link voltage of 450V. The phase voltage, line voltage, sum of phase

currents, the bearing current in terms of voltage using current probe and

the CM voltage are recorded using 4 channel DSO which is as shown in

Figs 4.13 & 4.14.

Referring Figs 4.13 & 4.14, the values of the phase voltage, line voltage

and the CM voltage of the experimental results are shown in Table 4.4.

The signal analysis software is used to plot the FFT results of the

DSO recorded waveforms. Figs. 4.15 to 4.20, show the FFT results of

phase voltage, line voltage and the CM voltage applied to IM in terms of

volts and dBµV respectively. The significance of these plots is to study

and compare with 2-level inverter and the same results can also be used

for the comparison with higher level inverters. Figs. 4.15 & 4.16 show the

FFT of phase voltage in volts and in dBµV respectively. Figs. 4.17 & 4.18

show the FFT of line voltage in volts and in dBµV respectively. From

Fig.4.19 it is observed that the FFT of CM voltage is around 44 volt in 3-

level NPC inverter for the fundamental frequency and the other higher

order frequency components are very less. Fig.4.20 show the FFT of the

CM voltage in dBµV and it is observed that the CM voltage is around 180

dBµV. Similarly other high frequency FFT plots are given in Appendix-2

for reference.

93

0 500 1000 1500 2000 2500

0

50

100

150

200

Frequency (Hz)

Am

plit

ud

e in

volts

Fig.4.15. FFT of Phase voltage in volts

Explanation: Fig.4.15 shows the FFT of phase voltage. The voltage

magnitude is found to be 180Vpeak at zero frequency, however observing

the phase voltage DSO recorded waveform (Fig.4.14,ch.1) there exists the

steady state values (stair case) hence the phase voltage magnitude is

shown at zero frequency but it should be considered as fundamental. It

is seen from the above plot that at 40Hz the voltage magnitude is around

10Vpeak. In real sense the fundamental frequency voltage magnitude is

around 190Vpeak (180+10). The even harmonic components should not

be considered since while doing the FFT, the –ve values are changed as

+ve as per Origin signal analysis software and due to symmetry of

waveform the even harmonic voltages will get cancelled. The triplen

harmonic components will circulate, hence should not be considered.

94

The 5th and the 7th harmonic component are found to be 2V and 1V

respectively. All the other higher frequency magnitudes of voltages are

negligible.

0 500 1000 1500 2000 25000

100

200

300

Frequency (Hz)

Am

plit

ud

e in

dB

µ V

Fig.4.16. FFT of Phase voltage in dB µ V

Fig. 4.16 shows the FFT of phase voltage in dBµV. The voltage

magnitude is found to be 270 dB µV.

95

0 500 1000 1500 2000 2500 3000

0

100

200

300

400

Frequency (Hz)

Am

plit

ud

e in

vo

lts

Fig.4.17. FFT wave form of Line voltage in volts

Explanation: Fig.4.17 shows the FFT of line voltage waveform. The

voltage magnitude is found to be 330Vpeak at zero frequency, however

observing the line voltage DSO recorded waveform (Fig.4.14,ch.2) there

exists the steady state values (stair case) hence the line voltage

magnitude is shown at zero frequency but it should be considered as

fundamental. It is seen from the above plot that at 40Hz the voltage

magnitude is around 30Vpeak. In real sense the fundamental frequency

voltage magnitude is around 360Vpeak (330+30). The even harmonic

components should not be considered since while doing the FFT, the –ve

values are changed as +ve as per Origin signal analysis software and due

to symmetry of waveform the even harmonic voltages will get cancelled.

The 5th and the 7th harmonic component are found to be 4V and 2V

96

respectively. All the other higher frequency magnitudes of voltages are

negligible.

0 500 1000 1500 2000 25000

100

200

300

Frequency (Hz)

Am

plit

ud

e in

dB

µ V

Fig.4.18. FFT wave form of Line voltage in dB µ V

Fig 4.18 gives the FFT of line voltage in dB µV. The voltage magnitude is

found to be 280 dB µV.

-100 0 100 200 300 400 500 600 700 800 900 10000

10

20

30

40

50

Frequency (Hz)

Am

plit

ud

e in

vo

lts

Fig.4.19. FFT of CM voltage

97

Explanation: Fig.4.19 shows the FFT of CM voltage waveform. The

voltage magnitude is found to be 44Vpeak at zero frequency; however it is

seen from the above plot that at 40Hz the voltage magnitude is around

5Vpeak. In real sense the fundamental frequency voltage magnitude is

around 49Vpeak (44+5). The even harmonic components should not be

considered since while doing the FFT, the –ve values are changed as +ve

as per Origin signal analysis software and due to symmetry of waveform

the even harmonic voltages will get cancelled. The 5th, 7th and the 11th

voltage harmonic components are found to be 5V, 1V and 3V

respectively. All the other higher frequency magnitudes of voltages are

negligible.

0 500 1000 1500 2000 25000

50

100

150

200

Frequency (Hz)

Am

plit

ud

e in d

B µ

V

Fig.4.20. FFT of CM voltage in dB µV

Fig 4.20 shows the FFT of CM voltage in dBµV and its magnitude of

voltage is found to be 180 dB µV.

98

4.8. CONCLUSION

The basic structure of the 3-Level NPC inverter with snubber was

designed, fabricated and tested with 3-phase IM as load. The gating

signals for 40 Hz frequency were generated using the PIC µ-controller.

Though there are 27 voltage vectors in 3-level NPC space vector diagram

(Fig.4.3), only the twelve outermost voltage vectors in the space vector

diagram was considered (since the other voltage vectors are

redundancies in nature) for the generation of gating signals.

Simulation is also done for 3-phase, 3-level NPC inverter connected to IM

as load using MATLAB/SIMULINK software. Table 4.3 and Table 4.4

gives the simulated and experimental results of 3-phase, 3-level inverter

fed IM respectively. Comparing these two tables the experimental results

are in concurrence with simulated results with small deviations. The

small deviations are accepted since in simulation the ideal conditions are

considered.

Comparing the Tables 4.3 & 4.4 with Chapter-3, Tables 3.1 & 3.2 the

CM voltage in 3-level inverter is less compared to 2-level inverter.

Comparing the CM voltage in 2-level inverter (Chapter-3, Fig.3.19. the

FFT of CM voltage is found to be 68Vpeak), where as the FFT of CM voltage

is found to be less in 3-level NPC inverter and it is around 49Vpeak. (Fig.

4.19)

Hence it is concluded that CM voltage is less in 3-level inverter. From

the FFT graphs the voltage amplitude of various harmonic frequency

99

components of CM voltage can be measured and hence the voltage

%THDV has been computed and presented in Chapter-7.

Note: Justification for Fig.4.13 and 4.14

The experimental CM voltage also contains the fast switching noise

signals generated by fast switching action of the power MOSFET.

However the waveform of CM voltage is repetitive in nature (the CM

voltage frequency is three times that of inverter output frequency) and

hence this is the actual CM voltage wave form for 3-level inverter.

CM voltage waveform in Fig.4.13 (ch.2) and Fig.4.14 (ch.3) are identical

and similar.