Chapter 3   : Fabrication of CMOS Integrated Circuits

This section gives an overview of the integrated circuit technology. Semiconductor devices and circuits are formed in thin slices of a material (called a wafer) that servers as the substrate. For proper operation of the device/circuit, the substrate material must have crystalline structure where all the atoms are aligned in a specific pattern. In the first section of this chapter, the structure and growth of crystals are discussed. The next section deals with the cleaning of wafers which is an important step in the fabrication of integrated circuits. One of the basic building blocks in integrated circuit processing is the ability to deposit thin films of material. A large number of deposited films by wide variety of techniques are used in integrated circuits. These films can either be grown on semiconductor or deposited by various techniques. Most films can be formed by more than one method. Thermal Oxidation of Silicon is taken up first because it is an important step which is often repeated throughout the IC fabrication. This is followed by other principal film deposition techniques such as vacuum evaporation, sputtering and chemical vapor deposition. The properties of the films or substrate can be modified by process like diffusion and ion implantation and they enables to form a variety of devices in integrated circuits. A brief description of diffusion and implantation process and systems are given in section 4. In the subsequent section the lithography process is treated. The basic approaches to CMOS fabrication such as the p-well, the n-well, the twin tub and silicon on insulator processes are discussed in section 6. Very brief discussion on the fabrication of passive components also included. This chapter ends with a discussion on latch up and technology related CAD issues. In summary, an integrated circuit process is usually a structured sequence of operations such as the ability to deposit/modify thin films on the substrate, to apply a patterned mask on the films by photolithographic process, and to etch the films selectively to form actual devices.

3.1 Crystals and Growth

The basic semiconductor materials used in chips are crystalline silicon. This section briefly discuss about the properties of semiconductor crystals and how silicon crystals are grown.

3.1.1 Crystals

Solid materials are classified by the way the atoms are arranged within the solid. Materials in which atoms are placed at random are called amorphous. Materials in which atoms are placed in a high ordered structure are called crystalline. Poly-crystalline materials are materials with a high degree of short-range order and no long-range order. These materials consist of small crystalline regions with random orientation called grains, separated by grain boundaries. There three arrangements are summarized in Fig.3.1.  

Fig.3.1: Arrangements of atoms in solids

The crystal can be thought of as consisting of two separate parts: the lattice and the basis. The lattice is an ordered arrangement of points in space, while the basis consists of the simplest arrangement of atoms which is repeated at

every point in the lattice to build up the crystal structure. Fig.3.2 illustrates the basis and lattice in a crystal.

Fig.3.2 : Illustration of basis and lattice in a crystal

A crystal structure is composed of a unit cell, a set of atoms arranged in a particular way and is periodically repeated in three dimensions on a lattice. The unit cell is given by its lattice parameters, the length of the cell edges and the angles between them. In 1848, Auguste Bravais demonstrated that there are in fact only fourteen possible point lattices and no more. In a cubic system, the lattice parameter is the side length of a cube and angles between the edges are 90. The cubic lattices are an important subset of these fourteen Bravais lattices since a large number of semiconductors are cubic. The three cubic lattices are the simple cubic lattice, the body-centered cubic lattice and the face-centered cubic lattice as shown in Fig.3.3. The positions of the atoms inside the unit cell are described by the set of atomic positions (x, y, z) measured from a lattice point.

Fig.3.3 : Atomic arrangements in a basic cubic cell

In Simple Cubic (SC) structure, atoms lie on the corners of a cube as shown in Fig. 3.3a. Very few crystals exhibit this structure. For example polonium exhibits this structure over a narrow range of temperatures. In this structure each atom has six equidistant nearest neighbors.

In Body centered Cubic (BCC) structure, structure atoms lie on the corners of a cube with an additional atom at the centre of the cube as shown in Fig. 3.3b. Its atomic positions are (000), (100), (010), (001), (101), (110), (011), (111)

and ( , , ). Metals like Molybdenum, tantalum (Ta) and tungsten (T), iron (Fe), Platinum (Pt), Sodium (Na) and Potassium (K) have this structure. In this structure each atom has eight nearest neighbours. By placement of an atom at the center of the cube, the body-centered cubic structure has twice the atom density of the simple cubic lattice.

In Face centered Cubic (FCC) structure, atoms lie on the corners of a cube with additional atoms at the centers of each

cube face as shown in Fig. 3.3c. Its atomic positions are (000), (100), (010), (001), (101), (110), (011), (111), ( , ,

0), ( , 0, ), ( 0, , ), , , 0), ( , 1, , 0) and (1, , ). In this structure each atom has twelve equidistant nearest neighbours. Due to its low energy, FCC is extremely common and the examples are lead (Pb), aluminum (Al), copper (Cu), and gold (Au).

Metals which are BCC (like chromium) usually harder and less malleable than close-packed metals such as gold. When the metal is deformed, the planes of atoms must slip over each other, and this is more difficult in the BCC structure.

Fig.3.4 : Diamond Structure

The most common crystal structure among frequently used semiconductors such as silicon and germanium is the diamond lattice, shown in Fig.3.4. Each atom in the diamond lattice has a covalent bond with four adjacent atoms, which together form a tetrahedron as given in Fig.3.4b. The tetrahedral radius of the silicon atom is 1.18 Å. The misfit factor of an impurity atom shows whether it is smaller or larger than the silicon atom. The diamond lattice can also be formed from two face-centered-cubic lattices, which are displaced along the body diagonal of the cube by one quarter of that body diagonal as shown in Fig.3.4c. The violet color atoms are from the second FCC lattice.

Fig.3.5 : Zincblende (ZnS) Structure

Compound semiconductors such as GaAs and InP have a crystal structure that is similar to that of diamond. However, the lattice contains two different types of atoms. This structure is referred to as the zinc-blende lattice, named after zinc-

blende (ZnS) and is shown in Fig.3.5, where the two different colors are showing different elements.

Another important geometric feature of a crystal structure is the nearest distance between atom centers (often called the

nearest-neighbor distance). This distance is a for the SC lattice, (half of a body diagonal) in the BCC lattice, and

(half of a face diagonal) for the FCC lattice.

Example 1: Calculate the maximum fraction of the volume in a simple cubic crystal occupied by the atoms. Assume that the atoms are closely packed and that they can be treated as hard spheres. This fraction is also called the packing density.

The atoms in a simple cubic crystal are located at the corners of the units cell, a cube with side a. Adjacent atoms touch

each other so that the radius of each atom equals . There are eight atoms occupying the corners of the cube, but only one eighth of each is within the unit cell so that the number of atoms equals one per unit cell. The packing density is then obtained as follows:

Note that in the case of a SC, about half the volume of the unit cell is occupied by the atoms. The packing density of four cubic crystals is listed in the Table 1.

Table1 : The packing density of four cubic crystals

  Radius Atoms/unit cell Packaging density

Simple Cubic 1

Body centered Cubic 2

Face centered Cubic 4

Diamond 8

All lattice planes and lattice directions are described by a mathematical description known as a Miller Index. In the cubic lattice system, the direction [hkl] defines a vector direction normal to surface of a particular plane (hkl). Miller indices are referenced to the crystallographic axes of a crystal. Cubic lattices need only three axes and they correspond to the x, y,

z, axes in cubic lattice structures.

Fig.3.6 Intersections of a plane on the x , y and z axis

Intersections of a plane and the x , y and z axes, as shown in figure 3.6, are used to determine the Miller indices of the plane. The Miller Indices h, k, l are obtained as follows:

Determine the points at which a given crystal plane intersects the three axes, for example at (a, 0, 0), (0, b, 0), (0, 0, c). If the plane is parallel an axis, it is said to intersect the axis at infinity.

The Miller index for the face is then specified by (1/a, 1/b, 1/c), where the three numbers are expressed as the smallest integers (common factors are removed). Negative quantities are indicated with an over bar.

Example 2:

A plane intersects the crystallographic axes at (2, 0, 0), (0, 3, 0), (0, 0, 4).

Step 1: (1/2, 1/3, 1/4); multiply by 12 to express as smallest integers.

Step 2: (6, 4, 3) are the Miller indices. This is a (643) plane.

The (110) is the plane intersects the crystallographic axes at (1,0,0), (0,1,0) and (0, 0, ). z=infinity means that this plane does not intersect the z axis.

Use the [ ] notation to identify a specific direction (i.e. [101]).

Use the < > notation to identify a family of equivalent directions (i.e. <110>).

Use the ( ) notation to identify a specific plane (i.e. (113)). Use the { } notation to identify a family of equivalent planes (i.e. {311}).

A bar above a index is equivalent to a minus sign.

Fig.3.7: Different crystallographic planes in a cubic system

Fig.3.7 shows the different crystallographic planes in a cubic system. The separation between adjacent planes in a cubic crystal is given by

The separation between set of (111) planes is the smallest compared to {110} and {100}.

For cubic crystals, the angle, between two planes, ( h1 k1 l 1 ) and ( h2 k2 l 2 ) is given by:

Example 3: Calculate the angle between the (111) and (200) planes.

From the above equation,

which produces the result, = 54.75

In a similar way one can find the angle between any planes and the values of most common planes are summarized in the Table 2.

Table 2 : The angle between planes in cubic crystals

Planes 100 110 010 001 101100 0.00 45.0 90.0 90.0 45.0011 90.0 60.0 45.0 45.0 60.0 111 54.7 35.3 54.7 54.7 35.3

Linear density of atoms can be defined as number of atoms centered on a direction vector / length of direction vector. Similarly planar density of atoms is number of atoms centered on a plane / area of plane. Linear density and planar density are important considerations during deformation and "slip"; planes tend to slip or slide along planes with high planar density along directions with high linear density. Based on these values {111} planes have the following unique characteristics:

The crystal growth is easiest

The chemical etching is slowest

Tensile strength is highest

Modulus of elasticity is highest

It is the typical cleavage plane

Cross sectional view                                   Top View

Fig. 3.8 : V-groove etching in (100) silicon showing the exposed {111} sidewalls

An anisotropic wet etch on a silicon wafer creates a cavity with a trapezoidal cross-section as shown in Fig. 3.8. The bottom of the cavity is a <100> plane, and the sides are <111> planes. The white material is an etch mask, and the grey material is silicon. The angle between (111) planes and (100) surface is 54.7° as calculated before and the etching stops at (111) planes at this angle resulting a V-groove.

Example 4 : Calculate the density of Si from the lattice constant, atomic weight, and Avogadro's number. Recall: Avogadro's number (6.02 × 1023 ) is the number of molecules/atoms in a gram molecular weight of a substance. Lattice constant = a = 5.43 x 10-8 cm

How many Si atoms in the diamond cell?

8 corner atoms x (1/8) = 1

6 face atoms x (1/2) = 3

+ 4 interior atoms = 4

Total 8 atoms/unit cell

The number of atoms/cm3  = 8/a3

= 8 / (5.43 X 10-8 cm)3

= 4.996 x 1022 atoms/cm3

If 6.02 x 1023 silicon atoms make 28.1g; then 4.996 x 1022 atoms should weigh 2.332 g. Thus the density of silicon is 2.332 g/cm3.

Up to the 150 mm wafer diameter era, wafers had flats, and the flats indicate the following information:

1. The doping type of the wafer (n- or p-type) 2. The orientation of the wafer: {100} or {111}

And wafers with diameters larger than 200 mm generally will have no flat at all, but just a small "notch" as shown in Fig. 3.9.

Fig. 3.9 Identification of wafers

By measuring the sign of the thermo voltage between a hot tip (a soldering iron) and a room-temperature tip pressed on the wafer can indicate whether the wafer is n- or p-type.

The breaking (cleaving) of wafer indicate the orientation of a wafer; e.g. {100} wafer pieces will be rectangular.

In this section we have studied about different types of cubic crystal structures, packing densities, various crystal planes and directions, miller indices etc. In the next section we will study how the crystals are made.

3.1.2 Crystal Growth

Integrated circuits are built on single-crystal silicon substrates that possess a high degree of chemical purity, a high degree of crystalline perfection, and high structure uniformity. Such silicon crystal preparation involves two major steps: (1) refinement of raw material (such as quartzite, a type of sand) into electronic grade polycrystalline silicon (EGS) and (2) growing of single-crystal silicon from this EGS either by Czochralski or Float Zone process.

Fortunately, the raw Si is abundantly available from steel industry and only a small part of it only required for the semiconductor industry. Since it is a byproduct from steel industry, it is commonly called Metallurgical Grade Silicon (MGS). MGS is poly crystalline material with a purity of about 99%. It is made by the reduction of SiO2 (quartz sand) with carbon (coal) in huge furnaces lined with carbon, with big graphite electrodes inside (carrying huge amounts of current) at about 2000°C. The reaction is

C (s) + SiO2 (s) Si (l) + CO (g)

But care should be taken to suppress the other reaction occurring simultaneously (Si + C SiC), which will not only reduce the yield of Si, but clog up the furnace by SiC.

The 9N purity (99.9999999) silicon is made essentially in three steps:

Liquid Si reacts with all substances and is a universal solvent. This makes crystal growth from liquid Si somewhat difficult. Si is converted to SiHCl3 via the reaction at around 300°C

Si (s) + 3HCl (g) SiHCl3 (g) + H2 (g) + heat

The resulting Trichlorosilane is already much purer than the raw Si; it is a liquid with a boiling point of 31.8°C.

The SiHCl3 is further distilled, resulting in extremely pure Trichlorosilane.

Finally, high-purity Si is produced by a "Chemical Vapor Deposition" (CVD) process (discussed in later sections) .

Often very small but precisely measured amounts of As, P or B can also be incorporated into the growing polysilicon.

The next step is to convert this poly-Si to a single crystal. There are two methods for crystal growth used in this case; Czochralski or crucible grown crystals (CZ crystals) and Float zone (FZ) crystals. The FZ method produces crystals with the highest purity, but is not easily used at large diameters.

Czochralski or crucible (CZ) method of crystals growth :

The Czochralski method, invented by the Polish scientist J. Czochralski in 1916, is the method of choice for high volume production of Si single crystals. A schematic drawing of a crystal growth by Czochralski method is given in Fig.3.10.

Fig.3.10 Czochralski method of crystal growth

Essentially, a crystal is "pulled" out of a vessel containing liquid Si as shown in Fig 3.10. A seed crystal is dipped into the liquid and is subsequently slowly withdrawn from the melt. The pulling rate (usually a few mm/min) and the temperature profile determines the crystal diameter that can achieved. The solubility of impurity atoms in the melt is larger than in the solid. As a result, the crystal will be cleaner than the liquid and crystal growing is simultaneously a purification method. However the distribution of impurities vary along the length of a crystal and a homogeneous doping is difficult to achieve.

Practically only As, P, and B is used for doping because of their segregation coefficient is close to 1. The segregation coefficient in thermodynamic equilibrium gives the relation between the concentration of impurity atoms in the growing crystal and that of the melt. It is usually much lower than 1 because impurity atoms prefer to stay in the melt.

Oxygen is the most important impurity found in silicon and is from the quartz crucible in which the molten silicon is contained. The oxygen is typically at a level of about 5x1017/cm3 1018/cm3 in CZ silicon. Oxygen has three principal effects in the silicon crystal. In an as-grown crystal, the oxygen generally occupies interstitial positions in the silicon lattice and improves the yield strength by 25%. A small amount of the oxygen in the crystal forms SiO4 complexes and act as donors. Even 1016 /cm3 donors can be formed, which is significant to increase the resistivity of lightly doped P-type wafers. During the CZ growth process, the crystal cools slowly through ~500°C temperature and oxygen donors form.

Typically annealing of the grown crystal is carried at temperatures above 500°C and to remove these oxygen complexes. The oxygen can precipitate under normal device processing conditions, forming SiO2 regions inside the wafer. The precipitation arises because the oxygen was incorporated at the melt temperature.

Carbon is another impurity normally present in CZ grown silicon crystals. The carbon comes from the graphite components in the crystal pulling machine. For some applications, it is important to have even lower concentrations of impurity atoms like Oxygen and the Float Zone Crystal Growth is used.

Float Zone Crystal Growth

The basic idea in float zone (FZ) crystal growth is to move a liquid zone through the material as shown in Fig.3.11. In this process the end of a long polysilicon rod is locally melted and brought in contact with a single crystalline Silicon seed. The melted zone slowly migrates through the poly rod leaving behind the final perfect crystal. In the float zone process, dopants and other impurities are rejected by the growing silicon crystal. Impurities tend to stay in the liquid and refining can be accomplished, especially with multiple passes. Since the melt never comes into contact with anything but vacuum (or inert gases), there is no incorporation of impurities by dissolving the crucible material as in the CZ crystal growth method. FZ crystals therefore are always used when very low oxygen concentrations are required. One needs to keep the liquid Si from just collapsing by surface tension and this limit the maximum diameter of crystals. A summary of the CZ and FZ growth methods are given in Table 3.

Fig.3.11: Float Zone (FZ) method of crystal growth

Table 3 : Comparison of the CZ and FZ Growth Methods

Characteristic CZ FZ Growth Speed (mm/min) 1 to 2 3 to 5

Crucible Yes No Consumable Material Cost High Low Heat-Up/Cool-Down Times Long Short Axial Resistivity Uniformity Poor Good

Oxygen Content (atoms/cm3 ) >1x10 18 <1x10 16 Carbon Content (atoms/cm3 ) >1x10 17 <1x10 16

Metallic Impurity Content Higher Lower

Bulk Minority Charge Carrier Lifetime (s-1 ) 5-100 1,000-20,000

Production Diameter (mm) 150-200 100-150

Conversion of silicon ingots into polished wafer is carried out by shaping, slicing, lapping and edge grind, etching, polishing and cleaning operations. For many applications, the quality of a polished wafer is not sufficient mainly due to defects generated during crystal growth in the bulk of the wafer. The best solution to this problem is to deposit an additional layer of high purity Silicon on the top of a polished wafer substrate. This process is known as epitaxy. This has the additional advantage in that the electrical resistivity of the surface layer can be different than that of the substrate.

Silicon Epitaxial Growth Process

Silicon epitaxial deposition (epitaxy) refers to the process of growing a thin layer of single-crystal silicon over a single-crystal silicon substrate. Epitaxy is different from the Czochralski process in that the crystal can be grown below the melting point. In semiconductors, the deposited film is often the same material as the substrate, and the process is known as homo-epitaxy. An example of this is silicon deposition over a silicon substrate. If the layer and substrate are of different materials such as AlxGa1-x As on GaAs, the process is termed as hetero-epitaxy. Epitaxy can be achieved by molecular beam epitaxy (MBE) method where the physical transport of material is carried out to a heated substrate. In chemical vapor deposition (CVD), materials such as Si, Ga, As, dopants etc. are transported in the form of volatile compounds to the substrate, where they react to form the epitaxial layer.

There are four major chemical sources of silicon for commercial epitaxial deposition: (1) silicon tetrachloride (SiCl4), (2) trichlorosilane (SiHCl3), (3) dichlorosilane (SiH2 Cl2) and (4) silane (SiH4). The over-all reaction for silicon epitaxy by silane reaction may be written as follows:

The growth of an epitaxial layer over the substrate offers some advantages. By growing a lightly doped epi layer over a heavily-doped silicon substrate, a higher breakdown voltage across the collector-substrate junction is achieved while maintaining low collector resistance. Lower collector resistance allows a higher operating speed. By fabricating the CMOS device on a very thin (3-7 µm) lightly doped epi layer grown over a heavily-doped substrate, latch-up occurrence is minimized. Aside from improving the performance of devices, epitaxy also allows better control of doping concentrations of the devices. The layer can also be made oxygen- and carbon-free. The disadvantages of epitaxy include higher cost of wafer fabrication, additional process complexities, and problems associated with defects in the epi layer.

In this section we have studied about the crystal structure, how it was grown and converted to wafers. The next section discusses the importance of wafer cleaning and different methods used to remove contaminations.

3.2 Cleaning and Etching of wafers

Surface of semiconductor wafer gets contaminated during device processing. The source of contaminants are ambient air, storage ambient, process gases, chemicals, materials, water etc which are used in the fabrication processes. Processing tools as well as personnel operating in the clean- rooms are also sources of contamination. The most prevalent contaminants are particles and they may cause a catastrophic failure during device manufacturing process. The measure of the air quality of a clean room is described in Federal Standard 209. Clean rooms are rated as Class 10K, where there exist no more than 10,000 particles larger than 0.5 microns in any given cubic foot of air; Class 1K, where there exists no more than 1000 particles; and Class 100, where there exist no more than 100 particles. These small particles are controlled in a clean-room by using High Efficiency Particulate Air (HEPA) filters.

Another type of contaminants which degrade the devices are metallic contaminants originate primarily from liquid chemicals, water and process tools. The most common metallic contaminants are iron (Fe), aluminum (Al), copper (Cu), nickel (Ni) as well as ionic metals such as sodium (Na) and calcium (Ca). Organic contaminants are present in ambient

air, storage containers and can arise from photoresists. Organic compounds readily adsorb surfaces adversely affect device properties. Native oxides as well as moisture from the ambient air or wet processes adversely affect the devices and can be considered as a contaminant and its removal is a part of cleaning process.

As total elimination of contaminants is not possible, methods of semiconductor surface cleaning are employed throughout the device manufacturing sequence. The cleaning can be achieved by a chemical reaction with a reactant and contaminant on the surface, by the physical interaction between cleaning ambient and the surface, the momentum transfer between high kinetic energy particles directed toward the contaminant etc. In Wet Cleaning, contaminant is removed via selective chemical reaction in the liquid-phase by its dissolution in the solvent, or its conversion into the soluble compound. Typically, process is enhanced ultrasonic agitation. In Dry Cleaning, contaminant is removed via chemical reaction in the gas phase converting it into a volatile compound. Wet cleaning is the dominant cleaning technology in semiconductor device manufacturing. Wet cleans use combinations of acids and solvents, oxidize, etch, and scrub contaminants from the wafer surface. An integral part of every wet cleaning scheme is rinses in ultra-pure deionized (DI) water which stops chemical reaction on the wafer surface and washes off reactants and reaction products. Wet cleaning is always completed with a wafer drying process.

RCA clean Wet cleaning recipes were first proposed over 30 years ago presents a complete cleaning process to remove from the surface heavy organics, particles, and metallic contaminants as well as native/chemical oxide. Typically the first step is to remove organic contamination remaining on the surface. The H2SO4 :H2O2 solution at 100°C-130°C, also known as SPM (Sulfuric Peroxide Mixture), or "piranha" clean. NH4OH : H2O2 : H2O mixture 1:1:50, at temperature ~ 70°C with ultrasonic agitation is used to remove particles.

This Ammonium hydroxide-hydrogen Peroxide Mixture (APM) is also known as Standard Clean 1 (SC1 or RCA 1). To remove metallic contamination, HCl: H2O2 : H2O mixture is used. This Hydrochloric acid - hydrogen Peroxide-water Mixture (HPM) is also known as Standard Clean 2 (SC2 or RCA 2). Dilution and bath temperature are similar to APM. Native/chemical oxide etch is carried out in diluted HF:H2O solution at the ratio of 1:100 or weaker. Thin films are very fragile and material loss also can result by such very resourceful and time consuming cleaning processes. In practice it is simplified by less aggressive cleans. In many applications a sequence involving just one cleaning step followed with D.I. water rinse and dry is enough.

In a dry cleaning technology, removal of contaminant fro m the surface takes place via chemical reaction in the gas- phase converting it into a volatile compound. Gas sources like O2, H2, CO2, Ozone, SiCl4, HCl, are used for dry cleaning. Methods like Laser, Sputtering etc are based momentum transfer between specie impinging on the surface. Gas-phase cleaning methods lack a shear chemical and physical strength of liquid cleaning ambient. However gas-phase surface processing methods are fully capable of controlling organic contamination.

Etching

Etch is a process that removes unwanted materials from the surface of a substrate by various dry and wet techniques. These techniques are used to remove silicon dioxide, silicon nitride, polysilicon, aluminum, tungsten, contamination particles, and other layer materials. This process step creates the layer definition that is based on the outcome of a previous photolithography process step. These etch processes transform a single layer of semiconductor material into the patterns, features, lines, and interconnects.

Fig. 3.12 :Etching profiles before and after the pro

A typical etching profile is given in Fig. 3.12. In this case the red region is the mask (protective layer) used, blue layer is to be removed selectively from regions not protected by mask and grey layer is the substrate which should not be etched. The profile after the etching indicates that there is a horizontal etching as well etching of underlying substrate. Selectivity is the characteristic of etch whereby the desired layer is etched without damaging the underlying or masking layers. The etching system's ability to do this depends on the ratio of etch rates in the two materials. The selectivity can be quantified as:

Anisotropy is the characteristic of etch whereby the desired layer is etched in one direction only. The degree of anisotropy can be quantified as:

In the above figure dimension 'x' shows the degree of anisotropy, 'y' shows the lack of selectivity with respect to the underlying layer and 'z' shows the lack of selectivity with respect to the masking layer.

A poorly selective etch removes the desired layer, but also attacks the underlying material. A highly selective etch leaves the underlying material unharmed. A perfectly isotropic etch produces round sidewalls. A perfectly anisotropic etch produces vertical sidewalls

The wet etching processes used liquid-phase ("wet") etchants. The wafer is immersed in a bath of etchant, which must be agitated to achieve good process control. For instance, buffered hydrofluoric acid (HF) was used commonly to etch silicon dioxide over a silicon substrate. Wet etchants are usually isotropic, which leads to undercuts when etching thick films. They also require the disposal of large amounts of toxic waste. For these reasons, they are seldom used in state-of-the-art processes.

Modern VLSI processes avoid wet etching, and use plasma etching instead. The plasma produces energetic radicals, neutrally charged, that react at the surface of the wafer. Since neutral particles attack the wafer from all angles, this process is isotropic. The source gas for the plasma usually contains small molecules rich in chlorine or fluorine. For instance, carbon tetrachloride (CCl4) etches silicon and aluminium, and trifluoromethane etches silicon dioxide and silicon nitride. A plasma containing oxygen is used to oxidize ("ash") photoresist and facilitate its removal.

In Ion milling, or sputter etching, lower pressures, energetic ions of noble gases, often Ar+, bombards the wafer with which knock atoms from the substrate by transferring momentum. Because the etching is performed by ions, which approach the wafer approximately from one direction, this process is highly anisotropic. On the other hand, it tends to display poor selectivity. Reactive-ion etching (RIE) operates under conditions intermediate between sputter and plasma. Deep reactive-ion etching (DRIE) modifies the RIE technique to produce deep, narrow features.

The fabrication of an integrated circuit involves a sequence of processes that may be repeated many times before a circuit is complete. In this section, we have discussed about the first step involved in semiconductor device fabrication i.e. the cleaning of wafers. Briefly we also have studied about the etching of thin films. Generally, the next step involved is oxidation of the wafer surface and is discussed in the next section.

3.3 Thermal Oxidation of Silicon

The oxide of silicon, or silicon dioxide (SiO2), is one of the most important ingredients in integrated circuits. Thermal SiO2

is amorphous. It has a density of 2.2 gm/cm3 and molecular Density of 2.3x1022 molecules/cm3 . The crystalline SiO2 is also possible and known as Quartz has a density of 2.65 gm/cm3. SiO2 has excellent properties which makes them necessary in every part of the integrated circuits. It is an excellent electrical insulator having energy gap ~ 9 eV with a resistivity greater than 10 20 ohm-cm and breakdown electric field greater than 10MV/cm. Si technology became popular because of the stable and reproducible Si/SiO2 interface. Conformal oxide growth on exposed Si surface is easily possible. SiO2 is a good diffusion mask for common dopants such as. B, P, As, Sb. In addition there exists good etching selectivity between Si and SiO2.

The formation of SiO2 on a silicon surface is most often accomplished through a process called thermal oxidation. As its name implies, is a technique that uses extremely high temperatures (usually between 700-1200°C) to promote the growth rate of oxide layers whose thicknesses range from 20 to 10000 angstroms. During the process, silicon substrate is exposed to a high purity oxidizing species like oxygen gas (dry oxidation) or water vapour (wet oxidation).

The chemical reaction at the silicon surface for dry and wet oxidation is given as

Oxidation of silicon is not difficult, since silicon has a natural inclination to form a stable oxide even at room temperature, as long as an oxidizing ambient is present. In both cases the oxidizing species diffuses through the growing oxide and reacts with the silicon surface. These oxidation reactions occur at the Si-SiO2 interface, i.e., silicon at the interface is consumed as oxidation takes place. As the oxide grows the Si-SiO2 interface moves into the silicon substrate. As a result, the Si-SiO2 interface will always be below the original Si wafer surface. The SiO2 surface, on the other hand, is always above the original Si surface. SiO2 formation therefore proceeds in two directions relative to the original wafer

surface as shown in Fig.3.12.

Fig. 3.13 : The silicon-silicon dioxide interface in thermal oxides

The amount of silicon consumed by the formation of silicon dioxide is also fairly predictable from the relative densities and molecular weights of Si and SiO2, i.e., the thickness of silicon consumed is 44% of the final thickness of the oxide formed. Thus, an oxide that is 1000 angstroms thick will consume about 440 angstroms of silicon from the substrate. In another words, 1µm thick Si oxidizes to 2.17 µm thick SiO2.

Thermal oxidation is accomplished using an oxidation furnace which provides the heat needed to elevate the oxidizing ambient temperature. A furnace typically consists of a temperature controlled heating system, fused quartz process tubes, arrange for controlled flow of various gases. The heating system usually consists of several heating coils that control the temperature around the furnace tubes. The wafers are placed in quartz glassware known as boats. A boat can contain many wafers. The oxidizing agent (oxygen or steam) then enters the process tube through its source end, subsequently diffusing to the wafers where the oxidation occurs.

During dry oxidation, the silicon wafer reacts with the ambient oxygen, forming a layer of silicon dioxide on its surface. In wet oxidation, the water is heated in the 40-80°C range and oxygen or nitrogen carrier gases are used for the flow of water vapors to the chamber. Alternatively hydrogen and oxygen gases are introduced into a torch chamber where they react to form water molecules, which are then made to enter the reactor where they diffuse toward the wafers. The water molecules react with the silicon to produce the oxide and another byproduct, i.e., hydrogen gas.

Kinetics of SiO2 Growth

The Linear and Parabolic growth laws were developed by Deal and Grove, and are known as the Linear Parabolic Model. This oxide growth model has been empirically proven to be accurate over a wide range of temperatures (700-1300°C), oxide thicknesses (300-20,000 angstroms), and oxidant partial pressures (0.2-25 atmospheres).

Fig.3.14 and 3.15 pictures various diffusions possible and the concentration of species during thermal oxidation and is the basis for Deal and Grove model.

Fig. 3.14 : A Model for thermal oxidation of silicon indicating various diffusions possible

Fig. 3.15 : A Model for thermal oxidation of silicon indicating the concentration of species

The gas-phase flux F1 is proportional to the difference between the oxidant concentration in the bulk of the gas (CG) and the oxidant concentration adjacent to the oxide surface (CS).

The Fick's law of solid sate diffusion states that

hG is the mass transfer constant (cm/s),D is the diffusion coefficient (cm2/s),kS is the surface reaction transfer constant

(cm/s), Using and PV = NkT, Henry's law to relate C0 and CS

Where H is the Henry's constant and PS is the partial pressure of oxidant gases at surface

If the equilibrium concentration of oxidizing species in oxide is

Taking as h, at steady state

Solving these two equations for two unknowns

To convert F into oxide thickness growth rate

Where N1 is the oxidant molecules per unit volume required to form a unit volume of SiO2. N1 is 2.3 x 1022 cm-3 for dry oxidation and 4.6 x1022 cm-3 for wet oxidation. Taking boundary conditions as x = x0 at t=0. The oxide thickness grown at

any point of time t is modeled as where A and B constants.

The time displacement is included to account for the oxide layer (at t = 0) formed by the accelerated growth in the initial phase of oxidation.

 

Fig.3.16 : oxide thickness verses time

Typical oxide thickness verses time dependency is shown in Fig.3.16. For small values of t , the oxide growth equation

can be approximated as and thus is known as linear rate constant. For large values of t, the above equation

can be approximated as and thus B is known as parabolic rate constant. That is oxide thickness growth slows down with increase in oxide thickness and can be readily seen from:

Fig.3.17 Wet and Dry oxide growth rate for Silicon

Dry oxidation of silicon is typically used to grow a thin, high quality oxide that is used in transistor gates and capacitors. Oxide grown in dry oxygen ambient has excellent insulating properties and is denser, free of defects. Wet oxidation of silicon is typically used to grow thick oxides that are used as diffusion barriers. Silicon dioxide acts as an effective mask against many impurities, allowing dopants into silicon only in regions that are not covered with oxide.

The oxide thickness grown on silicon is dependent on the oxidation time and temperature. Wet oxidation method offers faster growth rate compared to dry oxidation. The linear and parabolic rate constants have larger values in wet oxidation

case than in case of dry oxidation. This is because equilibrium concentration of oxidizing species in oxide ( ) is approximately three orders of magnitude greater for water than in dry oxygen. Therefore, for growing thick oxide within a realistic time, wet oxidation is a better choice.

The linear and parabolic rate constants increase with temperature in both dry and wet oxidation methods. B increases in

both cases through the diffusion coefficient (D) increase due to temperature. The reason for increase in is through ks.

It can be seen that for small duration, the oxidation is a reaction controlled process and longer duration it is a diffusion controlled process.

From the Deal and grove model, we have seen that the oxide growth rate is affected by time, temperature, and pressure. Thickness of oxide is raised by an increase in oxidation time, oxidation temperature, or oxidation pressure. Other factors that affect thermal oxidation growth rate for SiO2 include: the crystallographic orientation of the wafer; the wafer's doping level; the presence of halogen impurities in the gas phase and the presence of plasma during growth.

Example 5 : A <100> silicon wafer has 400nm of oxide on its surface. In a subsequent process, a portion of the oxide was etched and the resulting cross section is shown below. How long will it take to grow an additional 1um of oxide over the 400 nm existing layer in wet oxygen at 1100°C? The parabolic and linear rate constants at this temperature are 0.5289 µm2/hr and 2.8952 µm/hr respectively. Plot the resulting cross section after the wet oxidation indicating the oxide-silicon interface.

Given that and So A = 0.1827

From the equation

For an initial oxide thickness of 0.4 µm, the corresponding = 0.4407 hr

Now for an oxide thickness of 1.4 µm, the corresponding = 4.1893 hr

That is the time taken to grow an additional 1um of oxide over the 400 nm existing layer = 3.1893 hr

To calculate the oxide thickness in the region 2

= 1.3197 µm

The resulting cross section after the wet oxidation is shown in Fig. 3.18 clearly indicating the oxide-silicon interfaces.

Fig. 3.18 : The Si-SiO2 interface changes before and after thermal oxide growth

ANODIC OXIDATION

The anodic oxidation processes is usually carried out at room temperature. Thus, impurity concentrations present in the semiconductor are not altered during this process. As a result, anodic oxidation is a useful means for the controlled removal of layers of silicon and gallium arsenide at room temperature, and is often used as a diagnostic tool. This technique can also be used to grow reasonably high quality oxides on gallium arsenide.

Anodic oxidation or anodization, is carried out by placing the semiconductor in an electrolytic cell, as shown in Fig.3.18, where it is connected to the positive terminal of a power supply so that it serves as the anode. A noble metal such as platinum is connected to the negative terminal of the supply, and serves as a cathode. A large variety of electrolytic formulations can be used. The primary oxidizing component of all of these is water, which dissociates into H + and (OH) -

.

Fig. 3.19 : Schematic diagram of Anodic oxidation set up

Often a conductivity/pH modifier is added to this system to vary the resistance of the electrolyte as well as the dissolution rate of oxide in it. It is also possible to carry out an anodisation process in a nonaqueous solution. However, the requirement of this electrolyte is that one of its dissociation products be the (OH) - ion. Reactions leading to anodic oxidation of silicon are as follows:

Water in the electrolyte medium dissociates into H + and (OH) - :

The difference in electrochemical potentials between silicon and the electrolyte results in charge transfer from silicon until equilibrium is established. This leaves the surface layer partially depleted of electrons. During anodisation, holes are supplied from the bulk of semiconductor to the semiconductor-electrolyte interface, thus promoting the silicon surface atoms to a higher oxidation state :

 

The Si2+ combines with (OH)- to form the hydroxide.

Si(OH)2 subsequently forms SiO2 liberating hydrogen in the process,

The overall reaction is given by

In the absence of an external battery (or illumination), the continuous supply of holes to the reaction interface ceases. The concentration of the thermally generated holes is insufficient for the formation of SiO2 beyond a few monolayers. However, the battery provides the necessary holes for this anode reaction that sustains the process of oxide growth. The H+ drifts to the cathode, where it is evolved as molecular hydrogen by the addition of electrons

The anodic oxidation of p-type material is relatively straightforward since there is no problem with delivering holes to the semiconductor surface by means of a battery. The situation is somewhat complex for n-type semiconductor. Here the initial charge transfer from the semiconductor into the electrolyte creates a depletion layer in semiconductor, and a barrier to the flow of holes. In effect, then, the electrolytic-semiconductor system behaves much like a Schottky diode with the electrolyte serving the role of the metal. In order to sustain the process of oxide growth, provision is to be made to supply holes to the semiconductor surface. One approach is to illuminate the sample to provide these holes by photo-generation. Alternately, the anodisation cell can be operated at a voltage, which exceeds the Schottky diode breakdown voltage, so that avalanche generated holes can allow the oxidation to proceed.

Anodisation can be carried out using either a constant voltage source or a constant current source. In the case of constant voltage source anodisation, the oxide thickness builds up towards a final value. The final thickness is proportional to the applied voltage and typically the value is about 0.3 nm/V for silicon. When the anodisation is carried out from a constant current source, the oxide thickness varies linearly with time. In this case, the electric field across the oxide is constant and the voltage drop across it increases with time. The linear increase of voltage can be monitored and the process can be stopped when the desired oxide thickness is reached.

Oxides formed by anodisation are generally porous in character, and have water incorporated in them. During the anodic oxidation process, semiconductor material is transferred through the oxide to the electrolyte-oxide interface. Thus, anodised oxide has an interface charge density about one order of magnitude larger than that of the conventional thermal oxide. From the above discussions on thermal oxidation and anodic oxidation of silicon, it is clear that thermal oxidation results in better quality SiO2 as well as a better Si-SiO2 interface compared to anodic oxidation.

In this section we have studied thermal oxidation of silicon and basic model which describes the oxidation process of silicon. Briefly we have discussed about the anodic oxidation process also. In the next section we will take up the methods by which films of various materials are deposited on silicon.

3.4 Thin Film Deposition

Thin films play a vital role in virtually every micro- and nanostructure. The thin films consists of wide range of materials systems such as conductors, insulators and semiconductors. Conductors such as metals and metal compounds are used for connecting transistors, for contacts and for device structures. It can be found that interconnection is much harder than making transistors. Insulators are required for electrical isolation, as dielectrics for MOS structures and for mask applications etc. Semiconductors are essential to make transistors, diodes, resistors, capacitors and are used in amorphous and polycrystalline forms for variety of applications such as solar cells, epitaxial layers and electrical contacts etc.

Thin films made by a variety of means. Deposition technology can be classified in two groups i.e. depositions that happen because of a chemical reaction and that happen because of a physical reaction. Chemical Vapor Deposition, Electrodeposition, Epitaxy, and Thermal oxidation exploit the creation of solid materials directly from chemical reactions in gas and/or liquid compositions with the substrate material. In physical deposition technologies material is released

from a source and transferred to the substrate. The most common examples are evaporation and sputtering.

Atomic separation in a solid is about 0.3nm. The thin film thickness can range from nanometers (monolayers) to microns. Monolayers has high surface to volume ratio. Thin film properties are different from the bulk; however when hundreds of atomic layers forms micron layers, their properties are similar to that of “bulk”. Typically there is a critical thickness above which it behaves essentially as a bulk material. Variety of forms of thin films are possible based on their crystal structure, grain size, composition, defects, electro- chemical-mechanical-optical properties, adhesion, stress resulted etc.

Gas Kinetics and Vacuum Technology

In order to understand deposition techniques, we must first know some basics of gas kinetics and vacuum physics. The vacuum ranges can be broadly defined as follows:

Rough Vacuum ~ 0.1 - 760 torr (atmospheric pressure is 760 torr)

Medium Vacuum ~ 0.1 to 10-4 torr

High Vacuum ~ 10-8 to 10-4 torr Ultrahigh Vacuum < 10-8 torr

Table 4 : Pressure conversion table

mbar Pascals (N/m2 ) atmospheres Torr (mm Hg) psi (lb/in2 ) dyne/cm2 molecules/m3 1mbar = 1 100 9.87x10-4 0.75 0.0145 1000 2.65x1022 1Pa = 0.01 1 9.87x10-6 7.5x10-3 1.45x10-4 10 2.65x1020 1atm = 1010 10,100 1 760 14.69 1.01x106 2.69x1025 1Torr = 1.333 133.3 1.31x10-3 1 0.0193 1333 2.69x1025 1psi = 68.94 6.89x103 0.068 51.71 1 6.89x104 1.83x1024

1dyne/cm2 = 0.001 0.10 9.87x10-7 7.50x10 -4 1.45x10-5 1 2.65x1019 1molecule/m3 = 3.77x10-23 3.77x10-21 3.72x10-26 2.83x10-23 5.47x10-25 3.77x10-20 1

Fig. 3.20(a) : Cross sectional diagrams of gas molecules enclosed in a cube and their kinetics (b) the volume swept by one molecule between the collisions

To understand the kinetics of gas, let us consider a volume V of nitrogen gas in a cube of side L as shown in Fig. 3.19. Gasses are composed of a very large number of very small particles. They are very small compared to the distance between particles. Particles are always moving rapidly in a straight line. Particles exert no forces except during collisions.

The distributions of their velocities obey Maxwell's distribution. Their r.m.s. velocity vr.m.s is given by where k = Boltzmann's constant, T = temperature of the gas (K) and m = mass of the molecule. For example hydrogen molecule at room temperature has vr.m.s of 1700m/sec.

The volume swept by one molecule between collisions can be expressed as . How far does a molecule travel between collisions?

Actually, we need to consider that all the molecules are moving. Clearly, what really counts in the collision rate is the relative velocity of the molecules.  Defining the average velocity as the root mean square velocity, if one molecule has

velocity v1 and another has v2, then the square of the relative velocity , since  must average to zero, the relative directions being random.  So the average square of the relative velocity is twice the average square of the velocity, and therefore the average root-mean-square velocity is up by a factor v2, and the

collision rate is increased by this factor.  Consequently, the mean free path is decreased by a factor of .

= mean free path

d = diameter of a molecule

n = number per unit volume

For air at room temperature, the mean free path can be expressed as:

P, the pressure is in torr and will be in cm. Table 5 shows the mean free paths for various pressures.

Table 5 : Mean free paths at various Pressures

Pressure Mean Free Path 1 atm 6.7 x 10-6 cm 1 torr 5 x 10-3 cm

1 millitorr 5 cm 10-6 torr 50 m 10-9 torr 50 km

There are mainly two regimes gas flows, viscous and molecular flow regimes. In the case of viscous flow regime, the mean free paths of particles are much less than the size of the system (D). In this regime, gas density (pressure) is high enough gas-gas collisions dominate and molecules "drag" one another along in the flow. Collisions with walls will play a secondary role only in limiting the gas flow. This regime typically occurs when D (cm) P (Torr) > 0.5 for air at room temperature.

In the case of molecular flow gas density (pressure) is very low and typically occurs when D (cm) P (Torr) > 0.005 for air at room temperature. The mean free paths of particles are much larger than the size of the system (D). Only few molecule-molecule collisions occur and molecule-chamber wall collisions dominate the flow process. The molecules move independently of one another and are held back by walls.

In between these two regimes when the mean free paths are comparable to size of system (D), a complicated intermediate (transition) flow occurs. Sometimes the Knudsen number (Kn) is used to distinguish between regimes. Kn (dimensionless number) is ratio of the mean free path to the characteristic dimension of the chamber (can be diameter of a pipe, or vacuum chamber). When Kn> 1 then it is the molecular flow regime. When Kn< 0.01 it is the viscous flow regime. In between, the flow characteristics are indeterminate.

The number of gas molecules colliding with a surface each second is given by = 0.25 n vrms , where is the collision rate of gas molecules, n is the number of molecules per unit volume and vrms is the average velocity of a gas molecule. Expressing this equation in terms of things one can directly measure:

Where is in molecules/cm2 –sec, P is the pressure in torr, M is the molecular weight of the gas molecule and T is the temperature in K. As an example, Nitrogen (N2) has a molecular weight M = 28. In a chamber with nitrogen at room

temperature (293 K) and a pressure of 1 x 10-7 torr, = 3.88 x 1013 molecules/cm2-sec.

The time taken to form a single complete layer of gas on a surface is given by

where tm is the time to form a monolayer (in seconds), n = number of molecules per unit volume, vrms is the average velocity of the molecules and d is the diameter of a molecule. In case of air at room temperature, the expression becomes: t m = 1.86 x 10-6/P, when P is the pressure expressed in torr.

Thin film depositions are carried out in high vacuum environment for achieving quality films. Vacuum pumps are used to create vacuum in a sealed chamber where the film deposition takes place. A partial vacuum, or rough vacuum, can be created using a rotary pump. The vacuum pumps could be classified into two based on how the molecules are removed from the chamber. In case of mechanical, turbo molecular and oil diffusion pumps, the molecules are physically removed from the chamber. However in case of cryo pumps and sputter/ion pump with Ti sublimation, the molecules are adsorbed on a surface or buried in a layer. The mechanical pumps have moving parts and oil. They are used to pump down from 1 atm pressure to roughing (medium) vacuum. Examples are Piston pumps (not used much due to particle problems), Rotary vane pumps (majority of cheap applications) and Dry pumps. Turbo molecular pumps pump down from 1 atm and are clean pumps. They also have moving parts and pump speeds are low. Oil diffusion pumps have no moving parts but based on oil in vacuum. Sputter/ion as well as cryo pumps are clean with no moving parts and are used to pump down from 10-4 torr.

The deposition chambers for standard vacuum requirements 10-5-10-6 Torr use glass or stainless steel chambers. They are usually diffusion pumped. The CVD , thermal evaporation, sputter deposition films have typically polycrystalline quality. For ultrahigh vacuum (10-8-10-11 Torr) chamber requirements bakeable stainless steel is used. They are usually ion and/or turbo pumped. The thermal evaporated and sputter deposited films have epitaxial (better) quality films.

Physical Vapor Deposition

As discussed previously, Physical vapor deposition ( PVD ) is a technique used to deposit thin films of various materials onto of semiconductor wafers by physical means, as compared to chemical vapor deposition. Evaporation, Sputter Deposition and Pulsed laser deposition are examples of this method.

An evaporator uses a thermal or e-beam heating to melt the material and raise its vapor pressure to a useful range as shown in Fig. 3.21. This is done in a high vacuum, both to allow the vapor to reach the substrate without reacting with or scattering against other gas-phase atoms in the chamber. Only materials with a much higher vapor pressure than the heating element can be deposited without contamination of the film.

Fig. 3.21 : Different methods used for melting the source in an evaporation system

Sputtering relies on a plasma (usually a noble gas, such as Argon) to knock material from a "target" a few atoms at a time. Since the process is not one of evaporation, the target can be kept at a relatively low temperature, making this one of the most flexible deposition techniques. It is especially useful for compounds or mixtures, where different components would otherwise tend to evaporate at different rates. Pulsed laser deposition systems work by an ablation process. Pulses of focused laser light vaporize the surface of the target material and convert it to plasma; this plasma usually reverts to a gas before it reaches the substrate.

Evaporation

There are three basic types of kinetics in an evaporation process. The conversion of source material to gaseous state, then the transport source atoms to substrate which is away at a distance h and finally the deposition atoms on substrate. The details of each of these steps are described below:

Fig. 3.22: Conversion of source material to gaseous form

In the first stage, as shown in Fig. 3.22 the gaseous state is achieved by heating the source so that its vapor pressure (Pvapor) is greater than 10-4 torr. The evaporation is carried out in standard base vacuum pressures and the evaporation rate (flux) can be estimated from kinetic theory described in previous section. Some sources sublime from solid while others evaporate from liquid. When source compounds are changed to vapor, it may break apart and produce films with different stoichiometry. For example instead of SiO2, one may end up with SiOx, where x < 2. Similarly, metal alloy sources do not give same alloy in film; its components evaporate independently based on each separate vapor pressure and the composition of alloy source also changes with time.

The source vapor transport to surface is a line of sight deposition. In a good vacuum environment, long mean free path is achieved and thus collisions in gas can be avoided. For longer source to substrate distance, one needs higher vacuums. Typically, for a separation of 10 to 100 cm, a vacuum of 10-5 torr and lower are required. The particles have energies (~kT) comparable to evaporation temperature and at 1000°C, it is about 0.2 eV.

The distribution of evaporant depends on geometry of source and on position of target. Point source and planar source (surface Source) are considered in this section. The distribution of evaporant in the case of point source case is given in Fig. 3.23. If the target of area dAS is tilted of from radial direction by an angle projection of dAS onto sphere of radius r is dAScos as shown.

Fig. 3.23 : The distribution of evaporant in the case of point source

Consider a mass hitting dAS is dMS and Me , is the total evaporated mass,

From the equations, it can be seen that the distribution depends on . However, planar sources are more practical.

Fig. 3.24 : The distribution of evaporant in the case of planar source

Consider a source atoms enclosed cell with an opening as shown in Fig. 3.24. How many atoms reach the opening

travelling in the direction ?

If directions are random, volume of possible atoms coming out is . The number of atoms headed in right direction is given by

Integrating over time and source area we get

The last part of kinetics in an evaporation process is the deposition onto substrate and the film thickness (d) depends on

r, , through dM/dAs .

Consider flat substrate perpendicular to source as shown in Fig. 3.25,

 

Fig. 3.25 : The deposition of evaporant to a flat surface perpendicular to source

For this geometry: = , cos = h/r , r = (h2 + l2 )1/2 and in general :

For a point source, the equation becomes

where do is the maximum thickness.

For a surface source, the equation becomes

and

When compared to a point source the surface source has slightly poorer thickness uniformity. For better uniformity, one needs to decrease sample size (l) and increase distance to substrate (h). This situation calls for a possible in a bigger chamber and with better vacuum and it means that lot of evaporant is wasted. Better uniformity can also be improved by the use of multiple sources, moving substrate during deposition and using rotating crucible to reduce evaporant near center. If source and substrate are kept on same sphere surface as given in Fig. 3.26, then the equations become

and the dependency on , or r on is avoided.

Fig. 3.26 : Placement of source and substrate on a spherical surface

There are several sources of contamination in an evaporation scheme. Contamination occurs from source materials, source/substrate heaters and residual gas in chamber. One can have good film purity by using high purity source materials, using low diffusion materials as source/substrate heaters, with better vacuum and higher deposition rate

materials . The e-beam process though expensive, is usually "better" than thermal evaporation because of less contamination from the source holder. Only the desired material is heated and sustains high quality vacuum environment. They are especially suitable for higher melting point materials (T~3000°C). Higher deposition rates and better control of deposition rates also makes e-beam an attractive choice. As shown in Fig. 3.27, the step coverage is poor in evaporation methods because of shadow effects. By contrast, the CVD and sputtering offer better step coverage.

Fig. 3.27 : Step coverage in an evaporation and CVD process

Sputtering process

Sputtering is used in industry as a means of depositing both metals and insulators. During ion bombardment, energy can be transferred from incoming ions to a surface at an appropriate rate such that atoms are physically removed from the surface. This section starts with an introduction to plasma. Sputter deposited film properties depend on the parameters of the sputtering system, such as pressure and substrate bias. We will discuss the cause and effect of sputtering parameters on deposition processes and their relationship to film properties. The different sputtering systems such as DC, RF and magnetron are also covered.

Sputtering is carried out in a plasma chamber. Plasma is the fourth state of matter. As we increase the heat added to a solid, it will eventually make phase transitions to the liquid state, become gaseous and then finally the bonds binding electrons and ions are broken and the gas becomes electrically conducting plasma. Plasma is a gaseous collection of ions, electrons, energetically excited molecules, and a large number of neutral gas species, normally created by the application of electromagnetic fields. Plasmas can be used to drive reactions that would otherwise be thermally prohibited. Plasmas are used to deposit, chemically etch or sputter materials.

In the simplest case, plasma is formed by applying a potential difference (of a few 100 V to a few kV) between two electrodes that are inserted in a cell (or that form the walls of the cell). The cell is filled with a gas (an inert gas or a reactive gas) at a pressure ranging from a few mTorr to atmospheric pressure. Due to the potential difference, electrons that are emitted from the cathode, are accelerated away from the cathode, and give rise to collisions with the gas atoms or molecules. If e* is an excited electron in plasma, the following types of reactions can occur in plasma:

The excitation collisions give rise to excited species, which can decay to lower levels by the emission of light. This

process is responsible for the characteristic name of the "glow" discharge. The ionization collisions create ion-electron pairs. The ions are accelerated toward the cathode, where they release secondary electrons. These electrons are accelerated away from the cathode and can give rise to more ionization collisions. In its simplest way, the combination of secondary electron emission at the cathode and ionization in the gas, gives rise to a self-sustained plasma. Most modern plasmas are generated by either a DC current flowing through the gas or a radio frequency (RF) field exposed to the gas. RF plasmas do not require DC current flow, and thus, can be used to process insulating and conducting materials.

In the direct current (DC) glow discharge, a continuous potential difference is applied between cathode and anode, giving rise to a constant current. A schematic representation of a chamber, plasma glow and plot of potential is given in Fig. 3.28. The ionization breakdown of a heavy inert gas such as argon occurs when a spark voltage (VDC) is applied which is greater than the breakdown voltage (Vbr). The number of ions resulting (Ar+ plus electrons e-) will be much lower; typically less than 1% of the atoms in the chamber. Plasma maintains almost perfect charge balance. To maintain a self sustaining plasma, the VDC has to to much higher compared to Vbr. The plasma is highly conductive at low frequencies due to electrons. The conductivity of ions compared to electrons is much lower because ions are heavy and have much lower velocities. However, this set-up gives problems, due to the constant current; the electrodes will be charged up, leading to burn-out of the glow discharge.

Fig. 3.28: A schematic representations of a chamber, plasma glow and plot of potential

One important characteristic of plasma is their capability to shield out electrical potentials applied to them by redistributing their charged constituents. When an object is placed in plasma, it acquires a net negative charge because the electron thermal speed is much greater than the ion thermal speed, which causes more electrons to hit the object than ions. As the object charges negatively, the electrons start to be repelled. Equilibrium occurs when the electron current collected by the object balances the incident ion current. An electrically polarized region is thereby formed around the object. This polarized region is called a plasma sheath, or sometimes a positive ion sheath, because the electrons are largely excluded from the sheath. The exact form of the electrostatic potential distribution is complicated however in specific cases the potential decays exponentially with a characteristic length scale given by the Debye length.

Similar to the above discussed evaporation kinetics; there are three processes in sputtering also as shown in Fig. 3.29. The source material is to be change to gaseous state, then the transport source atoms to substrate and finally the deposition atoms on substrate.

Fig. 3.29 : Kinetics of a Sputtering Process

First we want see how the target atoms going into the gas phase. Sputtering is a momentum transfer process. Approximately 95 % of incident energy goes into the target top 10 Å layers and the target need to be cooled. This process can be modeled using hard sphere collisions. 5% of incident energy is carried off by target atoms and approximately 1 to 2% of the atoms in the target are ejected as ions and electrons (T and T+). These electrons are useful in keeping the plasma going. Target atoms come off with a non-uniform distribution. The process can be characterized by sputter yield (S) and it is the number ejected / number incident ions. S depends on mass and binding energy of the target material, mass and energy of the sputtering gas, and the angle of incident. The sputter yield is found maximum at about 20-30 degrees from glancing. Usually there exists a threshold energy exists and typical values of S about 1-10. In sputtering, unlike in evaporation, the composition of alloy in deposited film is approximately the same as alloy in target. This is because of the slow diffusion mixing of solids in case sputtering compared to rapid mixing in evaporation.

During the transport of atoms of to substrate, they pass through Ar gas and plasma environment. Typically one Ar+ ion for every 10,000 Ar neutrals results and the electrons in plasma collide with Ar neutrals to form ions and additional electrons. Target atoms collide with Ar atoms, Ar+ ions and electrons and typically lose 1-10 eV energy. The movement can be considered as random walk "diffusion" through gas. This is not a line of sight process and one can coat around corners. During the deposition, not only target atoms, but also the ions/electron can impinge on substrate. The growth of deposited films is enhanced by these energetic particles as well as by substrate heating to100 - 200°C.

Sputter Deposition Techniques

There are three basic sputtering techniques; DC (diode), RF (radio frequency) and magnetron. As discussed above, the DC sputtering is simple and is shown in Fig. 3.30. When the Argon gas pressure is increased the scattering of Ar ions with neutral Ar atoms also increases. If the gas pressure is decreased, the number of Ar/ Ar+ is also decreased. As a result, the optimum deposition rate is around 100 mTorr which is a compromise between the available number of Ar ions and their scattering. If one can increase the number of ions without increasing the number of neutrals, one can operate at lower pressures.

            

Fig. 3.30 : DC plasma system

Increasing the sputter voltage increases the sputter yield and typically voltages are from -2 to -5 kV. The deposition rate is increased by means of sputter yield and is found decreased with increasing Ar pressure. Usually a substrate bias voltage is applied to avoid electrons hitting the substrate while neutral atoms being deposited independently. Substrate temperature increases with increasing sputter voltage and decreases with increasing substrate bias. The deposition rate also usually decreases with increasing substrate bias.

RF Sputter Deposition

In DC systems, positive charge builds up on the cathode (target) and typically one requires 1012 volts to sputter insulators. To avoid this charge build up, an RF potential is used and can be used for depositing insulating materials. Sputter deposition occurs when target is negative. The schematic diagram of an RF plasma system is shown in Fig. 3.31. The substrate and chamber make a very large electrode and so not much sputtering of substrate occurs.

Fig. 3.31 : Radio Frequency (RF) plasma system

When the frequencies are less than about 50 kHz, electrons and ions in plasma are mobile and both follow the switching of the anode and cathode. This is equivalent to DC sputtering of both surfaces. At frequencies above about 50 kHz, since ions (heavy) can no longer follow the switching and electrons can neutralize positive charge build up sputter deposition occurs as shown in figure. And it is easy to keep plasma going under these conditions. RF sputter can operate at lower Ar pressures (1-15 mTorr) and the fewer gas collisions lead to more line of sight deposition.

The Magnetron Sputter Deposition

The Magnetron Sputter Deposition can be used with DC or RF. The goal is to increase ionization of Ar. This leads to higher sputter rates at lower Ar pressures (down to 0.5 mTorr) and more line of sight depositions. The probability of electrons striking Ar is increased by increasing electron path length using a crossed electric and magnetic fields. This is achieved by placing magnets (200 Gauss) behind target. The basics electromagnetic interactions are shown in Fig. 3.32. This leads to traps electrons near cathode resulting more ionization near cathode (10 times) and fewer electrons reach substrate (less heating).

Fig. 3.32: Direction of Electric field Magnetic field lines during their interactions

Table 6 : Comparison of evaporation and sputtering

EVAPORATION SPUTTERING low energy atoms higher energy atoms high vacuum path

few collisions

line of sight deposition

little gas in film

low vacuum, plasma path

many collisions

less line of sight deposition

gas in film larger grain size smaller grain size

fewer grain orientations many grain orientations poorer adhesion better adhesion

So far we have discussed two important physical vapor deposition techniques, evaporation and sputtering and the important features of these two are compared in Table 6. In the next section we will study Chemical Vapour deposition (CVD) process that involves depositing a solid material from a gaseous phase. It is similar in some respects to PVD. PVD differs in that the sources are solid, with the material to be deposited being vaporized from a solid target and

deposited onto the substrate. The formerly discussed sputtering or chemical vapor deposition systems can be combined with ion assisted and reactive ions deposition schemes. In case of ion assisted deposition, the surface is bombarded with relatively low voltages (50 - 300 eV) ions not necessarily same type as in film. The goal is not typically to incorporate ions in film but for physical rearrangement and local heating. It can change film properties. Similarly in Reactive Sputter deposition, reactive gases like oxygen, nitrogen etc is added to chamber during deposition to facilitate chemical reaction on substrate and target.

Chemical Vapor Deposition

CVD is an extremely versatile process that can be used to process almost any metallic or ceramic compound. Some of these include elements, metals and alloys, carbides, nitrides, oxides and intermetallic compounds. Materials are deposited from the gaseous state during CVD and there p recursor gases are often diluted in carrier gases and delivered into the reaction chamber. As they pass over or come into contact with a heated substrate, they react or decompose forming a solid phase which and are deposited onto the substrate. The substrate temperature is critical and can influence what reactions will take place. In this section we will discuss the basic steps involved in a CVD process, typical precursor materials used, different types of CVD processes and systems.

Fig. 3.33 : Schematic diagram of a horizontal CVD system

The basic steps in CVD film growth are production of appropriate source gas, transport of gas to substrate, adsorption of gas on substrate, reaction on substrate and the transport of "waste" products away from substrate. The growth of films depends on all these kinetics. CVD can be carried out in a horizontal reactor as shown in Fig. 3.33. A CVD apparatus will consist of several basic components:

Gas delivery system – For the supply of precursors to the reactor chamber Reactor chamber – Chamber within which deposition takes place Substrate loading mechanism – A system for introducing and removing substrates Energy source – Provide the energy/heat that is required to get the precursors to react/decompose Vacuum system – A system for removal of all other gaseous species other than those required for the

reaction/deposition. Exhaust system – System for removal of volatile by-products from the reaction chamber. Exhaust treatment systems – In some instances, exhaust gases may not be suitable for release into the

atmosphere and may require treatment or conversion to safe/harmless compounds.

Process control equipment – Gauges, controls etc to monitor process parameters such as pressure, temperature and time. Alarms and safety devices would also be included in this category.

The flow of gases is parallel to the surface of the wafers. The drop in growth rate with distance can be reduced by tilting the susceptor by about 5°. The goals of m ass transport in gas are to deliver gas uniformly to substrate (uniform films) and to optimize flow for maximum deposition rate. From kinetic theory of gasses, we have seen in previous sections that

the dimensions of the system (D) is proportional to . In a CVD system, the pressure is reduced for higher D and higher deposition rate. And the low flow rates produces laminar flow which desirable compared to turbulent flow at high flow rates.

Fig. 3.34 : A laminar flow passing over plate

A simple case of laminar flow passing a plate is shown in Fig. 3.34. The velocity of flow near plate is very small and this results in a stagnant layer. The gas can diffuse through stagnant layer to surface. The mass transport depends fundamentally on reactant concentration, diffusivity and on boundary layer thickness. In terms of experimental parameters it depends on pressure, gas velocity, temperature distribution, reactor geometry and gas properties like viscosity etc.

Fig. 3.35 : Basic model of CVD kinetics

Grove has developed a simple model in 1967. Consider a gas AB decomposed to solid A and gas B. Let F1= flux to surface, F2= flux consumed in film, CG= concentration of AB in gas, CS= concentration of AB at surface.

where hG= gas diffusion rate constant and where kG= surface rate constant. In steady state: F1= F2= F leading

The growth rate of film is proportional to F and there are rate-limiting cases. In the case of small hG, it is mass transfer limited and growth controlled by transfer to substrate; hG is not very temperature dependent the common limit is at higher temperatures. For small kS, it is surface reaction limited and the growth controlled by processes on surface like adsorption, decomposition, surface migration, chemical reaction, desorption of products. The kS is highly temperature dependent (increases with T), common limit at lower temperatures. This is often preferred scheme.

The gas sources are thermally, optically, or electrically (plasma) reacted with a surface. There are four different types of CVDs are popular; Atmospheric Pressure CVD (APCVD), Low Pressure CVD (LPCVD at ~0.2 to 20 torr), Metal Organic CVD (MOCVD) and Plasma Enhance CVD where plasmas are used to force reactions that would not be possible at low temperature.

Low Pressure Chemical Vapor Deposition (LPCVD)

Low Pressure Chemical Vapor Deposition (LPCVD) can be used for a variety of materials such as polysilicon for gate contacts, very short interconnect lines and resistors in analog technologies; thick oxides used for isolation between metal interconnects; doped oxides useful for global planarization; nitrides and other dielectrics for isolation or capacitors (higher K materials for larger capacitance) and metals for seed layers for vias and interconnect lines (not typically used for the entire metal line due to slow deposition rate)

LPCVD for Si Technology

For polysilicon deposition Si containing compounds are reacted with the wafer at ~0.2 to 1 torr and ~575-650°C. Silane (SiH4) is the most common silicon source and typically 100% silane or 20-30% silane with 80-70% inert gas is used as precursors. The temperature range is either limited by low deposition rate at low temperature end (insufficient thermal energy for the reaction) or by the formation of particles in the gas phase (gas spontaneously reacting before it reaches the wafer) and poor adhesion. On the upper temperature end deposition rate is limited by reaction rate (controlled by temperature and pressure) and arrival rate (controlled by gas pressure). Crystalline Structure is also controlled by temperature. Poly-Si can be doped using Diborane (B2H6), arsine (AsH3) or phosphine (PH3), diffusion or by implantation. Diffusion process results in lowest resistivity doping compared to high resistivity doping in implantation.

The resistivity can vary from ~10-3 to 10+5 -cm. Doped poly-Si makes good short interconnect lines.

LPCVD Technology for Oxides

Both undoped as well as doped oxides can be deposited using LPCVD. Undoped oxides are used as an insulator between multilevel metalization, implantation or diffusion mask, increase thermal oxide thickness for high voltage devices., P-doped is used as a multilevel metalization insulator, final passivation layer (prevents ionic diffusion), or as a gettering source. Either Silane or Dichlorosilane known as DCS {SiCl2H2} or Tetraethoxysilane known as TEOS {Si(OC2H5)4} are used as silicon sources. The following reactions occur during undoped oxide deposition.

1. < 500°C Contain H2O, SiH, and SiOH impurities

2.    ~900°C contains Cl

3. 650-750 °C 4. TEOS + Ozone (O3)     ~400°C

Ozone is more reactive and lowers deposition temperatures to ~400°C

 

PSG (Phosphorosilicate Glass) and BPSG (Borophosphorosilicate Glass) are examples of doped oxides and are useful as filling layers. Doped Oxides (glasses) can be made to “flow” or smooth out. This is particularly useful for smooth interconnects (prevents sharp edges which tend to break metal lines) or for partial global planarization for subsequent lithography steps. The following reactions occur during doped oxide deposition.

1.

2.

LPCVD of Silicon Nitride

Silicon Nitride is used for encapsulation; a process which seals up the device/circuit against contamination from air, moisture, plastics used in packaging etc. It is sometimes used for a dielectric isolation layer and as gate dielectric. Oxide/nitride mixtures known as oxynitrides are useful in FLASH memories. The following reactions occur during doped oxide deposition.

1.

2. contains up to 8% hydrogen

Please note that the above reactions are typical examples and many a lternative CVD chemistries are also available.

Metal Organic Chemical Vapor Deposition (MOCVD)

Many materials that we wish to deposit have very low vapor pressures and thus are difficult to transport via gases. One solution is to chemically attach the metal (for example Ga, Al, Cu, etc...) to an organic compound that has a very high vapor pressure. Organic compounds often have very high vapor pressure (for example, alcohol has a strong odor). The organic-metal bond is very weak and can be broken via thermal means on wafer, depositing the metal with the high vapor pressure organic being pumped away. Care must be taken to insure little of the organic byproducts are incorporated. Carbon contamination and unintentional hydrogen incorporation are sometimes a problem. As the human body absorbs organic compounds very easily, the metal organics are very easily absorbed by humans. Once in the body, the weak metal-organic bond is easily broken, thus, poisoning the body with heavy metals that often cannot be easily removed by normal bodily functions.

Molecular Beam Epitaxy (MBE)

Crystalline semiconductors are grown by raising the temperature to allow more surface migration and by using a crystalline substrate such as Si, GaAs, InP wafer, etc. Epitaxial growth is primarily used for II-VI, and III -V semiconductors, special metallic oxides and metals. MBE dominates III -V electronic market and strong competitor in upper end LASER market. In an UHV (ultra high vacuum) chamber, ultra high purity materials are evaporated. Because of the very low pressure, the mean free path is very long, typically hundreds of meters. Thus, the evaporated material travels in a straight line toward a hot substrate. After reaching the substrate, the atom or molecule moves around until it finds an atomic site to chemically bond to. Shutters can be used to turn the beam flux on and off. The flux of atoms/molecules is controlled by the temperature of the evaporation source/cell. Due to ultra high vacuum conditions,

MBE offers the highest purity depositions. By this method, almost any fraction of an atomic layer can be deposited and layers can be sequenced one layer at a time; for example Ga then As then Ga etc.

Plasma Enhanced Chemical Vapor Deposition (PECVD)

Stoichiometry is not guaranteed in PECVD systems where depositions take place under non-thermal equilibrium conditions. Thus, instead of Si3N4 or SiO2 , one obtains SiXNY or SiOX where x and y can vary resulting in amorphous

Silicon to SiN/SiO2. Due to the rapid deposition without the temperatures required for surface migration, films tend to be porous leading to lower density than thermally grown films. Post deposition anneals in either O2 or NH3 are required to

increase the density of the films. Typically, diluted SiH4 for the Si source combined with N2 or NH3 for the nitrogen source are used for nitrides depositions. Films can have very high hydrogen content. Similarly, for oxide and oxynitride

depositions SiH4 combined with and O2 / N2O mixtures can be used.

Table 7 : Comparison of various CVD schemes

  APCVD LPCVD MOCVD PECVD

Advantages

High deposition

rates, simple, high throughput

Excellent uniformity,

purity

Highly flexible and can deposit

semiconductors, metals, dielectrics

Uses low temperatures necessary for

rear end processing

Disadvantages

Poor uniformity,

purity is less than LPCVD

Lower (but reasonable) deposition rates than APCVD

HIGHLY TOXIC!, Very expensive source material. Environmental

disposal costs are high

Plasma damage typically results

Major applications

Mainly for thick oxides

Polysilicon deposition, dielectric

layer deposition, and doped dielectric

deposition

Dominates optical (but not electronic) III-V technology,

some metallization processes (W plugs and Cu)

For dielectrics coatings

Table 7 compares the different CVD schemes. Advantages of CVD include its high growth rates, ability to deposit materials which are hard to evaporate, good reproducibility and growth of epitaxial films. However CVD involves high temperatures, complex processes and toxic and corrosive gasses. Film stoichiometry and density can be monitored by a combination of etch rate comparisons to thermally grown films and ellipsometry to determine the index of refraction of the films. Any dissimilar material deposited on a wafer can cause film stress. This puts a finite limit on the thickness of the film can be deposited before wafer bowing or film cracking occurs. Having discussed with the film deposition methods such as PVD and CVD now we move on to film modification

methods such as diffusion and ion implantation in the next major section.

3.5 Ion-Implantation and Diffusion

Diffusion and Ion Implantation are the methods by which impurity is introduced into silicon to change its resistivity. These processes allow the formation of sources and drains of MOSFETs and active regions of bipolar transistors. In diffusion (in a high temperature environment) the dopant atoms are moving from a highly concentrated region to a low concentrated region. The classic approach to creating regions of silicon with different electrical properties was to deposit a dopant material, on the surface, then diffuse or drive it into the surface of the silicon by exposing it to controlled periods of high temperature. As device geometries have become smaller, the side-ways diffusion has become more difficult to deal with, so the industry has converted to the ion implantation process. In implant, the dopant molecules are implanted vertically into the surface of the silicon by a high-energy ion beam. This penetrates the silicon vertically without any appreciable side-ways diffusion. Thus p-type or n-type regions in silicon are created when they are doped with Boron and Phosphorous ions respectively.

This section treats the diffusion and Ion Implantation processes. The diffusion is discussed first. It begins with the physics and simple mathematical model governing two practical cases of diffusion called unlimited source and constant source diffusion. This is followed by a brief discussion of the diffusion systems and different source materials for the doping of semiconductors. Finally case studies like base diffusion for a BJT and diffusion in PN junctions are presented. The discussion on Ion Implantation begins with a comparison between these two processes with the advantages and drawbacks of ion implantation. This is followed by the dopant ion-substrate interactions and Ion Implant equations concerning the implant profile and depth. This section closes with a brief sketch of Ion Implantation equipment. The following section starts with diffusion of dopants in a Si lattice.

Basics of Diffusion

A drop of color in a glass of water spreads from concentrated region to surroundings. This occurs because of the diffusion of color molecules. Similar situation take place when free charge carriers spread in a semiconductor and dopant atoms diffuse in semiconductor at elevated temperature. In this section we use the term diffusion in the later sense. In general, the diffusion is motion of species in solids in the direction of concentration gradient. The chemical process of diffusion is described by the second order differential equation known as Fick's laws.

Fick's first law is used in steady state diffusion , i.e., when the concentration within the diffusion volume does not change with respect to time (Fin=Fout).

Where F is the diffusion flux (in number of dopants cm-2 s-1), D is the diffusion coefficient or diffusivity (in cm2 s-1), n is the concentration of dopants (in cm-3), x is the position (cm).

The diffusion coefficient (D) determines rate with which element moves in a given solid by diffusion. D depends strongly on temperature and varies between elements by orders of magnitude. For example in the case of diffusion in silicon diffusion coefficient for gold (Au), is in the range of 10-3 cm2 /sec (fast diffusant) while for Antimony (Sb) is in the range of 10-17 cm2 /sec. Since D is a function of temperature, the flux (F) is also a function of temperature. Negative sign indicates that the flow is down the concentration gradient.

Fick's second law is used in non-steady or continually changing state diffusion, i.e., when the concentration within the diffusion volume changes with respect to time. Because diffusion in solids is slow, diffusion is almost always transient.

This can be derived from the First Fick's law and the mass balance assuming the diffusion coefficient D to be a constant. This equation state that the dopant will redistribute until it is spread uniformly throughout the material. The time scale of this redistribution is given by the coefficient of diffusion.

The tendency toward diffusion is very strong even at room temperature because of the high molecular velocities associated with the thermal energy of the particles. The diffusion coefficient is temperature dependent, and is can be described by the Arrhenius expression:

D = D 0 exp(- E a /RT)

k is Boltzmann's constant. D0 (is the maximum diffusion coefficient (at infinite temperature) and Ea (the energy of activation) is constants describing the diffusion. All kinds of diffusion require a certain minimum energy to occur and it can be called the activation energy. The higher the activation energy, the harder it is for diffusion to occur. The activation energy and maximum diffusion constant of different elements is given in Table 8.

Table 8 : The activation energy and maximum diffusion constant of different elements

S i B In As Sb P Units

D 0 5 6 0 1 . 0 1 . 2 9.17 4.58 4.70 cm2 s -1

E A 4.76 3 . 5 3 . 5 3.99 3.88 3.68 e V

The temperature dependence is often shown graphically in an Arrhenius plot where the logarithm diffusion coefficient is plotted against 1/T . Such a plot will be a straight line with slope -Ea/k and intersects the log( D) axis in log(D0) . The Arrhenius plot of B, P and As in Si is shown in Fig.3.36. The D0 and Ea of a particular dopant can be determined experimentally by measuring the diffusion coefficient at different temperatures. The temperature dependency of the diffusion process is exploited for significant matter transport and usually the temperature is kept above 800°C for almost all dopants.

Fig. 3.36 : The temperature dependency of diffusion constant of B, P and As in Si

Typically one use higher doping concentrations and lower thermal budgets for semiconductor fabrication. It was observed that Fick's laws are not accurate enough for the explaining the anomalous diffusion behavior. Therefore it is necessary to focus on atomistic level to get insight on the interaction of dopants with lattice atoms. It is established that diffusion of impurities can only occur within the crystal lattice due to the presence of point-defects.

Diffusion by point defects

Diffusion occurs in silicon primarily at native point-defects and impurity-related point defects. Typically native defects such as point defects, line defects and surface defects are present in an otherwise perfect crystal lattice. At room temperature point defect concentration is low that practically no diffusion occurs. However, an increase of point defects will cause an increase in the diffusion. The concentration of point defects will increase for example if the crystal is heated or irradiated by ion. Both situations are likely to occur during the fabrication of devices. Impurity related defects arise from the introduction of group- III elements or group-V elements into the silicon lattice.

Normally dopants will occupy a lattice site, and the dopant is said to be substitutional. When the dopant is in the substitutional position it is not likely that it will move around. However, when it gets in contact with a point defect, it will be mobile. A point defect in silicon, can be a Si self-interstitial (a silicon atom which does not occupy a lattice site), or a vacancy (a lattice site which does not contain a silicon atom). As illustrated in Fig. 3.37, t here are mainly two possible atomic diffusion mechanisms known as interstitial and vacancy diffusion. The diffusion mechanisms through grain boundaries and surface are also possible. The highest activation energy is for volume diffusion though interstitial and vacancy sites. The grain boundary diffusion requires less energy and surface diffusion requires the least.

Fig. 3.37 : Diffusion mechanisms within crystal targets

Diffusion through interstitial spaces: Impurities which have small ionic radii can travel directly from one interstitial site to another one (see Fig.3.37). Especially Group-I and Group-VIII elements are diffusing mainly interstitially and are therefore fast diffusers.

Vacancy Diffusion: Vacancies are holes in the matrix and they are always moving. An impurity can move into the vacancy and diffuse through the material. A substitutional dopant can exchange its position with the neighboring vacancy. Similarly when a dopant at a substitutional site is kicked out by a silicon interstitial atom, the dopant occupies the interstitial position while the original self-interstitial has disappeared by occupying the regular lattice site.

Thus dopants can diffuse within a crystal lattice using point-defects as diffusion vehicle either by the vacancy mechanism or the interstitial mechanism or a combination of both. The dopants are selected based on their properties such as solubility in silicon, dissolution into lattice sites and ionization. The most common p-type dopant boron diffuses

mainly via interstitials, where the n-type dopant phosphorus shows at intrinsic concentrations interstitial dominated diffusion and for high concentrations a dual mechanism with a strong vacancy component. Arsenic is also diffusing via interstitials and vacancies, but the interstitial diffusion is at least limited due to the relatively large ionic radii. Large dopants like Antimony will find no stable position between lattice sites, so they can only diffuse via vacancies.

 

The transport of dopants within the lattice is not only controlled by the diffusion mechanism, there are also recombination processes between dopants and point-defects occurring, which can disturb or even prevent dopants from diffusion. These recombinations are always possible when dopant-defect pairs are approaching lattice defects of the opposite type. If the dopant concentration level is significantly below the intrinsic carrier concentration, the diffusivities of the dopants show no dependence on the doping level.

In the subsequent section we will focus on two practical circumstances in which the diffusion can be carried out. Diffusion from an unlimited source (Constant source diffusion) occurs when a wafer is exposed to an infinite amount of dopants during the diffusion period. In the case of diffusion from a limited source, a finite quantity of the dopants is first placed on the wafer and diffusion proceeds from this limited source and it is assumed that all the dopants are consumed.

Diffusion from an unlimited source

The surface concentration will be fixed at the solid solubility, and the distribution will be in the form of a complimentary error function:

where :

N = concentration (cm-3)

N 0 = solid solubility limit for dopant (cm-3)

x = position inside silicon relative to the surface D = diffusion coefficient for dopant (cm2/s) t = time (seconds)

If one sketch of this concentration profile for various diffusion times, one can observe that the surface concentration is constant where as the diffusion depth increases with time. Please note that the Dose beyond x=0 continues to increase with diffusion time. Note that the dose is given by

The error function values for typical values are given in the Table 9.

Table 9 : Typical error function values

Z erf(Z) Z erf(Z)0.00 0 0.60 0.6039 0.10 0.1125 0.70 0.6778 0.20 0.2227 0.80 0.7421 0.30 0.3286 0.90 0.7970 0.40 0.4284 1.00 0.8427 0.50 0.5205 1.50 0.9661

Diffusion from a limited source The solution that satisfies Fick's second law when a fixed dose Q is introduced as a delta function at the origin is given by

Fig. 3.38: Double sided iffusion from a delta source at origin

Fig. 3.38 shows the double side diffusion profile resulting from a delta source at origin. Please note the following important consequences:

1. Dose Q remains constant before and after diffusion

2. Peak concentration decreases as

3. Diffusion distance from origin increases as

 

This equation can be slightly modified to model a practical situation where all the dopants from the constant source are consumed entirely to one side.

Fig. 3.39 : Single side d iffusion from a delta source at origin

The solution is given by

Also note that the infinite source diffusion case discussed previously can be thought infinite source of dopant made up of small slices each diffusing as a Gaussian. Error function solution is made up of a sum of Gaussian delta function solutions.

Fig. 3.40 : Diffusion profiles in constant source and limited source cases

Diffusion Systems

The diffusion process is carried out in systems called diffusion furnaces which may be either sealed or open tube type. The silicon wafer and the dopants are placed into the quartz tube before sealing and subsequently after the high temperature process; the tube is broken to remove the diffused wafers. Thus the sealed tubes are for one time use and can be maintained contamination free. The open tube method is preferred because multiple diffusion runs can be

carried out. Separate tubes for each type of dopants are maintained because tubes are contaminated with the respective impurity. The insertion of wafers and solid dopant sources are done from one end of the tube and the other end is used for the flow of gases or impurities in vapour form. The diffusion furnaces are usually operated at temperatures 600°C-1200°C and constant temperature zones are maintained with a ± 0.5°C tolerance.

Three main sources of dopants such as gaseous, liquid and solids source of dopant atoms are used in semiconductor doping processes. The gaseous sources are most widely used since they are reliable and convenient. The typical examples are BF3 (diborane), PH3 (phosphine) and AsH3. Source gas reacts with oxygen at the wafer surface to form a dopant oxide, the dopant then diffuses from the oxide into silicon resulting in a uniform dopant concentration across the surface.

Liquid sources are available in two forms: Bubblers and spin on dopants. Bubblers convert the liquid to vapour, which then reacts with oxygen to form dopant oxides on the wafers. The spins on dopants are solutions which on drying form doped SiO2 layers. The typical examples of liquid sources are POCl3 and BBr3 (boron tribromide).

Solid sources are available in two forms; such as tablet/granular and disc/wafer form. BN discs are most commonly used oxidized at 750 - 1100°C to serve as the boron diffusion source. Dopants are introduced into the silicon substrate using a two step, high temperature process. The first diffusion (predeposition) introduces dopants into the wafer. The second diffusion (drive) redistributes the dopants and allows the dopants to diffuse into the wafer more deeply (up to ~3 micrometers). The goal of the dopant predeposition diffusion is to move dopant atoms from a source to the wafer, and later allow the dopants to diffuse into the wafer. In order for the dopants to move into the silicon, they must be given energy, usually in the form of heat. In order for the diffusion to occur in a reasonable time, the temperature must be very high (900ºC <T<1200º). At this temperature the dopant (in the form of an oxide) reacts with the exposed silicon surface to form a highly doped glass. It is from this glass that the dopants can then diffuse into the wafer. Arsenic has a low

misfit factor ( ) and can be incorporated to a high concentration without causing strain the lattice. Arsenic's low diffusivity (about one-tenth of boron or phosphorous) and its abrupt doping profile makes it ideally suited for shallow diffused structures where more precise control of junction depth is needed. Phosphorus also has a high solid solubility

and active carrier concentration close to arsenic. Its misfit factor also is small ( ). these characteristics makes its very useful for the fabrication of n+ regions in MOS and bipolar circuits.

Phosphorus, in the form of P2O5 , diffuses from the source to the wafer. When it reaches the silicon, it will undergo the following chemical reaction:

During the phosphorus predeposition a layer of phosphosilicate glass (PSG) was grown on the surface of the silicon. This layer will act as a constant source of dopants for subsequent diffusion steps, thus fixing the surface concentration of the phosphorus doped areas to the solid solubility limit. The distribution will be in the form of a complimentary error function:

where :

N = concentration (cm-3 )

Ns1 = solid solubility limit for dopant (cm-3)

x = position inside silicon relative to the surface D = diffusion coefficient for dopant (cm2/s) t = time (seconds)

In order to remove the PSG, a three step etch will be performed:

 

remove PSG: HF etch

chemical oxidation: H2SO4 /HNO3

remove chemically oxidized layer: HF etch

Boron Diffusion from a solid source to form a BJT base: a case study

Boron is the most commonly used p-type dopant for silicon, principally because it is the only column III element that can be masked by SiO2. The first step, called the predeposition, is an open tube diffusion process that involves the gaseous transfer of a compound containing the dopant to the Si wafer. The gas may be supplied in several different ways, but in almost all cases the final chemical reaction when it reaches the silicon is:

Boron, in the form of B2O3, diffuses from the source to the wafer. The surface concentration during such constant source diffusion is usually limited by the solid solubility of the dopant in silicon. The boron predeposition transfers boron from a solid source to the wafer. The borosilicate glass (BSG) is in contact with the silicon surface. A concentration gradient is formed, and since this process occurs at high temperature, diffusion will occur. If the boron source used is a solid source of boron nitride wafers, Si wafers are stacked next to oxidized wafers as shown in Fig. 3.41. At the pre-deposition temperature, concentration gradient induced diffusion is established between the source wafers and the silicon wafers.

Fig. 3.41: Boron diffusion from using oxidized boron nitride

wafers

This concentration gradient is a function of the distance between the source and silicon, the temperature of the pre-deposition, and the composition of the gas ambient (oxidizing or non-oxidizing, presence of H2O, etc.). The gas flow rate is kept low enough so that the gas between source and wafer is essentially stagnant. The concentration gradient results in the transfer of B2O3 to the silicon surface, and so produces a very thin, very highly doped region at the silicon wafer surface. The final level of doping and resulting sheet resistance is determined by time and temperature.

The boron concentration near the surface after predeposition is too high and the junction depth is too shallow to act as a good base. The second stage of the diffusion process is a 'sourceless' diffusion called the drive-in and is referred to as constant source diffusion. After the BSG is removed from the surface of the wafer, drive-in will lower the surface concentration and simultaneously drive the dopant deeper into the wafer. The distribution can be approximated as a Gaussian profile:

Where the subscript 1 refers to predeposition and subscript 2 refers to drive in parameters.

N = concentration (cm-3)x = position inside silicon relative to the surface D = diffusion coefficient for dopant (cm2/s) t = time (seconds)

N02 = surface concentration after the drive (cm-3)

N01 = surface concentration after the predeposition (cm-3) = surface

concentration prior to the drive-in (cm-3)

D1 = diffusion coefficient f of dopant during the predeposition (cm2/s)

t1 = time of the predeposition (seconds)

D2 = diffusion coefficient of dopant during the drive (cm2/s)

t2 = time of the drive (seconds)

The BSG (SiO2 - B2O3) is striped off from the pre-deposited Si wafer the using HF. The HF actually attacks the SiO2 , not the B2O3 , so care must be used in the pre-deposition step to prevent the deposition of excessive amounts of B2O3. This is done mainly by assuring no H2O is present in the furnace, which would greatly increase the rate of transfer of B2O3 to the silicon. Also note the thin SiBx phase on the wafer is hydrophilic, so the wafer will not de-wet after etching. The actual drive-in is performed at very high temperatures (~1100°C) without the BN wafers. The drive-in is usually initiated in an oxidizing environment; the initially grown SiO2 act as a mask and prevents the out-diffusion of the boron during the rest of the process.

In general, when a dopant is diffused at temperature T1 for time t1 and followed by diffusion at temperature T2 for time t2 etc., the total effective Dt is given by the sum of all the individual Dt products.

Some of the Dt steps may be negligible in a process. The Gaussian solution only holds if the Dt used to introduce the dopant is small compared with the final Dt for the drive-in i.e. if an initial delta function approximation is reasonable.

Example 5 : In a bipolar transistor, if the emitter profile is formed by a predeposition and the base profile by an implant + drive-in, then the junction for the emitter-base occurs when

 

And the emitter-base occurs when

Example 6 : Boron Diffusion from a solid source to form well: a case study

We can now consider how to design a boron diffusion process, for the well/tub of a CMOS process to achieve the

following specifications:

Let us consider the resistivity of a cube shown in Fig. 3.42.

Fig. 3.42 : Resistivity of bulk and surface charges

The average conductivity of any layer is given by,

where J = current density (A/cm-2 )

n = number of charge carriers i.e. electrons/holes (cm-3)

E = electric field (V/cm)

= mobility of charge carriers (cm2/ V.s)

= resistivity of layer ( .cm)

cm

The sheet resistance of a shallow junction is

For a diffusion made into a background concentration NB, the sheet resistance of a non-uniformly diffused layer is given by

Here is the mobility of majority charge carrier in the diffused layer and is a function of the doping concentration at any depth x . Sheet resistance can be experimentally measured by a four point probe technique. This equation has been numerically integrated by Irwin for different analytical profiles (for example P type Gaussian profiles). Such plots with surface concentration (cm-3) verses effective conductivity ( -cm)-1 are called Irvin's curves

From the Irvin curve we obtain that

Assuming a Gaussian profile after the drive in

Substituting the given values, we get Dt = 3.7x 10-9 cm-2

Assuming a drive in temperature of 1100°C, we know then the boron diffusivity is D =1.5x10-13 cm2 cm-1. Solving for drive in time one get 6.8 hours.

Given both the surface concentration and the Dt product, the initial dose can be calculated this Gaussian profile.

This dose could easily be implanted in a narrow layer close to the surface, justifying the implicit assumption in the Gaussian profile that the initial distribution approximates a delta function. If a gas/solid phase predeposition step at 950°C were used, B solid solubility at 950°C is 2.5x1020cm-3 and B diffusivity is 4.2x10-15cm2s-1 . The dose for an erfc profile is

So that the time required for the predeposition is obtained as 5.5s. One can also see that the Dt pre-deposition << Dt drive-in .

Example 7: Phosphorous Diffusion to form a PN Junction: a case study

Suppose we do a relatively shallow implant of boron into a p-type wafer, and deposit a Q0 of 5×1013 phosphorus atoms/cm2 atoms. We then perform an anneal diffusion at 1100°C for 60 minutes. At 1150°C, D for phosphorus seems to be about 2×10-13 cm2/sec. In Fig. 3.43 a plot of n(x) for various times, to see how the impurities move into the semiconductor, and how the concentration at the surface, N(0) decreases as more and more of the impurities moves deeper into the wafer.

If the substrate had been doped at 1016 acceptors/cm3 where would be the location of the p-n junction between the implanted phosphorus layer, and the background boron?

Solution

Solution obtained is ~ 1.2 m after 1 hour of diffusion time. Because for x<1.2 m, the phosphorus concentration is greater than that of boron, and so the material is n-type. For x>1.2 m, the boron concentration exceeds that of the phosphorous, and so the material is now p-type.

Fig. 3.43: P Concentration profile verses depth for different duration

Ion Implantation

Ion implantation is the introduction of atoms into a solid substrate by bombardment with ions in the keV to MeV energy range. Compared to diffusion, this technique provides wide selection of atomic species as well as external control of both the number the depth distribution of the implanted species. In a diffusion process, surface concentration is governed by the temperature and the depth distribution is determined by both the time and temperature. The initial impact of ion implantation in silicon technology was in charge control. This in combination with the fact that simple masking techniques can be used to define the geometrical area of the implanted region led to extensive to MOS technology. Presently implantation is the most common method of introducing dopant atoms for the fabrication of Si devices.

Advantages

This process provides excellent dose control. Typical 1011 to 1016 cm-2. It has been possible to control the number of dopant atoms per cm2 to about 1% over the surface of a wafer, and to control the number within 3% from wafer to wafer.

The ion implantation results in less lateral diffusion i.e. diffusion of dopant atoms in the direction parallel to the surface of

semiconductor compared to the vertical diffusion where diffusing species are moving in a direction normal to the wafer surface.

The dopant elemental selection can be easily carried out by mass separation from impure sources and this helps in preventing contamination.

The room temperature process allows resist to be used and it allows doping anytime during process.

Modeling is very accurate

Complex doping profiles can be made using multiple energy implants

Highly abrupt junctions can be made

Highly automatic parameters

Limitations

As the energetic ions are introduced in the Si lattice, many Si atoms are knocked off their lattice positions resulting in large numbers of Si interstitial atoms and vacant lattice sites (Frenkel pairs). The as-implanted dopants are usually electrically non-active and the lattice damage deteriorates the device performance. It is necessary to have the annealing of the implanted sample at temperatures high enough to permit the dopant atoms to incorporate into substitutional sites and thus become electrically active, and for the defects to annihilate and thus repair the damage.

However diffusion of impurities in implanted Si can occur during thermal anneal. For example, the diffusivity of B in implanted crystalline Si is anomalously high compared to equilibrium values. It causes the dopant profile to spread significantly compared to the as-implanted profile. The presence of damage also causes dopant clustering and thus prevents complete electrical activation. The down-scaling of Si CMOS devices requires simultaneously the formation of ultra shallow junctions for the source and drain extensions and a low sheet resistance (high carrier concentration). Conventionally, there is a compromise involved in maximizing dopant electrical activation while minimizing dopant diffusion.

The amount of crystallographic damage can be enough to completely amorphize the surface of the target. In some cases, complete amorphization of a target is preferable than a highly defective crystal, for the reason that an amorphized film can be regrown at a lower temperature than required to anneal a highly damaged crystal.

Implantors are very expensive machines, requiring heavy maintainace. The Safety hazard precautions are also stringent because of the radiation, high energy beams and high voltages.

Sputtering : Some of the collision events result in atoms being ejected from the surface, and thus ion implantation will slowly etch away a surface. The effect is only appreciable for very large doses.

Fig. 3.44 : Basic illustration of channelling

 

Ion channeling :Since the semiconductor substrates have crystal structure, particular crystallographic directions offer much lower stopping than other directions. The result is that the range of an ion can be much longer if the ion travels exactly along a particular direction, for example the <110> direction in silicon and other diamond cubic materials as shown in Fig. 3.44. This effect is called ion channelling, and, like all the channelling effects, is highly nonlinear, with small variations from perfect orientation resulting in extreme differences in implantation depth. For this reason, most implantation is carried out a few degrees off-axis, where tiny alignment errors will have more predictable effects. Ion channelling can be used directly in Rutherford backscattering and related techniques as an analytical method to determine the amount and depth profile of damage in crystalline thin film materials.

A comparison of Solid/Gas Phase Diffusion verses Ion Implantation and Annealing is provided in Table 10.

Table 10 Diffusion verses Ion Implantation

Diffusion Ion Implantation   Room temperature mask

  Precise dose control

Usually limited to solid solubility Low dose is hard to achieve

without a long drive-in

Wide range of doses

  Accurate depth control Junction depth limited to 1 micron

No damage created by doping Implant damage enhances diffusion Dislocations caused by damage may cause junction leakage

Implant channeling may affect profile

Batch fabrication Low throughput

Impurity Profiles : Range and Depth Distribution

There are two basic mechanisms by which energetic ions are stopped in a substrate. Ions interact with electrons and nuclei of substrate atoms and lose energy during these collisions. The range (R) is the total distance traveled by an ion before resting. Please note that the path is not a straight line. The Nuclear collisions transfer energy away from ion and the coulombic interaction with electrons transfer energy to electrons.

If Sn (E) is energy loss per unit length due to nuclear stopping and Se (E) is energy loss per unit length due to electronic

stopping, the total rate of energy loss ( ) is the sum of the two losses:

Fig.3.45 : Ion Nuclei interactions

 

If one consider ions as "balls" with momentum p=mv the nuclear stopping is provided by velocity interaction. If the rate of energy loss is plotted as a function of ion energy, it can be seen that the loss increases linearly at low energy because the ion velocity is smaller, the loss reaches maximum and decreases at higher energy because the higher velocity makes ion move too quickly to interact. Sn (E) increases with ion mass (p=mv) and if ions are light (e.g. Boron),

its energy loss/unit length ( ) is much lower.

Se (E) is energy loss per unit length due to electronic stopping. Drag force caused by charged ion in "sea" of electrons (non-local electronic stopping).

Fig. 3.46 : Ion electron interactions

Collisions with electrons around atoms transfers momentum and results in local electronic stopping .

Fig. 3.47 : Electron Electron interactions

 

This is similar to stopping a projectile in viscous medium:

k depends on ion and target mass and atomic number. The lighter ion, boron, has larger . The crossover point between electronic and nuclear stopping is an important parameter. The critical energy Ec when the nuclear and electronic stoppings are equal is

That is for B, Se (E) dominates down to 10 keV and for As, nuclear stopping dominates up to 700 keV.

The range (R) is:

A more significant parameter of interest is the projected range (RP) and it is the distance travelled normal to the surface as shown in Fig. 3.48.

Fig. 3.48 : Range (R) and projected range (R P ) in ion implantation

Fig. 3.49 : Straggle ( R P ) and lateral straggle ( R T ) in ion implantation

Ionic collisions are a statistical process, the ions with same initial momentum do not undergo same collision history and

RP is the depth at which most ions stop. RP (straggle) is the standard deviation of the curve along the direction of the incident ion and RT (lateral straggle) is the standard deviation parallel to the surface. Because of the spread of ions at right angles to its incidence, the lateral straggle is also known as transverse straggle. RT is of importance in determining the doping distribution near the edge of a window which is cut in a mask.

The transverse straggle can be ignored if the width of the window is large compared to the junction depth. When the beam of ions hits the wafer, the concentration of ions in the substrate becomes a function of the depth of the ions. First approximation of this function is a Gaussian curve of the form

The peak concentration occurs where x= Rp

where Q0 is the ion dose (cm-2), Np is the maximum (desired) concentration, Rp is the range or desired depth, and Rp is the straggle or standard deviation. The projected range and straggle can be approximated from range:

Where M1 is the ion mass and M2 is the substrate mass.

A wide variety of masking materials can be used during the implantation and the thickness of the mask can be estimated using the above equations once the range (or stopping) parameters of the mask material is known.

Example : Find the projected range, straggle and peak concentration for a 150 keV, 1014 Phosphorous implant into a 4" wafer. What current density is required if we want each wafer to take no more than 1 minute to be implanted? Will our answer change if we change the implant energy? If wafer has background boron concentration of 3x1015 cm-3, what is the junction depth after implant? 150 keV Phosphorous has RP = 0.2 µm; RP = 0.06 µm. If the implanted sample is annealed for 30 m at 950°C in an inert atmosphere, what will peak concentration be? Where will junction depth be? The diffusion coefficient of P (D) at 950°C is = 3x10 -15 cm2s-1 .

Ans: Np= 6.6x1018 cm-3 and current density (J) =0.27µA/cm-2, x j=0.435 µm. If the implanted profile is Gaussian, later thermal anneal cycles produce a Gaussian profile as well.

Fig. 3.50 : B, P, As and Sb implanted concentration profile in Si

Fig. 3.51: Gaussian profile in the case of implantation followed by thermal anneal

, using the expression

, the peak concentration and junction depth can be calculated; Np= 6.6x1018 cm-3 and junction depth (x j) = 0.435 m.

Ion Implantation systems

Ion implanters are usually specified in terms of two key parameters; the ion energy which determines the penetration depth and the ion current which decides the dose. The basic building blocks of an implanter are ion sources, ion extractors, accelerators to high energies and beam manipulators as shown in Fig.3.52. Ions are produced by passing the gas vapour through a discharge chamber. The electrons are accelerated towards an anode which is typically at 100V. A magnetic field is provided to force electrons into a spiral trajectory and this will enhance the ionisation efficiency. The positive ions are moved out of the discharge chamber by means of another anode biased at 15-20 kV. The pressure in the remaining part of the system is kept below 10 -6 Torr to minimize the ion scattering.

The output of an ion discharge chamber consists of many species in addition to the contamination produced by sputtering from its walls. Thus a mass separator is required to make source pure. The mass separation is based on the dynamics of charged particles, of mass (m) and velocity (v), moving at right angles to a uniform magnetic field (a flux

density of B). These particles will experience a force (F) such that . This force tends ions to move in a

circular path of radius r, and experience a centrifugal force . These forces are equal and opposite. The velocity of

ions is related to the accelerating potential (V) by . Combining these equations, the radius of the ion path

is given as .

Fig. 3.52 : Schematic diagram of a basic implantation system

For a given extraction voltage and magnetic flux density, the r is proportional to square root of mass and thus ions of any particular mass can be selected by appropriately placing an exit slit. The collimators filter a stream of rays so that only those travelling parallel to a specified direction are allowed through. They help to shape the beam of radiation emerging from the machine and can limit the maximum field size of a beam. The surviving ions move into the

accelerator tube where the ion beams gets energized under the very high acceleration potential. The output of the tube is usually maintained at ground potential for safety reasons.

In order to implant in the x and y directions the wafer surface, electrostatic and mechanical beam scanning techniques are used. The electrostatic scanning in both x and y directions is the simplest, and has advantage of very high scanning speed. However, when the beam voltages are 50 keV or higher, beam expansion (blow up) takes place and so mechanical scanning is usually used. In the mechanical scanning system the beam is stationary and the substrate wafer is moved.

3.6 Lithography

Fabrication of devices depends on selective processes such as removal of material (etching) addition of material (deposition) and modification of material (implantation, diffusion, etc.). One need to have defined areas on the substrate exposed to these processes and the rest of the substrate must be protected also during the same processes. These selected/unselected areas make up the pattern. Pattern definition takes place in the resist which is a thin layer of polymeric material coated on the substrate. The resist is modified so that it remains in some areas and is removed in others. Lithography in the integrated circuit technology context is typically the transfer of a pattern to a photosensitive material by selective exposure to a radiation source such as light.

This section starts with how a pattern is transferred to a photosensitive material thus explaining the different terms used in a lithographic system. This is followed by a very brief discussion on the different lithography techniques based on the light/sources. All the process steps required in a lithography technique is outlined next. The different types of image projection methods, comparison between positive and negative resists, new technologies like lift off and image reversal etc are included in these discussions. Finally the section concludes with a brief discussion on the fabrication of masks.

Fig. 3.53: Transfer of a pattern to a photosensitive material

A lithographic system includes exposure tool, mask, resist, and all of the processing steps to accomplish pattern transfer from a mask to a resist and then to devices. A photosensitive material is a material that experiences a change in its physical properties when exposed to a radiation source. If we selectively expose a photosensitive material to radiation (e.g. by masking some of the radiation), the pattern of the radiation on the material is transferred to the material exposed. If the resist is placed in a developer solution after selective exposure to a light source, it will etch away one of the two regions (exposed or unexposed). If the exposed material is etched away by the developer and the unexposed region is resilient, the material is considered a positive resist. If the exposed material is resilient to the developer and the unexposed region is etched away, it is considered a negative resist. Both cases of pattern transfer are depicted in Fig. 3.53.

From the 1960s, when integrated circuits had linewidths of 5 µm, optical lithography has been used universally for manufacturing. Electron-beam (e-beam) and X-ray lithographies can be considered as alternatives to optical lithography. However, wafer throughput with e-beam lithography is too slow for use in current semiconductor wafer production. Currently e-beam lithography is regarded as complementary to optical lithography. Optical lithography depends on e-beam lithography to generate the masks. Because of its intrinsic high resolution, e-beam lithography is at present the primary lithographic technique used in sub-quarter-micron device research.

 

Types of exposures

Light -- 436 nm - 157 nm; near UV to Deep UV optical lithography

X-rays -- 5 nm - 0.4 nm; x-ray lithography

Electrons -- 10 keV - 100 keV; electron beam lithography

Ions -- 50 keV - 200 keV; focused ion beams

Basic steps of a photo lithography process are treated in the following section. The various steps covered are surface preparation, spin coat, prebake (soft bake), exposure and alignment with mask, post exposure bake and developing.

Surface preparation: Clean and dry the wafer. Dehydration is carried out in an oven.

Spin coat: The wafer is held to the spindle using vacuum as shown in the schematic diagram of a photo resist spinner of Fig. 3.54. Dispense about 5 ml of photo resist on to the wafer. Start with slow spin (~500 rpm) and then ramp up ~ 3000 to 5000 rpm. The excess resist fly off during the spinning.

Where is the thickness of the photo resist after spinning, is viscosity of the resist, is the angular velocity and is radius of the wafer.

Fig. 3.54 : Schematic of a photo resist spinner

Prebake (Soft bake): After spinning the photo resist still contains solvents up to 15% and there could be built in stresses. The wafers are prebaked at ~80°C for about 20 minutes to densify the resist and remove the stress. The thickness of the resist is usually decreased by ~25% after this step. The prebake also promotes the adhesion of resist to wafer. Less prebake can increase the development time (rate).

Alignment and exposure:

Let us say that already there is a pattern available on the wafer and the new mask is to be aligned with respect to this pattern. Usually with each mask alignment markers are available and Fig. 3.55 illustrates how these patterns in a mask and wafer are aligned. The proper alignment is achieved using three degrees of freedom available on the alignment bench.

Fig. 3.55 : Illustration of mask and wafer pattern alignment

 

Photolithography can be classified into three based on the type of exposure known as contact, proximity and projection printing, as shown in Fig. 3.56. We will discuss them one by one in the following subsections.

Fig. 3.56 : Illustration of contact, proximity and projection printing

Contact printing :

In the case of contact printing the resist is in contact with the mask. There is no magnification achieved and pattern transferred on the substrate is 1:1. The advantages of this method are inexpensive equipment, faster process and the entire wafer can be exposed at once. The resolution achieved is ~0.5 um or better but is typically limited by resist thickness. The diffraction effect is minimized in this scheme as the gap is between mask and wafer is zero.

Fig. 3.57 : Model of a contact printing scheme

Consider a contact printing scheme as shown in Fig. 3.57. For an exposure wavelength , the minimum line period, achieved with a coating of photo resist with thickness is given by

It is clear from the expression that the resolution is largely limited by the light scattering in the photo resist.

The major disadvantage of this method is the degradation of the mask. Since the wafers are in contact with the mask every run, pinholes and scratches are created on the metal-oxide layers of the mask. If any particles or dirt are present they directly imaged in the wafer and mask-wafer gap variations can results in local loss of planarization leading to non-

uniform resolution regions. Moreover the mask is expensive since it has the same size of the wafer and no magnification.

Proximity printing : In the proximity printing as shown in Fig.3.58, the resist is almost but not in contact with the mask and 1:1 magnification can be achieved. By this technique, the major disadvantages of contact printing are almost nullified. There is no mask wear or contamination, the process is faster and the entire wafer is exposed at once. The same mask can be used for many runs reducing its cost.

Fig. 3.58 : Model of a proximity printing scheme

For an exposure wavelength , the minimum line period, achieved with a coating of photo resist with thickness t and a separation of between mask and resist is given by

The major disadvantage of this method is the diffraction resulted due to the mask separation from wafer. This will lead to low resolution of ~1-2 or slightly better. This is less repeatable than contact methods and the mask is expensive since it has the same size of the wafer and no magnification.

Projection printing

In this method the mask image is projected a distance from the mask and de-magnified to a smaller image onto the wafer. Typically 1:4 to 1:10 magnification is achieved. This results in very high resolution of ~0.07 um or slightly better. The mask contact is completely avoided resulting in almost no mask wear. It would be an advantage for high volume production. In addition, the mask defects or particles on mask are demagnified in size on onto the wafer.

However extremely expensive and complicated equipment is needed for this scheme and the diffraction effects limit accuracy of pattern transfer.

Fig. 3.59 : Diffraction effect in proximity printing for different mask wafer spacing

The Diffraction effect in proximity printing for different mask wafer spacing is illustrated in Fig. 3.59. Three cases are illustrated (a) s is mall (b) s is larger and (c) s is the largest.

After the alignment is accomplished the wafer is exposed to few hundred mJ/cm2 of high energy light in any one of the printing schemes described above.

Developing :

Due to the exposure on selected regions, the resist properties are changed. The developing is used to dissolve the weak regions of photoresist. Development of optical resists takes place in an alkaline solution. Acetone or trichloroethylene is used to develop positive photo resists. Methyl ethyl ketone (MEK i.e. CH3COC2H5) or Methyl isobutyl ketone (MIBK i.e. CH3COC4H9) can be used for negative photo resists.

Simple solutions of NaOH, or KOH could also be used, but because of the possibility of mobile ion contamination in MOS devices, metal ion free developers are often used. These are usually TMAH, tetra-methyl ammonium hydroxide. Some developers also contain surfactants to improve wetting properties. Each developer used has a different dilution, and some require longer development times than others. Developers are generally matched to a type of photo resist. Though they may be interchangeable to some extent, changing the type of developer used in a process will usually change the exposure time necessary to resolve the pattern. Plasma etching with oxygen (Ashing) is also effective for removing organic polymer debris.

Hard bake:

Hard bake is carried out ~110-150°C to stabilize and harden the developed photo resist. This hardening of PR is required for the subsequent aggressive processes such as Ion implantation or Plasma etching. This bake removes the remaining solvent and traces of developing solution. As a result the possible solvent burst effects during the subsequent vacuum processing are eliminated. Post bake introduces some stress in the resist and it may slightly reduce the resist

thickness also. With sufficient time and/or temperature, the resist will undergo plastic flow as illustrated in Fig.3.60 for various temperature cases. Longer or hotter post bake makes the resist removal harder. In some processes like metal lift-off patterning, where soft photo resist is used the hard bake is not needed.

Fig. 3.60 : Illustration of plastic flow in photoresist during baking

Having discussed the different process steps involved in a lithographic technique now we will consider the specifications of lithography i.e. requirements expected from pattern, resists etc. The different pattern requirements are pattern size, feature size and alignment accuracy. Some of the requirements of the technique used for the pattern transfer are mask tone, resist type and resist thickness. The requirements of the lithography tool are field size, alignment marks and mask size and type. Field of view is the maximum area seen through a magnifier and the entire field of view may not be in focus.

Resolution : How small of features can you make? Current production state of the art is ~90 nm and the resolution is “diffraction limited”. Even if a beam of light passes through a single slit, the rays within it interfere with each other and this phenomenon is called diffraction. As patterns approach the same order of magnitude as the wavelength of light, one must be concerned with the wavelike nature of light.

 

As we all know, when light rays from different parts of a slit combine on the distant wall after travelling an extra half-wavelength, they interfere destructively and produce a dark spot. The pattern produced by light shining through a single slit is a central bright spot, surrounded by dark/light/dark/light spots. The spots become fainter and less distinct the farther away from the center they are. The positions of dark spots on the wall can be determined from the equation

There are so many other considerations like registration, throughput etc. By registration one knows whether patterns can be repeatedly aligned one layer to another. It has been observed that within dimensions of ~ 1/3 of resolution one can position the patterns. What is the throughput of a particular lithography system? Can these be done in a cost effective time? 50-100 wafers an hour, down to 1 chip per hour are typical.

As far as the chemistry of resists concerned, they generally consist of 3 parts; the resin, the solvent and photoactive component. The Resin is a "plastic like" or "glue-like" compound that is solid in it is undiluted state. The solvent is for

dissolving the resin, allowing the resin to be applied in a liquid state. The Photoactive Compound (PAC) acts to inhibit or promote the dissolution of the resin in the developer. PAC inhibits dissolution in positive resists before light exposure. After exposure the PAC promotes dissolution of the resin.

Positive Photo Resists are most commonly used in the IC industry and they are superior to Negative Photo Resists because they do not swell during development, they are capable of finer resolution and reasonably resistant to plasma processing operations. The negative photo resist has high sensitivity but low contrast; it adheres well to substrate and has good mechanical properties and resistance to chemicals and plasma etching. Since the negative resist swells during the development, the minimum feature size is limited to 2um. NPR is difficult to remove and its developers are usually less eco-friendly organic solvents.

A PR is characterized by its ability to distinguish between light and dark portions of a mask. How the contrast of a particular resist is is measured? To achieve high contrast, the chemical response to the irradiation must be highly nonlinear. The intensity profile of a photoresist exposed through a mask window is shown in Fig. 3.61. The corresponding contrast curves for ideal positive and negative is given in Fig. 3.62. In case of high contrast resists, sharpened regions are achieved instead of blurred regions close to the exposed areas. The slope of the exposure response is a measure of contrast.

Fig. 3.61 : The intensity profile of a photoresist exposed through a mask window

Fig. 3.62 : Contrast curves for ideal resists (a) PPR (b) NPR

In the case of PPR :

D100 = the minimum dose for which the photoresist will completely dissolve (harden in case of NPR) when developed. D0 as the maximum energy density for which the photoresist will not dissolve (harden in case of NPR) at all when developed.

Between these values, the photoresist will partially dissolve (harden in case of NPR). For PPR, the contrast is related to the rate of polymer chain scission (breakings) and the rate of change of solubility that is solvent dependent. For NPR, the contrast is related to the rate of polymer chain formation.

Image Reversal :

The resists used in microlithography today are virtually all positive tone. The masks can be made in either tone and thus get the image reversal. However, the image reversal process is specifically used to generate an undercut profile during lift-off.

Before discussing the image reversal, the Lift-off is discussed first. Suppose a particular metalized pattern is required on a wafer. One could deposit the metal film onto the wafer first, and then pattern the resist. If the metal could be etched, process flow for patterning of resist after metal deposition is shown in Fig. 3.63.

Fig. 3.63 : Process flow for etching a deposited metal

But suppose the metal cannot be etched, or only wet etched, which is not very precise for small features. The preferred technique is lift-off. In lift-off, the resist is patterned first, and then the metal is evaporated over the resist. The resist is then dissolved away in a solvent, carrying the unwanted metal with it. However, the normal positive resist profile presents a problem of sidewall slope as shown in Fig. 3. 64.

Fig. 3.64: The sidewall profile in the case of lift off

After evaporation, the metal would form a continuous film and if the resist were removed, the edges of the metal film would tear, or the whole pattern could be torn away. The solution lies in the use of image reversal to create an undercut profile. The process flow is shown in Fig. 3.65.

Fig. 3.65 : Process flow in the case of image reversed lift off

In this technique, instead of exposing the feature where the metal is remaining, one exposes around the feature using a negative rather than a positive mask. After reversal, the sidewall slope that worked against forms the undercut profile, which is favorable for lift-off. When the metal is evaporated, the film is discontinuous over the desired features. Now the resist can be removed cleanly, leaving a well-defined metallization pattern behind. A good rule of thumb is to use a resist layer at least three times the thickness of the metal desired.

Image reversal is accomplished in two ways: using a special Vacuum Oven or by using a special photoresist of the AZ 5200 series. The oven method takes longer, but produces superior and more consistent results. The AZ resist is faster and suitable for large feature sizes.

In the oven process, the wafers are placed in the oven after exposure, where an ammonia diffusion bake takes place. The ammonia diffuses into the resist, where it binds to the indene carboxylic acid that has been generated in the exposed areas. The exposed areas are now rendered insoluble, while the unexposed areas are not affected by the ammonia. Following the bake, a flood exposure is performed to expose the previously unexposed areas. This is shown schematically in Fig. 3.66.

 

Fig. 3.66 : The sidewall profile in the case of image reversed lift off

The photoresists of the AZ 5200 series activates an amine that is already present in the resist. This amine bonds to the photogenerated acid, just as the ammonia does in the Oven. A flood exposure and development follows.

Fabrication of Masks :

Optical lithography requires the fabrication of a mask. Masks are glasses coated with a film in which the pattern is formed. Generally two types of masks are formed; resist-coated chrome masks and emulsion coated glasses. In the first one a layer of sputtered Cr about 100 nm thick coats the glass plate. Resist is then spun on the plate, and the exposure is made. After development, the Cr is removed from the unprotected areas with an acid etch, and an image of the pattern is left in the Cr. The exposure can be made with either an optical or an e-beam tool.

In the case of emulsion mask, a layer of high-resolution photographic emulsion coats the glass plate. Optical exposure and development causes parts of the emulsion to become opaque, forming an image of the pattern. These types of masks are inexpensive to make, but have poor resolution and are not nearly as robust as Cr masks.

There are two considerations of the glass out of which the mask is made; the thermal expansion of the glass and its transmission at the exposure wavelength. Thermal coefficients for different types of soda-lime, borosilicate and quartz glass are 9.3 ppm/°C, 3.7 ppm/°C and 0.5 ppm/°C respectively. The worst case here is soda-lime glass, which gives a 1.2 change across a 5 inch mask for every 1°C variation in temperature, but we still use soda-lime in most cases because it is much cheaper. Thermal effects can be limited by using a temperature compensated environmental chambers. Borosilicate glass is usually used for masks made on e-beam tools. Since the masks are exposed under vacuum, heat is not transferred as readily, so a lower expansion glass is desirable. These masks are about twice as expensive as soda-lime.

When the transmission properties of the various types of glasses are compared deep UV exposures require quartz instead of other types of glass, because glass begins to absorb strongly at wavelengths below about 350 nm. However, quartz masks are several times more expensive than glass.

Having examined all the basic process steps involved in the fabrication of Integrated Circuits, in the next major section

the fabrication procedure of passive components and devices will be discussed.

3.6 Basic CMOS Technology

The fabrication of a modern IC in the CMOS process involves hundreds of sequential steps and can last up to many days of processing time. In this section the basic fabrication steps involved to make transistors, interconnects, resistors and capacitors are discussed. The problem of latch up and ways in which it is avoided is taken up subsequently. The section concludes with some technology related computer aided design aspects like layout design rules. First the transistor process is considered.

In early days of technology, the control gate of the MOS transistor was made with aluminum instead of polycrystalline silicon. It was difficult to align the metal over the channel precisely; an offset in one direction or other would create a non-functioning of the transistor. To overcome these problems, the poly-silicon gate was introduced. This polysilicon would be deposited before source/drain diffusion. During the diffusion, source and drain regions are self-aligned with respect to the gate. This self-alignment structure reduces the device size. In addition, it eliminates the large overlap capacitance between gate and drain, while maintaining a continuous inversion layer between source and drain. In the case of metal gate process, Al deposition has to be carried out almost at the end of fabrication because further high temperature processing would melt Al. In case of self-aligned poly silicon gate technology, these restrictions are also circumvented.

Fig. 3.67 : Cross section of NMOS transistor in a self aligned Poly Silicon Gate Technology

A further improvement of this technique is the use of a low-doped drain (LDD) structure. As an example, we consider the structure shown in Fig 3.67. Here a first shallow implant is used to contact the inversion layer underneath the gate. The shallow implant causes only a small overlap between the gate and source/drain regions. After adding a sidewall to the gate a second deep implant is added to the first one. This deep implant has a low sheet resistance and adds a minimal series resistance. The combination of the two implants therefore yields a minimal overlap capacitance and low access resistance.

In CMOS ( Complementary Metal-Oxide Semiconductor ) technology, both N-type and P-type transistors are used to realize logic functions. Today, CMOS technology is the dominant semiconductor technology for microprocessors, memories and application specific integrated circuits (ASICs). The main advantage of CMOS over NMOS and bipolar technology is the much smaller power dissipation. Unlike NMOS or bipolar circuits, a

CMOS circuit has almost no static power dissipation. Power is only dissipated in case the circuit actually switches. This allows integrating many more CMOS gates on an IC than in NMOS or bipolar technology, resulting in much better performance.

3.6.1 Basic process steps of a self-aligned NMOS transistor

To fabricate an NMOS transistor one need to start with a lightly doped p-type Si wafer, <100>-oriented. The cross sectional view of the wafer after each process steps is presented in this discussion. The top view of the entire wafer would be circular however only a portion of the wafer with a rectangular shape is given in Fig. 3.68.

         Side View                                                        Top View

Fig. 3.68: Cross section of starting

wafer

The first step is to form the SiO2 layer by thermal oxidation. The cross section wafer after oxide growth is shown in Fig. 3.69. Typically the wafer thickness is about 500 and an oxide layer of few nm would not be visible if the dimensions are drawn as per scale. Therefore, for understanding the process concepts the following cross sections are not drawn to scale.

         Side View                                                        Top View

Fig. 3.69: Cross section view of

wafer after oxidation

A thin film of silicon nitride is deposited over the oxide using CVD and the cross section view of wafer after nitridation is given in Fig. 3.70. Following nitride deposition, positive photoresist applied as shown in Fig. 3.71.

          Side View                                                        Top View

Fig. 3.70: Cross section view of

wafer after nitride deposition

         Side View                                                        Top View

Fig. 3.71: Cross section view of wafer

after photo resist application

The PPR is patterned using active area mask and the silicon nitride layer is etched from regions unprotected by PPR. The resulting cross section view of wafer will be like in Fig.3.72.

         Side View                                                        Top View

Fig. 3.72 : Cross section wafer after

selective nitride etching

Boron channel stop implant is carried out. The regions not protected by nitride and PPR are covered during this implant. This implant avoids creation of possible inversion layers outside the channel regions under the field oxide. Introducing boron raises the impurity concentration in the substrate and thus the threshold voltage of FOX devices is made higher than for normal MOSFETs.

Photoresist is removed and field oxidation is carried out to grow a thick oxide. Layer of silicon dioxide under the polysilicon gate (which will be created later) is known as gate oxide. On the other hand, the oxide not directly under the gate of a transistor is known as field oxide. The field oxide provides isolation between adjacent transistors. Oxide is selectively grown in the regions unprotected by nitride as can be seen in Fig. 3.73. In this case larger oxide step is avoided compared to a situation where field oxide is grown over the entire surface and selectively etched to form the active region.

 

         Side View                                                        Top View

Fig. 3.73 : Cross section wafer after filed oxide growth

Silicon nitride layer is removed and threshold tailoring implant is carried out. Only in active region where the oxide thickness is less this implantation takes place and other areas are protected by thick field oxide. The change in

threshold voltage, where + is for p-dopant and – is for n-dopant.

         Side View                                                        Top View

Fig. 3.74 : Cross section view

after gate oxide growth

The existing oxide is removed from the active area and a very thin, high quality gate oxide is grown as shown in Fig. 3.74. This is followed by poly silicon deposition and patterning by lithography process using a poly mask. Cross section of wafer after polysilicon deposition and patterning is provided in Fig. 3.75.

         Side View                                                        Top View

Fig. 3.75 : Cross section of wafer after polysilicon deposition and

patterning

Now the n+ ion implantation is carried out to form source and drain areas. No lithography is needed for this step since the field oxide act as a mask against implantation and source and drain areas are self aligned to the gate. The resulting cross section is shown in Fig. 3.76.

         Side View                                                        Top View

Fig. 3.76 : Cross section wafer after filed oxide growth

The surface is non-planar now and it can make an impact on the next metal deposition step. The step coverage in this process is most critical (nonplanarity of the wafer surface). The non-planar surface is evened by CVD deposition of phosphosilicate glass (PSG) followed by a high temperature anneal to flow and smoothen the surface. Fig. 3.77 furnishes the cross section after PSG deposition.

         Side View                                                        Top View

Fig. 3.77 : Cross section wafer after filed oxide growth

Contact windows are created in PSG and silicide is formed in the contact openings followed by much thicker layer of metal deposition and patterning. The resulting view is presented in Fig. 3.78. Protective overcoat is deposited over the final layer of metallization to provide mechanical protection and to prevent contamination of the devices.

         Side View                                                        Top View

Fig. 3.78 : Cross section of wafer

after metal deposition and

patterning

The CMOS inverter is an important gate is the ICs. It consists of only two transistors, a pair of one N-type and one P-type transistor. There are again a large number of different CMOS technologies. For example, it is possible to start with an n-type substrate suitable for the p-MOSFET's and to create a sufficiently deep p-type region in areas where n-channel MOSFET's are required. This is known as a p-well technology. The opposite choice of a p-type substrate and creation of an n-well is also possible. In the next section a basic n–well CMOS process flow is described.

 

3.6.2 Basic n–well CMOS process

In a standard n-well process, one of the first things made is the n-well in a p type substrate. Once the n-well is created as shown in Fig. 3.79, the active areas can be defined. The MOSFET is build within this active area. As discussed in the previous section, a very thin layer of silicon dioxide is grown on the surface. This will be used to insulate the gate from the surface. The thin layer of SiO2 is grown and covered with Si3N4 as shown in Fig. 3.80. This will act as a mask during the subsequent channel stop implant and field oxide growth. The channel stop implant is to prevent conduction between unrelated transistor source/drains. A thick additional layer oxide grows in both directions vertically where Si3N4 is absent. The field oxide provides isolation between transistors. A threshold adjustment implant to balance off the threshold voltage differences would be the next process step. The P-MOS results in a higher threshold voltage level than nMOS with normal doping concentrations. With additional negative charges buried inside the channel, VT for pMOS could be controlled.

Fig 3.79 : Formation of n-well

Fig. 3.80 : Gate oxide covered with silicon nitride in the active areas

Polysilicon deposition is carried out and gate definition is then completed using the mask shown in Fig. 3.81. After this step the cross section will be as in Fig. 3.82. Note that the connection between two gate inputs in a CMOS inverter is achieved using the poly silicon. The source and drain diffusions for pMOS is carried out using p-type diffusion. Boron is the most popular element used for this step. Similarly, source and drain diffusions for nMOS is carried out using n-type diffusion. Phosphorous and Arsenic can both be used for this step. The resulting cross section is given in Fig. 3.83. Additional oxide is created, and then the contact holes are cut in the oxide down to the diffusions and polysilicon. These contacts can be filled by metal permitted to flow into the holes. The drains of pMOS and nMOS transistors are connected by a metal line in order to take the output from the CMOS inverter. The final cross sectional diagram of the inverter is shown in Fig. 3.84.

Fig. 3.81 : Top view of Poly silicon mask

Fig. 3.82: Poly silicon gate definition is completed

Fig. 3.83 : Transistor source/drain diffusion is completed

Fig. 3.84 : Cross section of a CMOS inverter in an n-well process

3.6.3 P-well process

Prior to the n-well process p-well process was popular. P-well process is preferred in circumstances where balanced

characteristics of the nMOS and pMOS are needed. It has been observed that the transistors in the native substrate tend to have better characteristics than that was made in a well. Because p devices inherently have lower gain than devices, n well process amplifies this difference while a p-well process moderates the difference. The standard p-well process steps are is similar to n-well process, except that a p-well is implanted instead of an n-well as a first step. Once the p-well is created, the active areas and subsequently poly gates can be defined. Later diffusions can be carried out to create source and drain regions. Finally, metal is deposited and patterned for contacts.

3.6.4 Twin-Tub process

It is also possible to create both a p-well and an n-well for the n-MOSFET's and p-MOSFET respectively in the twin well or twin tub technology. Such a choice means that the process is independent of the dopant type of the starting substrate (provided it is only lightly doped). A simplified sketch of twin-well CMOS process cross section is given in Fig. 3.85. The process steps of individual n-well process p-well process were already discussed above and is not repeated here.

Fig. 3.85 : A simplified sketch of twin-well CMOS process cross section

3.6.5 Silicon-on-Insulator process

Silicon-on-Insulator (SOI) has been under active consideration for the last many years. SOI refers to placing a thin layer of silicon on top of an insulator such as silicon oxide or glass. The transistors would then be built on top of this thin layer of SOI. The basic idea is that the SOI layer will reduce the capacitance of the switch, so it will operate faster.

Thin Layer of Silicon

SiO2 or Al2O3(sapphire)

Fig. 3.86 : A SOI cross section

One of the areas that can store charge in a MOS switch is the silicon substrate itself. Since an insulator act as a substrate, the junction capacitance will be eliminated and the MOS transistor will operate faster. The body effect problems and latch up problems are eliminated in SOI. One of the first early applications of SOI has been in memories for space application; since the memories built on SOI were perceived to be more resistant to soft error rate. Soft error rate refers to upset of data in the memory by cosmic rays and background radioactive material. Due to the absence of wells, a closer transistor packing can be achieved in SOI. The major disadvantages of SOI are that it presents lower gains and higher cost. Protecting diodes at inputs cannot be realized in SOI due to absence of silicon substrates.

3.7 CMOS Process Enhancements

Apart from making transistors a number of developments may be added to CMOS processes primarily to increase the connectability, provide high quality capacitors for analog circuits and memories or provide resistors with variable specifications.

3.7.1 Interconnects

Probably the most important add-ons for CMOS logic processes are additional signal and power routing layers. This greatly simplifies the routing of logic signals between modules and improves the power and clock distribution to modules. Improved routability is achieved through additional layers of metal or by improving the existing polysilicon interconnecting layer.

The connections between transistors are primarily done using a metal such as aluminum or copper and these wires are known as interconnects. In the early generations of MOS technology, only one or two metal layers were available. Presently the transistor density has increased tremendously and the number of layers of interconnect is gone over ten layers. The fabrication of interconnect begins with the first metal layer and that is used to make contact with transistor source, drain and gate terminals and to connect them to nearby VDD , ground and input/output of other transistors.

The different levels of metals are connected to each other using contacts or vias. Generally speaking contacts are used to connect wires to transistors while vias are used to connect one metal layer to another. Typically upper layers of metal are used for global signals, clock and power distribution and must carry large amounts of currents. The cross sections are made relatively large to keep the resistance levels low. The lower levels are intended for block level and cell level routing and are kept small for high density. One problem in fabricating multi layer interconnects is that, as layers are placed one over another the surface becomes uneven and this may lead to stresses and strains in structure. Before a new layer of metal is placed on the chip, the surface must be planarized to avoid this problem. In the past aluminum was used for the metal layers and tungsten was used to implement vias. Due to increase in resistance and electro migration problems copper is introduced to replace aluminum. Unfortunately, copper diffuses rapidly in silicon and typically a thin copper cladding material such as titanium nitrate is used to surround copper to prevent diffusing into SiO2 .

3.7.2 Circuit Elements

In this section we describe the passive components such as resistors and capacitors and non-volatile R/W memory.

Resistors in CMOS Technology

Resistors include diffused, polysilicon and well resistors. The diffused layer that used to form the source and drain of MOS devices can be used to form a diffused resistor. Similarly the polysilicon required in silicon gate MOS technology can be used to form resistors. The nominal sheet resistance is in the order of 20 / Ž to 80 / Ž . To reduce the sheet resistance a silicide layer is deposited on the top of the polysilicon. The well region in the CMOS technologies can also be used as resistors. It is relatively lightly doped region and this resistor provides a sheet resistance of the order of 10k

/ Ž . The MOS transistor biased in the triode region can be used in many circuits to perform the function of a resistor. In the drain-source resistance calculated by differentiating the drain current in the triode region with respect to the drain-source voltage.

The principal disadvantage of this form of resistor is its non-linearity. That is the resistance is not constant, but depends on the drain-source voltage

Capacitors in CMOS technology

Capacitors in CMOS technology include poly-poly, metal-poly, silicon-silicon and vertical and lateral metal-metal. Many MOS technologies that are used to implement analog functions have two layers of poly silicon. The additional second layer can be used to provide an efficient capacitor structure, an extra layer of inter connect, and also to implement floating gate memory cells that are electrically programmable and optically erasable with UV light. An important aspect of the capacitor structure is the parasitic capacitance associated with each plate. The largest parasitic capacitance exist from the bottom plate to the under lined layer, which could be either the substrate or a well diffusion. This bottom plate parasitic capacitance is typically 10 to 30 % of the capacitor itself.

MOS transistor itself can be used as a capacitor when biased in the triode region, the gate forming one plate and the source, drain and the channel forming another. In the processes with only one layer of poly silicon, alternative structures must be used to implement capacitive elements. One approach involves the insertion of an extra mass to reduce the thickness of the oxide on top of the poly silicon layer so that when the interconnect metallization is applied, a capacitor is formed.

Capacitors can also be constructed using the metal and poly layers with standard oxide thicknesses between layers. A key disadvantage of such structures is that capacitance per unit area is small because of thicker oxide. To reduce the capacitor area and to avoid the extra processing steps lateral capacitor structures can be used. A lateral capacitor can be formed in one layer of metal by separating one plate from another by spacing. Such lateral capacitor can be used in conjunction with vertical capacitors.

We have already discussed about the devices such as pMOS and nMOS, circuits like CMOS inverter, interconnects and finally passive elements. In the next section we will take up latch up: a serious problem IC industry faced in their early stages.

3.7.3 Latch-up

Latch up stems from the parasitic bipolar transistors which are structurally inherent to bulk CMOS. These transistors can be activated in various ways and as CMOS technologies are scaled down, this variety grows. Under certain conditions the activated transistors can dominate the circuit behavior. However, with proper process and lay out design, CMOS chips can be operated without ever encountering latch up.

Physical origin

To have both n-channel and p-channel transistors, it is necessary to have both p and n type background material. Fig. 3.87 shows the cross sectional view of an inverter circuit in N-well CMOS process with parasitic bipolar transistors.

Fig. 3.87 : Cross section of a CMOS inverter with the possible parasitic bipolar transistors

As shown in figure, the p+ region of the p-transistor, the n-well and the p-substrates form a vertical parasitic pnp transistor Q1. When forward biased any P+ diffusion can serve as an emitter and inject holes into the n-well base. The reverse biased junction formed by the n-well and substrate then collects the unrecombined holes. The n-well, the p-substrate and the N+ source of the n-transistor forms another parasitic npn transistor Q2. In this case electrons are injected from an N+ diffusion into the substrate can be collected by the reverse biased n-well. There exist two resistors Rwell and Rsub due to the resistive drop in the well area and the substrate area. Q1 and Q2 form a semiconductor controlled rectifier (SCR), a PNPN circuit as shown in Fig.3.88. Positive gate current switches the device from high to low impedance, negative gate current from low to high. If Rwell and/or Rsub are not 0, and for some reason (e.g. power up, current spike etc), Q1 or Q2 are forced to conduct, VDD will be shorted to ground through the small resistances and the transistors. Once the circuit is 'fired', both transistors will remain conducting due to the voltage drop across Rwell and Rsub. The only way to get out of this mode is to turn the power off. This condition is known as latch-up.

Fig. 3.88 : Formation of SCR in a CMOS inverter

Triggering

Under normal operation the circuit performs as an inverter and the parasitic bipolar portion can be ignored. In particular, if the bipolar circuit switches from its normally high impedance state into its low impedance state, the power supply then sees PNPN's low impedance path to ground. Several conditions must obtain before the PNPN portion of the circuit can latch (switch to its low impedance state). They are

1. The loop gain of the PNPN configuration must exceed unity for the circuit to switch. That is, the transistors'

common-base current gains must satisfy or equivalently .2. A bias condition must exist such that both bipolars are turned on long enough for current through the blocking

junction to reach the level defined as switching current. Turn on is usually caused by externally excited current flow through one or both emitter/base bypass resistors.

3. The bias supply and associated circuits must be capable of supplying current at least equal to the switching current for the PNPN structure to leave the blocking state and at least equal to the holding current to reach the latched state.

Prevention techniques

We now turn to CMOS design techniques to prevent latch up. They divide into two categories such as lay out guidelines and process guidelines. Guard structures, multiple well contacts, substrate contact rings and butted source contacts are some of layout precautions a CMOS designer can adopt to avoid latch up. Guard ring structures have been used for many years to decouple one parasitic bipolar from another. These guards are used to collect injected minority carriers before they can cause a problem. A minority carrier guard ring can be an additional well diffusion e.g. n+ rings is placed between a parasitic emitter and the n-well as shown in Fig. 3.89. It collects some electrons and remaining electrons only reach the n-well. The guard rings could be deeper surrounding the n type parasitic emitter and such a configuration virtually eliminates electron current flow to the well. The guard rings should not be opposite type source/drain diffusion so that the guard ring itself does not contain parasitic transistors.

Fig. 3.89 : Latch up prevention by guard ring

Since majority carrier currents flowing through the well are accompanied by voltage drops that can cause the vertical parasitic transistor to turn on, designer should limit the resistance along these ohmic paths. This can be accomplished by providing multiple well contacts to the well using metal lines. Source/drain diffusion by itself provides a sheet resistance at least two orders of magnitude lower than the well's, and its sheet resistance can be lowered still further by frequent contacting with a metal line.

Although the highly doped substrate in an epi-CMOS technology is an effective ground for a back side wafer contact, careful design is required to achieve its full benefit for a low resistance topside substrate contact. A square topside substrate contact with an edge dimension compared to the epi-layer thickness can add kilo ohms of series resistance to the substrate path. Consequently, topside substrate contacts should have larger areas. One means of satisfying this requirement and providing maximum dispersal of substrate current is to place a substrate contact ring around the edge of the chip. Such a ring can reduce the lateral bypass resistance below 1 ohm.

Metal connecting contiguous n and p diffusions across their metallurgical junction, forms a butted contact. Such a contact can be used to minimize the emitter/base bypass resistances of a parasitic bipolar.

Process techniques for controlling latch up divide into two categories-bipolar spoiling and bipolar decoupling. One of the earliest techniques of bipolar spoiling was doping silicon with gold or neutron irradiation to reduce the base minority carrier life time. Another method of spoiling the gain of the vertical parasitic bipolar is to build into the base a retarding electric field to impede base transport. This can be achieved by using a retrograde well, i.e. doping increases in going downward from emitter to collector. Still another technique of bipolar spoiling is the use of schottky barrier source/drains and thus reducing the emitter injection efficiency.

Bipolar decoupling has proved more effective and easier to implement than bipolar spoiling. Several methods are possible. A highly doped substrate beneath a lightly doped epi-layer very effectively shunts the lateral parasitic bipolar. Reverse bias on the substrate (or well) raises the bypass current needed to turn on corresponding bipolar.

3.8 Technology-related CAD issues

The processes are becoming more and more complex and it may not be practical for the designer to catch up the implications of process like a fabrication engineer. The goal of defining a set of design rules is to allow for a ready translation of circuit concept into actual geometry in silicon. As the layout of an integrated circuit is being prepared, these layout rules must be observed in order to ensure that the integrated circuit is manufacturable. Rules regarding layout dimensions arise, in part, from the fact that at each mask step in the process, features of the next photo mask must be aligned to features previously defined on the integrated circuit. Even when using precision automatic alignment tools, there is still some error in alignment. In some cases, alignment of two layers is critical to circuit operation. As a result, alignment tolerances impose a limitation of feature size and orientation with respect to other layers on the circuit.

Electrical performance requirements also dictate feature size and orientation with respect to other layers. An example of this is the allowable distance between diffusions supporting a given voltage difference. Understanding the rules associated with electrical performance is most important to the designer if circuits are to be designed that challenge the limits of the technology. The limits for these rules are constrained by the process conditions. Consider the example of wire spacing; a designer wants wires close together that have denser layout. The fabrication process may not be accurate to draw wires too close together. A general set of standard rules for many processes is usually good enough. MOSIS is one of the economically viable integrated circuit fabrication services where one can purchase prototype and small-volume production quantities of integrated circuits. MOSIS Scalable CMOS (SCMOS) is a set of logical layers together with their design rules, which provide a nearly process and metric independent interface to all CMOS fabrication processes available through MOSIS. The designer works in the abstract SCMOS layers and metric unit ("lambda"; not to be confused with the channel length modulation parameter ). Designer then specifies which process and feature size he wants the design to be fabricated. MOSIS maps the SCMOS design onto that process, generating the true logical layers and absolute dimensions required by the process vendor. The designer can often submit exactly the same design, but to a different fabrication process or feature size. MOSIS alone handles the new mapping. All lengths in the layout are in terms of multiples of 's. For example, minimum transistor length is 2 , minimum wire spacing is 3 , etc. The actual value of can be chosen later depending on the target technology (typically, feature size is 2 ).

The masks are actually the interface between a semiconductor manufacturer and the chip designer. In design of a working chip, one should make sure that the mask is prepared according to specific geometric design rules. In addition, interrelationship ship between masks must be ensured to result the correct interconnected set of circuit elements. CAD tools are used to check these two requirements and Magic is a very old layout tool released from Berkeley in 1986. Magic is extraordinarily powerful, and today is still quite capable of large-scale designs, either analog or digital. Magic is available in public domain and recent updates to Magic keep its features on par with "industry standard" layout tools. Other industry standard layout tools come from Mentor Graphics, Cadence, and from in-house CAD groups (e.g. Intel and DEC). Magic is an interactive system for creating and modifying VLSI circuit layouts. One uses a color graphics display of basic cells and can combine them hierarchically into larger structures. The Magic understands about the nature of circuits and uses this information to provide additional operations. For example, Magic has built-in knowledge of layout rules; as one is editing, it continuously checks for rule violations. Magic also knows about connectivity and transistors, and contains a built-in hierarchical circuit extractor. Magic also has a plow operation that one can use to stretch or compact cells. Lastly, Magic has routing tools to make the global interconnections in the circuits.

The only layers the designer needs to use are:

ndiff, pdiff, nwell ndc, pdc, nwc, pwc, poly

nfet, pfet, m1, m2, via

Magic will automatically convert these paint layers to mask layers when it does CIF generation. By restricting the

designer to using these designated layers (called design paint layers), Magic minimizes the trouble into which the designer can get. Magic allows faster Incremental Design Rule Checking (Incremental DRC), Extraction and CIF Generation. All three of these tasks are controlled by the technology file. The technology file is a set of rules that specify the fab technology. The MOSIS fab uses "Scalable CMOS" (SCMOS) tech rules and the highlights are given in Table 11.

Table 11 : Highlights of based S calable CMOS (SCMOS) technology rules

LAYER WIDTH SPACE poly 2 3Diff 3 3

metal1 3 3metal2 3 4nwell 10 9 cut 2 2via 2 3

To verify the layout, Magic creates an .ext netlist containing transistors and capacitors. This can then be incorporated into Spice or sim netlists. All values (cap per area for each layer) are defined in the techfile, so one need to specify for which process you are extracting. The most important characteristic of the SCMOS technology is that it is flavor-less and scalable: layouts designed using the SCMOS rules may be fabricated in either N-well or P-well technology at a variety of feature sizes. The lambda units used in Magic are dimensionless and can be scaled to dimensions such as 0.6 microns/lambda, 1.0 microns/lambda, 1.5 microns/lambda, etc. In order for SCMOS designs to be fabricated with either N-well or P-well technology, both p-well and n-well contacts must be placed, and where wells and rings are specified explicitly (e.g. in pads) both flavors must be specified. When the circuit is fabricated, one of the flavors of wells, rings, and substrate contacts will be ignored. The SCMOS technology provides two levels of metal. All contacts are to first-level metal.

In most cases design rules are unique to each wafer manufacturer. Rules change from fab to fab, process to process.  The design rules for the particular wafer manufacturer should be obtained before the design is begun and consulted during the design. This is especially important in the design of state-of-the-art analog CMOS. However, the principles developed here should remain unaltered while translated to specific processes.

Fig. 3.90: (a) CMOS inverter circuit

Fig. 3.90 (b) : CMOS inverter magic layout

Fig. 3.90 (c) : CMOS inverter cross sectional view

The development of a CMOS inverter the circuit from circuit design, circuit layout and a fabricated cross-sectional point of view is shown in Fig 3.90. The formation of the various levels which make up the finished CMOS inverter has already been discussed in previous sections. A circuit designer sees things from above, and only worries about the placement of transistors, and how they will be connected together. In fact, the only factor in the actual design of the layout engineer has any choice on is the transistor width, W. All other parameters are decided before hand by the process engineer.