Chap. IV –CMOS Operational Amplifiers · EEL 6713 - Analog Integrated Circuit Design 3 IV.1...

EEL 6713 - Analog Integrated Circuit Design 1

n IV.1 Introduction

n IV.2 Performance parameters

n IV.3 OTA (single-stage op amp)

n IV.4 Cascode and folded-cascode amplifiers

n IV.5 Cascade amplifiers

n IV.6 Fully-differential amplifiers and common-modefeedback

Chap. IV –CMOS Operational Amplifiers


IV.1 IntroductionThe ideal op amp

+

vi

-

+

-

+Avi-

RS

+vo-

A→∞RS=0

+

vi

-

+

-

Gmvi GS +vo-

Gm=AGS


IV.1 Introduction

2 2

1 12

1

11 1

11 1

o

i

v R Rv R RR

A R

= + ≅ + + +

Applications of op amps - 1

+vi-

-

+

R2

R1 +vo-

Inverting amplifier

2 2

1 12

1

11

1 1

o

i

v R Rv R RR

A R

= − ≅ −

+ +

-

+

R2

R1

+vi-

+vo-

Noninverting amplifier


IV.1 IntroductionApplications of op amps - 2

Transimpedance amplifier

2 2 2

11

1ov A

R R Ri A A

= − ≅ − − ≅ − +

-

+

R2

i +vo-

- Continuous-time filters- SC filters- D/A & A/D converters- Sensor signal conditioning- Voltage & current references- Comparators- Nonlinear analog functions,- .......


IV.1 Introduction

P. Allen and D. Holberg – CMOS Analog CircuitDesign, 2nd. Ed., Oxford, New York, 2002.

Op amp design:•Choice of architecture;•Bias currents &Transistors dimensions;•Compensation;•Simulation;•Layout;•Post-layout simulation

Op amp requirements:•Technology;•Supply voltage;•Gain, GBW, output swing,noise, offset voltage, PSRR, ICMR, ....


IV.2 Performance parameters - 1

W.-C. S. Wu et al., Digital-Compatible High-Performance Operational Amplifier with Rail-to-Rail Input and Output Ranges, IEEE JSSC, vol. 29, no. 1, pp. 63-66, Jan. 1994.

Gate channel capacitances are used for compensation capacitors.



L. Moldovan and H. H. Li, A Rail-to-Rail, Constant Gain, Buffered Op-Amp for Real Time Video Applications, IEEE JSSC, vol. 32, no. 2, pp. 169-176, Feb. 1997

Op Amp fabricated by MOSIS service in 2-µm, n-well CMOS, DPDM



J. F. Duque-Carrillo et al., 1-V Rail-to-Rail Operational Amplifiers in Standard CMOS Technology, IEEE JSSC, vol. 35, no. 1, pp. 33-44, Jan. 1990



Vid(mV)

Vod(V)

VOS

Offset voltage

Systematic offset – results from circuit design and is present even when all supposedly identical devices are matched (usually can be set to a low value).

Random offset – results from mismatches in supposedly identical pairs ofdevices (depends on area and bias).

P. R. Gray and R. G. Meyer, MOS Operational Amplifier Design – A Tutorial Overview, IEEE JSSC, vo. 17, n0. 6, pp. 969-982, Dec. 1982.



P. R. Gray and R. G. Meyer, MOS Operational Amplifier Design – A Tutorial Overview, IEEE JSSC, vo. 17, n0. 6, pp. 969-982, Dec. 1982.

Differential voltage gain

d dBA

Extrapolated unity-gain frequency

1p−0 dB



P. Allen and D. Holberg – CMOS Analog Circuit Design, 2nd. Ed., Oxford, New York, 2002.

Settling time



CMRR, PSRR, Slew rate, Noise, Common-Mode Input Range, Output Swing, Power, Silicon Real State, ....

Dynamic Range (DR)

,max

,min

20log in

in

vDR

v

=

Noise (distinguish between signal and noise)

Distortion (within acceptable level: application-dependent).


IV.3 OTA (single-stage op amp) - 1Or current-mirror op amp (Johns & Martin) /symmetric OTA (Laker & Sansen)

VSS

IT

+vG1-

M1 M2

I1 I2

+vG2-

1:B CM 1:B CM

1:1 CM

CL

BI1 BI2

BI1

Io= B(I2-I1)


IV.3 OTA (single-stage op amp) - 2

K. Laker and W. Sansen: Design ofAnalog Integrated Circuits and Systems, McGraw-Hill, 1994

Fig. AP6-1

Bias circuitry Cascode outputLow-gain diff. amp.


IV.3 OTA (single-stage op amp) - 3

D. Johns and K. Martin, Analog Integrated Circuit Design, Wiley, 1997.


IV.3 OTA (single-stage op amp) - 4Input common-mode range: see diff. amp.

( )T

L P

BISR

C C=

+

1 2id g gv v v= −

CL+CP1m idBg v−oR

+vo

-

( ) ( )1

1m o

do L P

Bg RA s

sR C C=

+ +

( )11

( )2

m

L P

BgGBW Hz

C Cπ=

+

Io= B(I2-I1)

VSS

IT

+vG1-

M1 M2

I1 I2

+vG2-

1:B CM 1:B CM

1:1 CM

BI1 BI2

BI1CL

CM delays were neglected

asymmetry


IV.4 Cascode & folded-cascode amplifiers - 1

Telescopic diff. amp. with self-biased cascode CM

Telescopic diff. amp. with high-swing cascode CM

- Reduced output swing;

-Doublet !

- Not applicable to low supply voltage.



D. Johns and K. Martin, Analog Integrated Circuit Design, Wiley, 1997.

Low-gain diff. amp. High-gain diff. amp.



P.R. Gray, P.J. Hurst, S.H. Lewis, andR.G. Meyer, Analysis and Design ofAnalog Integrated Circuits, 4th. Ed.,Wiley, 2001.



IT

IT/2

IT

IT/2

IT/2IT/2

IT∆i ∆i∆i

∆i

∆i2∆i

P.R. Gray, P.J. Hurst, S.H. Lewis, and R.G. Meyer, Analysis and Design of Analog Integrated Circuits, 4th. Ed., Wiley, 2001.

Can be changed toincrease positive output swing

Folded-cascode amplifier - 1



0

01d

dL

AA

sC R≅

+


Folded-cascode amplifier - 2ICMR : Exercise

Output swing : ExerciseNote: The output swing can be around

-VSS+2VDSsatp to VDD-2VSDsatp for high-

swing current mirror and optimized bias.Ro

T

L

ISR

C± = ±

0d m oA G R=

& doublet

1m mG g=

( )

44

4

212 2

2

1 ds Ao ds

o ms A

ds Ads ds

ms A

gG g

R g

gg g

g

= =

+ +High-swing current mirror



K. Bult & G.J.G.M. Geelen, A fast-settling CMOS opamp for SC circuits with 90-dB DC gain, IEEE JSSC, no.6, pp. 1379-1384, Dec. 1990.

The gain-boost technique - 1

Stacked devices reduce output swing.Cascade amplifiers: stability?

1 22

2 2

2 1 2 1

1 1ds ds

mg ddmg dd mg

ods ds ds ds

g gg n A

g A gR

g g g g

++ +

= ≅


IV.4 Cascode & folded-cascode amplifiers - 7The gain-boost technique - 2



IV.4 Cascode & folded-cascode amplifiers - 8The gain-boost technique - 3



IV.5 Cascade amplifiersTwo-stage amplifiers - 1

ICMR: see diff. amp.VDD

Output swing:

4 5DD DSsat o SS DSsatV V V V V− > > +

Low-voltage gain:

1 6

2 2 6 7

o m mdo

i ds ds ds dsLF

v g gA

v g g g g= = −

+ +

CL

VSS

M4M3

M1 M2

M8 M5

M7

M6

IT vi

+

-

CC

vo

1:1 1:B

1:1 1:2B

inv noninv

For systematic offset → 0. “Early” effect at the output

1:2B


IV.5 Cascade amplifiers

( )1

2 12 1

o x o o To C C

C

o o o oo o L

L

d v v dv dv II C C

dt dt dt C

dv dv I II I C

dt dt C

−= ≅ → =

−= + → =

Two-stage amplifiers - 2CC

CL

voGmI -AdII

Io1

Io2

vi

+

-

vx

T

C

ISR

C± = ±

6max ( 1) Bext

L

I B ISR SR

C+ +− +

≅ >

( 1) Text

L

B ISR

C− −

= −The output node can be the SR limiting node*

*For a discussion, see Laker & Sansen, pp. 510-512


IV.5 Cascade amplifiers

0 0max

; sin ; o oo

dv dvSR v A t A SR

dt dtω ω≤ = = ≤

Two-stage amplifiers - 3Amplitude x frequency limitation due to SR

J. Dostál, Operational Amplifiers, 2nd. Ed., Butterworth-Heinemann, Boston, 1993.

Amplitude limitation

SR-limited slope



( ) ( )( ) ( )1

=+

o

in

A sVs

V A s F s

Determines the poles ofthe closed-loop system

Allen & Holberg, 1st ed.



x x x x1

I IR C−

1

II IIR C− 1p2p

jω

σ

s-plane

The op amp design must take into account both load and feedback loop

φM




Response of second order system with various phase margins




Equivalent differential circuit

+

vin

-

RIgmIvinCI

+

vI

-

gmIIvIRII CII

+

vo

-

CC

1mI mg g=

( ) 12 4

2 4 6 6

I ds ds

I db db gb gs

R g g

C C C C C

−= +

= + + +

6mII mg g=

( ) 16 7

6 7

II ds ds

II db db L

R g g

C C C C

−= +

= + +

If CC→0, then

( ) ( ) ( )1 1o mI mII I II

in I I II II

V g g R Rs

V sR C sR C≅ −

+ +

Poles relatively close → phase margin can be low or even negative !!!

Exercise: Derive the transfer function Ad(s) of the compensated operational amplifier



( ) ( ) ( )( )( )

0

1 2

11 / 1 /

dod

in

A s zVA s s

V s p s p−

= = −− −

Compensated operational amplifier

0d mI mII I IIA g g R R=

( ) ( )1

1 1

I I C II II C mII I II c mII I II c

pR C C R C C g R R C g R R C

≅ − ≅ −+ + + +

( )2mII c

I II

mII

I I IC II

g Cp

C C C C CgC

−≅ − ≅+ +

mII

c

gz

C=

x x x x

s plane

pole splitting

mII

c

gz

C=1

I IR C−

1

II IIR C− 1p2p

jω

σ

Note: 0 12 /d mI CGBW A p g Cπ = =

/T CSR I C=( ) ( )/ 1 1

2 T mI t f

SRI g n i

GBWφ

π= = + +



x x

s-plane

mII

c

gz

C=

1p

2p

jω

σ

To avoid low phase margin,choose 2 , 2π>p z GBW

12π ≅ m

C

gGBW

C

1 1

2

2 2tan tan

2π π π

φ − − ≅ − − − M

GBW GBWp z

1 1

6 6

( / )

+ +

m I II C I II m

m C m

g C C C C C gg C g



Laker & Sansen’s book

Simplified model for noise analysis(input-referred noise current source not accounted for)

2 22

2 22

oI nId

oII nIIvII

v eA

f f

v eA

f f

=∆ ∆

=∆ ∆

Ad is the op amp voltage gain

AvII is the voltage gain relative to the second noise source. For the calculation, account for the output impedance of the first stage and compensation network)

2nIe

compensation

2nIIe

ov



NOTE: white noise onlyK. Laker and W. Sansen: Design ofAnalog Integrated Circuits and Systems, McGraw-Hill, 1994

Open-loop output noise of a Miller OTA

1st stage

2nd stageAvII

Ad



Two-stage CMOS op amp with a cascode current mirror load in the input stage


This connection reduces the feedforward current through Cwhen comparing to connectingC to node Y



P. Allen and D. Holberg – CMOSAnalog Circuit Design, 2nd. Ed., Oxford, New York, 2002.

CMOS two-stage op amp using nulling resistor compensation



CMOS two-stage op amp using nulling resistor compensation

P. Allen and D. Holberg – CMOSAnalog Circuit Design, 2nd. Ed., Oxford, New York, 2002.

1

1

mII I II c

pg R R C

≅ −

( )2mII c

I II

mII

I I IC II

g Cp

C C C C CgC

−≅ − ≅+ + ( )6

11/c z m

zC R g

= −−

3

1

z I

pR C

= −

Placing z on top of p2:6 6

11 c IIz

m c

c L

m c

CC

CR

g CC

gC +

= ≅

+

High-frequency pole

Determined by source/drain and gate voltages, and W/L


IV.5 Cascade amplifiersTwo-stage amplifier: design equations - 1

0 1 2

11

2 4

62

6 7

d d d

md

ds ds

md

ds ds

A A A

gA

g g

gA

g g

=

=+

=+

( )2mII c

I II

mII

I I IC II

g Cp

C C C C CgC

−≅ − ≅+ +

mII

c

gz

C=

0 12 /d mI CGBW A p g Cπ = =

/T CSR I C=

CL

VSS

M4M3

M1 M2

M8 M5

M7

M6

IT vi

+

-

CC

vo

1:1 1:B

1:1 1:2B

inv noninv

VDD


IV.5 Cascade amplifiersTwo-stage amplifier: design equations - 2

7 7SS DSsat o DD DSsatV V V V V− + < < −

max

min

ICM

ICM

V

V

=

=See diff. amp.

CMRR, noise (white & 1/f), PSRR±, (random) offset voltage,

CL

VSS

M4M3

M1 M2

M8 M5

M7

M6

IT vi

+

-

CC

vo

1:1 1:B

1:1 1:2B

inv noninv

VDD

Chap. IV –CMOS Operational Amplifiers · EEL 6713 - Analog Integrated Circuit Design 3 IV.1...

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Transcript of Chap. IV –CMOS Operational Amplifiers · EEL 6713 - Analog Integrated Circuit Design 3 IV.1...