Challenges in Hardware Logic Verification
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Challenges in Hardware Logic Verification
Bruce WileIBM Server Group Verification Lead
10/25/01
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Agenda
Five Challenges in VerificationFuture Verification Trends
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5 Challenges in Verification
1. Better use of available simulation cycles
Server Farm(Batch pool)
TestcaseGenerators + =
Billionsof Simcycles
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5 Challenges in Verification
1. Better use of available simulation cycles
Use coverage metrics to increase
new path testing.
Bug discovery rate
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5 Challenges in Verification
2. Specification methodology
ack will come on after the bias signal, followed in two cycles by the
State Machines
NOT MY
Timing diagrams
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5 Challenges in Verification
2. Specification methodology
LogicDescription
Simulation
Formal VerificationModel Checking
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5 Challenges in Verification
3. Power verification
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5 Challenges in Verification
3. Power verification
Turn off units when not in use
Verify "not in use" and no clocking
Function Check
Low power micro- arch design anddesign changes
Measure switching factor in chip and in "hot areas"
during sim and benchmarks.
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5 Challenges in Verification
4. Error path testing in self healing systems
Self-protecting
Self-healing
Self-configuring
Self-optimizing
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5 Challenges in Verification
4. Error path testing in self healing systems
For all of the legal paths for which the design must be verified, there's an order of magnitude more "illegal" paths.Verification must ensure that the hardware can:
Recover and continue, orTake itself off-line
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5 Challenges in Verification
5. Detecting System Deadlocks
I/O I/O I/O I/O
P P P P P P P P
Memory
P P P P P P P P
Memory
P P P P P P P P
Memory
P P P P P P P P
Memory
anyServerQueue
Interrupt
Buffer
When processor receives I/O interrupt it can't moveforward until buffer releases address X, but buffer can't move forward until interrupt is completed....
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5 Challenges in Verification
5. Detecting System Deadlocks
I/O I/O I/O I/O
P P P P P P P P
Memory
P P P P P P P P
Memory
P P P P P P P P
Memory
P P P P P P P P
Memory
anyServer
One solution: Abstract (hi-level) model using "Protocol" (Formal) verification to search for hangs
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5 Challenges in Verification
5. Choosing the right verification technology
Multiple technologies to choose from,But, few experts in all
Random Testcase GenFV Deterministic
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5 Challenges in Verification
5. Choosing the right verification technology
EducationExperience in the verification cycleStrong Verification career pathContinuing challenges
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Agenda
Five Challenges in VerificationFuture Verification Trends
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Future Verification Trends
Coverage Directed Testcase Generation
I-Stream Generator
BHT Control Logic and BHT Array (Design
under Test)
Instruction Unit and
Pipe Behavioral(checking
and Driving
BHT Array Loader
BHT Array Shadow
(Checking)
Automatic modification of random parameters based on observed coverage
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Future Verification Trends
Integration of Simulation with Formal Verification
LogicDescription
Simulation
Formal VerificationModel Checking
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Future Verification Trends
Integration of Simulation with Formal Verification
Integration control
LogicDescription
Simulation
Formal VerificationModel Checking
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Future Verification Trends
Sharing of verification I.P.
I/O I/O I/O I/O
P P P P P P P P
Memory
P P P P P P P P
Memory
P P P P P P P P
Memory
P P P P P P P P
Memory
anyServerFPU
InfiniBand
Bus Architecture
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Future Verification Trends
Sharing of verification I.P.
SOC Design will lead sharing of Verification IPComponents come from multiple sourcesNeed to supply verification IPNeed to have standard backplaneNeed standard constructs