CFP Management Interface - CFP Multi-Source...

CFP Management Interface Specification April 14, 2009 Version 1.0 _________________________________________________________________________

Copyright © 2008-2009 CFP MSA of 72

CFP Management Interface

100/40 Gigabit Transceiver Package Multi-Source Agreement

Draft 1.0

April 14, 2009



MSA Group Contacts

Document Editor Jiashu Chen [email protected]

Finisar Chris Cole [email protected] Opnext Matt Traverso [email protected] Sumitomo Eddie Tsumura [email protected]

Reference Documents

1. IEEE Standard 802.3-2002, Clause 45 2. IEEE Standard P802.3ba, Draft 2.0 3. XENPAK MSA Issue 3.0 4. XFP Specification Rev. 4.5 5. CFP MSA: I2C Protocol Draft 6. CFP MSA Hardware Specification

Change/Enhancement Proposals for Rev 1.1 Release

Current Draft Date Topics under Review or Consideration 1.0 April 14, 2009 - Both Ch n TX Alarm and Ch n RX Alarm flag registers (and associated

latch and enable registers) in Table 10 are subject to revision. - Add a software force input to the OR gate in Fig. 9 by using bit 0 of

register A01Dh, currently allocated for “Init_Complete” which is regarded as redundant.

- Replace the term “Optical Channel” with “Network Lane” and “Electrical Channel” with “Host Lane” throughout this document.

- Create CFP NVR Table 3 for storing BOL data for each network lane, moving from Channel Specific DDM Register Tables.

- Need definitions around PRBS testing (e.g., lane to lane orientation, host/network orientation etc.) which is called out in the control registers.

- Need to document lane mapping, for example, a serial optical lane implementation would use lane 0; a 4 network lane PMD would use lanes 0~3 etc.

- Further content consistency, doc format, and language improvement. - Elaborate the allocation of channels, for example, which channel tables

are allocated 40GE product, 0,1,2,3 or 4,5,6,7. - Need to add CFP Management Interface MSA revision number next to

8068h.



Revision History

Revision Date Objectives/Changes By External NDA Draft 0.1 12/23/2008 Initial release work in progress Jiashu

Chen External NDA Draft 0.2 01/26/2009 2nd release. Added contents Jiashu

Chen External NDA Draft 0.3 02/19/2009 3rd release.

- Removed the Detail forms for each individual register and replaced them with 3 collective Register details form,

- Replaced the original states definition with Rev7 content

- Addressed 1st round review comments with massive over all changes.

Jiashu Chen

External NDA Draft 0.4E 04/03/2009 4th release. - Added all the known required registers. - Changed the minimum size of register

section to 128 addresses and call it table. - Divided CFP NVR into 2 tables, NVR1 and 2. - All the register table contents had changes.

CFP NVR 1 and DDM tables had the most changes.

- Added Alarm/Status signal aggregation diagram and discussion.

- Transferred all the pin hardware related discussions to CFP MSA HARDWARE SPECIFICATION including the spec for MDIO pins.

- Completed the description of startup/turn-off processes. Completed the state diagram.

- Diagrams of three Startup sequence examples and one Turn-off example are added.

Jiashu Chen

External NDA Draft 0.4F 04/07/2009 4th Release F version - Corrected MDIO OP code error in Figure 2,

swapping 11 and 10. - Added missing Figure 6: Startup Sequence

Example 3: Some host transition control. All the figure numbers are increased by one after Fig 6.

- Figure 3 State transition diagram has a PDF conversion error. Now corrected.

- Corrected Figure 4 title. - Deleted Section 5.14 due to duplicated

information. - In Table 1, Starting DDM channel number is

changed to 0 from 1.

Publication Draft 1.0 04/13/2009 First full draft for releasing to public. - Added comments to register details Table 7, 8,

.9, and 10.



- Expended pin programming Registers A005h, A006h to A005h, A006h, A007h, A008h, A009h, and A00A for one register per pin.

- Moved all non-threshold registers from CFP_NVR Table 2 to CFP_NVR Table 1.

- Changed Figure 1: MDIO Interface architecture. Added a register block representing all IEEE802.3 reserved registers.

- Changed the wording of 3rd paragraph of section 3.2 regarding the 8-bit format.

- Deleted password control on DDM registers. - Added MDIO soft control/command timing table. - Added FEC control registers (amplitude and

phase) to each Channel Specific DDM table. - Removed the RX Detection Threshold Register

from CFP NVR Table 2.



TABLE OF CONTENTS

LIST OF FIGURES...................................................................................................................9

LIST OF TABLES ..................................................................................................................10

1 DOCUMENT SUMMARY................................................................................................11 1.1 BACKGROUND ............................................................................................................11 1.2 CFP MANAGEMENT INTERFACE ...................................................................................11 1.3 CONTENT OF THIS DOCUMENT......................................................................................11 1.4 NOTATION NOTES.......................................................................................................11

1.4.1 Numbering Notations............................................................................................11 1.4.2 Other Notational Remarks ....................................................................................12

2 CFP MANAGEMENT INTERFACE USING MDIO STANDARD.....................................13 2.1 CFP MDIO OVERVIEW ...............................................................................................13 2.2 CFP MDIO IMPLEMENTATION .....................................................................................13 2.3 CFP MDIO INTERFACE ARCHITECTURE .......................................................................14 2.4 CFP MDIO MANAGEMENT FRAME STRUCTURE ............................................................15

3 CFP MDIO REGISTER OVERVIEW ...............................................................................16 3.1 REGISTER SHADOW SPACE .........................................................................................16 3.2 NON-VOLATILE REGISTERS..........................................................................................16 3.3 VENDOR PRIVATE REGISTERS .....................................................................................16 3.4 MODULE CONTROL, STATUS, AND DDM REGISTERS .....................................................16 3.5 CHANNEL SPECIFIC DDM REGISTERS ..........................................................................16 3.6 RESERVED REGISTERS ...............................................................................................18

4 CFP CONTROL AND SIGNALING THEORY.................................................................19 4.1 CFP MODULE WORKING STATES.................................................................................19

4.1.1 Signals that affect transition of working states......................................................19 4.1.1.1 Combined module reset signal ......................................................................19 4.1.1.2 Combined module low power signal..............................................................19 4.1.1.3 Combined transmitter disable signal .............................................................19 4.1.1.4 Fault condition(s)...........................................................................................20

4.1.2 Output signals that are affected by module insertion or state transition ...............20 4.1.2.1 MOD_ABS.....................................................................................................20 4.1.2.2 GLB_ALRM ...................................................................................................20 4.1.2.3 HIPWR_ON...................................................................................................20 4.1.2.4 MOD_READY ...............................................................................................20 4.1.2.5 Mod_Fault .....................................................................................................20

4.1.3 CFP Working States.............................................................................................21 4.1.3.1 Reset State (Steady) .....................................................................................21 4.1.3.2 Initialize State (Transient)..............................................................................21



4.1.3.3 Low-Power State (Steady) ............................................................................21 4.1.3.4 High-Power-up State (Transient)...................................................................22 4.1.3.5 TX-Off State (Steady)....................................................................................22 4.1.3.6 TX-Turn-on State (Transient) ........................................................................22 4.1.3.7 Ready State (Steady) ....................................................................................23 4.1.3.8 TX-Turn-off State (Transient) ........................................................................23 4.1.3.9 High-Power-Down State (Transient)..............................................................23 4.1.3.10 Fault State (Steady) ......................................................................................23

4.2 STATE TRANSITION DIAGRAM ......................................................................................23 4.3 EXAMPLE MODULE STARTUP SEQUENCES.....................................................................25

4.3.1 Power up CFP Module to Ready State without Host Transition Control ...............25 4.3.2 Power up the module with full host transition control............................................26 4.3.3 Power up the module with some host transition control........................................27

4.4 MODULE TURN-OFF SEQUENCE EXAMPLE ....................................................................29 4.5 SPECIAL MODES OF OPERATION ..................................................................................29 4.6 GLOBAL ALARM SYSTEM LOGIC ...................................................................................30 4.7 TIMING FOR MDIO CONTROL AND STATUS ...................................................................34 4.8 CFP REGISTER ACCESS .............................................................................................34 4.9 PASSWORD CONTROL.................................................................................................35

5 DETAILED REGISTER DESCRIPTION..........................................................................36 5.1 CFP NVR TABLE 1: BASE ID INFORMATION..................................................................36

5.1.1 CFP NVR Content ................................................................................................36 5.1.2 CFP Data Bit-width...............................................................................................36 5.1.3 ASCII Coded Text ................................................................................................37 5.1.4 Module Identifier (8000h)......................................................................................37 5.1.5 Extended Identifier (8001h) ..................................................................................37

5.1.5.1 Power Class ..................................................................................................37 5.1.5.2 Lane Ratio Type............................................................................................37 5.1.5.3 WDM Type ....................................................................................................37

5.1.6 Connector Type Code (8002h) .............................................................................37 5.1.7 Ethernet Application Code (8003h) ......................................................................38 5.1.8 Fibre Channel Application Code (8004h)..............................................................38 5.1.9 Copper Application Code (8005h) ........................................................................38 5.1.10 SONET/SDH Application Code (8006h)............................................................38 5.1.11 OTN Application Code (8007h).........................................................................38 5.1.12 Additional Data Rate Capabilities (8008h) ........................................................39 5.1.13 Network and Host Lane Number (8009h) .........................................................39 5.1.14 Media Type and Number (800Ah).....................................................................39

5.1.14.1 Media Type ...................................................................................................39 5.1.14.2 Directionality..................................................................................................39 5.1.14.3 Optical Multiplexing and De-Multiplexing.......................................................39 5.1.14.4 Active Fiber per Connector............................................................................39

5.1.15 Maximum Network Interface (Optical) Lane bit rate (800Bh) ............................39 5.1.16 Maximum Host Interface Lane (Electrical) bit rate (800Ch) ..............................39



5.1.17 Single Mode Optical Fiber Length (800Dh).......................................................40 5.1.18 Multimode Optical Fiber Length (800Eh) ..........................................................40 5.1.19 Copper Cable Length (800Fh) ..........................................................................40 5.1.20 Heat Sink Type (8010h) ....................................................................................40 5.1.21 Transmitter Spectral Characteristics (8011h)....................................................40

5.1.21.1 Number of Wavelengths................................................................................40 5.1.21.2 Number of Active Transmit Fibers.................................................................40

5.1.22 Minimum Wavelength per Active Fiber (8012h, 8013h) ....................................41 5.1.23 Maximum Wavelength per Active Fiber (8014h, 8015h) ...................................41 5.1.24 Maximum per Channel Optical Width (8016h, 8017h) ......................................41 5.1.25 Device Technology 1 (8018h) ...........................................................................41

5.1.25.1 Laser Source Technology .............................................................................41 5.1.25.2 Transmitter Modulation Technology ..............................................................41

5.1.26 Device Technology 2 (8019h) ...........................................................................41 5.1.26.1 Wavelength Control.......................................................................................41 5.1.26.2 Cooled Transmitter........................................................................................42 5.1.26.3 Wavelength Tunability ...................................................................................42 5.1.26.4 VOA Implemented.........................................................................................42 5.1.26.5 Detector Type................................................................................................42 5.1.26.6 EDC Enhanced Receiver ..............................................................................42

5.1.27 Signal Code (801Ah).........................................................................................42 5.1.27.1 Modulation Polarity........................................................................................42 5.1.27.2 Signal coding.................................................................................................43

5.1.28 Absolute Maximum Total Optical Output Power per Connector (801Bh) ..........43 5.1.29 Absolute Maximum Total Optical Input Power per Connector (801Ch).............43 5.1.30 Maximum Power Dissipation (801Dh)...............................................................43 5.1.31 Maximum Power Consumption in Low Power Mode (801Eh) ...........................43 5.1.32 Maximum Operating Case Temperature (801Fh) .............................................43 5.1.33 Minimum Operating Case Temperature (8020h)...............................................43 5.1.34 Vendor Name (8021h ~ 8030h) ........................................................................43 5.1.35 Vendor OUI (8031h, 8032h, 8033h)..................................................................44 5.1.36 Vendor Part Number (8034h ~ 8043h)..............................................................44 5.1.37 Vendor Serial Number (8044h ~ 8053h) ...........................................................44 5.1.38 Date Code (8054h ~ 805Bh) .............................................................................44 5.1.39 Lot Code (805Ch, 805Dh).................................................................................45 5.1.40 CLEI Code (805Eh ~ 8067h).............................................................................45 5.1.41 MSA Revision Number (8068h) ........................................................................45

5.1.41.1 CFP MSA Hardware Specification Revision Number ....................................45 5.1.42 Module Vendor Hardware Revision Number (Optional) (8069h).......................45 5.1.43 Module Vendor Firmware/Software Revision Number (Optional) (806B)..........45 5.1.44 Diagnostic Monitoring Type (806Dh).................................................................45 5.1.45 Diagnostic Monitoring Capability 1 (806Eh) ......................................................45 5.1.46 Diagnostic Monitoring Capability 2 (806Fh) ......................................................45 5.1.47 Module Enhanced Options (8070h) ..................................................................46 5.1.48 Maximum High-Power-up Time (8071h) ...........................................................46



5.1.49 Maximum TX-Turn-on Time (8072h).................................................................46 5.1.50 CFP NVR 1 Checksum (807Fh)........................................................................46

5.2 CFP NVR TABLE 2: EXTENDED ID INFORMATION..........................................................52 5.3 CFP CONTROL, STATUS, AND DDM REGISTER TABLE...................................................53

5.3.1 CFP Command/Setup Registers ..........................................................................54 5.3.1.1 Password Entry and Password Change (A000h and A002h) ........................54 5.3.1.2 NVR Access Control (A004h)........................................................................54 5.3.1.3 PRG_CNTLs Function Select (A005h, A006, A007h) ...................................54 5.3.1.4 PRG_ALRMs Source Select (A008h, A009h, A00Ah)...................................54 5.3.1.5 Module Bi-/Uni- Directional Operating Mode Select (A00Bh) ........................55

5.3.2 CFP Control Registers (A010h, A011h, A012h, A013h) .......................................55 5.3.3 Module State Register (A016h) ............................................................................55 5.3.4 Data_Ready (A017h)............................................................................................55 5.3.5 Alarm/Status Summary Registers (A018h, A019h, A020h) ..................................55 5.3.6 Module Alarm/Status Registers (A01Dh, A01Eh, A01Fh, A020h) ........................55

5.3.6.1 Module General Status..................................................................................55 5.3.6.2 Module Fatal Fault Status .............................................................................56 5.3.6.3 Module Alarms and Warnings 1 ....................................................................56 5.3.6.4 Module Alarms and Warnings 2 ....................................................................56

5.3.7 Module Alarm/Status Latch Registers (A023h, A024h, A025h, A026h)................56 5.3.8 Module Alarm/Status Enable Registers (A029h, A02Ah, A02Bh, A02Ch) ............56 5.3.9 Analog AD Value Registers ..................................................................................56

5.4 CHANNEL SPECIFIC DDM/BOL DATA/CONTROL REGISTER TABLE .................................68 5.4.1 Channel Specific Alarm Registers (A200h, A201h) ..............................................68 5.4.2 Channel Specific Alarm Latch Registers (A202h, A203h) ....................................68 5.4.3 Channel Specific Alarm Enable Registers (A204h, A205h) ..................................68 5.4.4 Channel Specific Analog A/D Value Registers (A206h, A207h, A208h, A209h, A20Ah) ............................................................................................................................68 5.4.5 Channel Specific BOL Measurement Registers (A20Bh, A20Ch, A20Dh, A20Eh) 69 5.4.6 Channel Specific FEC Control Registers (A20Fh)................................................69



LIST OF FIGURES

Figure 1: Management Interface Architecture ........................................................................14 Figure 2: CFP MDIO Management Frame Structure ..............................................................15 Figure 3: State Transition Diagram during Startup and Turn-off.............................................24 Figure 4: Startup Sequence Example 1: No Host Transition Control......................................26 Figure 5: Startup Sequence Example 2: Full Host Transition Control ....................................27 Figure 6: Startup Sequence Example 3: Some Host Transition Control.................................28 Figure 7: Example of Turn-off Sequence: No Host Transition Control....................................29 Figure 8: Power-up Sequence for CFP Module Operating in Receiving Only Mode ..............30 Figure 9: Global Alarm Signal Aggregation ............................................................................33



LIST OF TABLES

Table 1: CFP MDIO Register Allocation .................................................................................17 Table 2: Global Alarm Related Registers ...............................................................................31 Table 3: Global Alarm Query Hierarchy..................................................................................32 Table 4: Timing for MDIO Control and Status ........................................................................34 Table 5: Register Access under Password Control ................................................................35 Table 6: Register Details Table Column Description ..............................................................36 Table 7: CFP Non Volatile Register Table 1 Details...............................................................47 Table 8: CFP Non-Volatile Register Table 2 Details...............................................................52 Table 9: Control, Status, and DDM Register Details ..............................................................57 Table 10: Channel Specific DDM Register Details .................................................................70



1 DOCUMENT SUMMARY

1.1 Background This technical document, CFP Management Interface, has been created by the CFP MSA group as a companion document to CFP MSA Hardware Specification. This document is offered to CFP module users and suppliers as a basis for a technical agreement. However it is not a warranted document. Each CFP module supplier will have their own datasheet. If the user wishes to find a warranted document, they should consult the datasheet of the chosen module supplier. The MSA group reserves the rights at any time to add, amend, or withdraw technical data contained in this document.

1.2 CFP Management Interface CFP MSA Hardware Specification has specified the use of Management Data Input/Output (MDIO) as the management interface between a Host and a CFP transceiver module, in which the hardware aspects of the MDIO interface such as its electrical characteristics and timing requirements are described. This document describes the adoption of IEEE802.3 Clause 45 as the primary definition of CFP MDIO bus. And it focuses on the description of CFP MDIO architecture, command frame, register set, control and signaling theory, and details of the register contents.

1.3 Content of this document Section 1 is the summary of this document. Section 2 provides an overview of the MDIO interface logic composition. Section 3 layouts the overview of the MDIO register set. Section 4 is devoted into detailed the discussions of CFP module control and host-module signaling theory. Finally Section 5 gives a series of tables describing the detail of all CFP MDIO registers.

1.4 Notation Notes

1.4.1 Numbering Notations Hex number is post-fixed by a lower case letter “h”. The examples are A000h, FFFFh, etc. Binary number is post-fixed by a lower case letter “b”. The examples are 11b, 1101b, etc. Decimal number has no pre-/post-fix, such as 65536. Two’s complement is used for signed values.



1.4.2 Other Notational Remarks Whenever is possible the special characters are avoided. For example, the symbol of micrometer is designated as “um” instead of “μm” to prevent from format loss in the editing process. The word “vendor” represents CFP module designer and manufacturer and the word “user” represents CFP module customer. In the Draft 1.0 of this document, “Optical Channel”, “Channel” and “Network Lane” are interchangeably used with equivalent meaning under proper context. “Electrical Channel”, “Channel” and “Host Lane” are interchangeably used with equivalent meaning under proper context.



2 CFP MANAGEMENT INTERFACE USING MDIO STANDARD

2.1 CFP MDIO Overview The MDIO interface of CFP transceivers follows the general specification of IEEE 802.3 Clause 45 and on-going IEEE 802.3 40GbE and 100GbE standardization project. From a hardware point of view, CFP MDIO electrical interface consists of 8 wires including 2 wires of MDC and MDIO, 5 wires of Port Address, and one wire for Global Alarm. MDC is the MDIO Clock line driven by host and MDIO is the bidirectional data line driven by both host and module depending upon the data directions. The CFP uses these pins in the electrical connector to instantiate the MDIO interface, listed in Table 2.1 MDIO Interface Pins, in CFP MSA Hardware Specification. Additional wires may be used as control signals and flags during the start-up and initialization of the CFP module; see section CFP Control and signaling theory for more detail. From a software/protocol point of view, CFP MDIO interface consists of the MDIO management frame, a set of MDIO registers, and a set of control and signaling rules. To avoid the conflict with IEEE802.3 standards, CFP register set does not use the addresses from 0000h to 7FFFh at the present time. All the CFP specific MDIO registers start at address 8000h, occupying the second half of the total space ranging from 8000h to FFFFh, totaling 32768 addresses.

2.2 CFP MDIO Implementation CFP MSA specifies the following implementation specifics for the MDIO interface.

a) Preserve the management frame structure defined in IEEE Standard 802.3 Clause 22.2.4.5 with further enhancement in Clause 45.1.1.

b) Preserve the addressing scheme of Clause 45 with 32 Port addresses, 32 Device addresses, and 65536 Register addresses at each Port-Device address.

c) MDIO nomenclatures defined in Clauses 22 and 45 of IEEE 802.3 are all adopted such as MDC, MDIO, STA (host), MMD (CFP), and PRTAD (Port address).

d) CFP MSA supports the clock rate of MDIO interface up to 4 MHz while maintain the downward compatibility to 100 kHz.

e) Both read and write activities occur on the rising edge of the MDC clock only. f) MDIO registers shall use shadow memory to decouple host-side timing

requirements from module vendor’s internal processing, timing, and hardware control circuit introduced latency.

g) CFP MSA only supports MDIO device type 1 (PMA/PMD). No other type of device is supported at the present time.

h) CFP includes the Global Alarm (GLB_ALRMn on connector output to the host) wire as part of the CFP MDIO interface.



2.3 CFP MDIO Interface Architecture CFP MSA specifies a MDIO interface architecture illustrated in Figure 1: Management Interface Architecture. Figure 1 depicts the architecture diagram that consists of a MDIO logic block, a MDIO register shadow block, a non-volatile memory (NVM) block, and a digital diagnostic monitor (DDM) block. While the implementation of this interface is vendor dependent this MSA specifies the use of MDIO register shadow to meet the host side timing requirement. This MDIO register shadow thus shall meet the following:

a) It supports dual access from host and from module internal operations such as NVM and DDM data.

b) It supports continuous host access (read and write) at maximum MDC rate of 4 MHz. c) It allows the uploading of NVM content into the register shadow after module

initialization is complete. The data saving from register shadow to NVM shall also be supported.

d) It supports the DDM data update periodically during the whole operation of the module. The data refresh rate shall meet the minimum of 10 Hz spec.

e) It supports the whole register suite including all non-volatile registers, control/status registers, as well as DDM registers.

f) It is implemented with SRAM or other fast storage media to achieve the above performance.

Figure 1: Management Interface Architecture

HOST MDIOInterface MDIO Logic

MDIORegisterShadow

Non-VolatileMemory(NVM)

Control Logic / CPU

MDIO Bus

PORTADD Bus

DataFlow

Reserved forIEEE802.3

CFP Module

DigitalDiagnosticMonitors(DDM)

DataFlow

1.0000h

1.7FFFh1.8000h

1.FFFFh



2.4 CFP MDIO Management Frame Structure CFP uses same communication data frame structure defined in IEEE 802.3 Clause 45. Each frame can be either an address frame or a data frame. The total bit length of each frame is 64, consisting of 32 bits preamble, followed by the frame command body. The command body consists of 6 parts illustrated in Figure 2: CFP MDIO Management Frame Structure, where ST = start bits (2 bits), OP = operation code (2 bits), PHYADR = physical port address (5 bits), DEVADD = MDIO device address (or called device type, 5 bits), TA = turn around bits (2 bits), and the final 16-bit field for payload, can be address or data depending upon the OP code.

Figure 2: CFP MDIO Management Frame Structure

ST OP PHYADR DEVADD TA 16-bit ADDRESS/DATA32-bit Preamble

00

OP ACCESS TYPE00 Address01 Write11 Read10 Post Read Inc Add

DEVADD DEVICE TYPE00000 Reserved00001 PMA/PMD00010 WIS00011 PCS00100 PHY XS00101 DTE XS

Access Type ContentAddress Reg AddressWrite Write DataRead Read DataRead Inc Read Data



3 CFP MDIO REGISTER OVERVIEW

3.1 Register Shadow Space The total CFP MDIO register shadow address space (from 8000h to FFFFh) is logically divided into 8 pages with each page naturally starting at even hex thousand, that is, 8000h, 9000h, A000h, …, F000h. Each page has 4096 addresses and is further divided into 32 tables. Each table has 128 Register addresses. Note that there is no physical boundary in between pages and tables. The sole purpose of this logical segmentation is for the convenience of CFP MDIO Register space allocation and access control. The overview of the register shadow is listed in Table 1: CFP MDIO Register Allocation.

3.2 Non-volatile Registers CFP register shadow supports three types of non-volatile register (NVR) table, CFP NVR Tables, Vendor NVR Tables, and User NVR Tables. Each NVR table shall be backed by physical non-volatile memories (NVM) for all populated registers. On module Initialize, all of the NVR tables shall be uploaded with default values stored in NVMs. CFP MSA specifies CFP NVR 1 Table for storing basic ID data, CFP NVR 2 Table for storing Extended ID data, Vendor NVR Table for storing additional data for users, and User NVR Table for storing user’s data. This MSA further specifies the content of CFP NVR 1 Table and CFP NVR 2 Table. The content of Vendor NVR Table and User NVR Table is subject to additional agreement between user and vendor.

Page 8000h is allocated for all the three types of NVR tables. Each NVR contains 2 tables, totaling 256 logical addresses. All the NVR tables are implemented with lower 8-bit of space filled with data and the upper 8-bit of space left unused. A fully populated table shall require a maximum of 128 bytes of physical memory to back up.

3.3 Vendor Private Registers Page 9000h is reserved exclusively for each vendor of CFP module for their development and implementation. There is no plan for MSA to use this page.

3.4 Module Control, Status, and DDM Registers Page A000h is allocated for all the CFP specific controls and digital diagnostic monitoring (DDM). All the data stored in this page are considered to be volatile. Initial values are assigned to these registers for correct startup and operation upon the power-up of the module.

3.5 Channel Specific DDM Registers For each optical channel CFP supported there is a table of registers containing the channel specific DDM data, warning/alarm signals, and some BOL measurement data. Consider all



the foreseeable applications; a total of 12 optical channel specific register tables are allocated.1

Table 1: CFP MDIO Register Allocation

CFP MDIO Register Allocation Starting Address in Hex

Ending Address in Hex

Access Type

Allocated Size

DataBit

Width Description

1.0000 1.7FFF X 32768 x Reserved for IEEE 802.3ae/ba Use 1.8000 1.80FF RO 128x2 8 CFP NVRs, Can only be written by Vendor. 1.8100 1.83FF RO 768 x MSA Reserved 1.8400 1.84FF RO 128x2 8 Vendor NVRs, Can only be written by Vendor. 1.8500 1.86FF RO 768 x MSA Reserved 1.8800 1.88FF R/W 128x2 8 User NVRs 1.8900 1.8FFF RO 1792 x MSA Reserved for User NVR extension 1.9000 1.9FFF RO 4096 x Reserved for Vendor Private Use 1.A000 1.A0FF R/W 128x2 16 CFP Module Controls, Status, and DDM Data 1.A100 1.A17F R/W 128 16 CFP Channel 0 Specific DDM and Measured Data1.A180 1.A1FF R/W 128 16 CFP Channel 1 Specific DDM and Measured Data1.A200 1.A27F R/W 128 16 CFP Channel 2 Specific DDM and Measured Data1.A280 1.A2FF R/W 128 16 CFP Channel 3 Specific DDM and Measured Data1.A300 1.A37F R/W 128 16 CFP Channel 4 Specific DDM and Measured Data1.A380 1.A3FF R/W 128 16 CFP Channel 5 Specific DDM and Measured Data1.A400 1.A47F R/W 128 16 CFP Channel 6 Specific DDM and Measured Data1.A480 1.A4FF R/W 128 16 CFP Channel 7 Specific DDM and Measured Data1.A500 1.A57F R/W 128 16 CFP Channel 8 Specific DDM and Measured Data1.A580 1.A5FF R/W 128 16 CFP Channel 9 Specific DDM and Measured Data

1.A600 1.A67F R/W 128 16 CFP Channel 10 Specific DDM and Measured Data

1.A680 1.A6FF R/W 128 16 CFP Channel 11 Specific DDM and Measured Data

1.A700 1.AFFF RO 2304 x Reserved by CFP MSA 1.B000 1.BFFF RO 4096 x Reserved by CFP MSA 1.C000 1.CFFF RO 4096 x Reserved by CFP MSA 1.D000 1.DFFF RO 4096 x Reserved by CFP MSA 1.0000 1.EFFF RO 4096 x Reserved by CFP MSA 1.F000 1.FFFF RO 4096 x Reserved by CFP MSA

1 1 Register support for electrical lanes to support PMDs such as 40GBASE-CR4 on the network side is planned.



3.6 Reserved Registers All reserved registers and all the reserved bits in a register shall be “read-only” and they shall be read as all-zeros. When write to these registers or bits, there shall be no effect.



4 CFP CONTROL AND SIGNALING THEORY

4.1 CFP Module Working States To facilitate a well-defined CFP startup and turn-off sequences and other applications, MSA specifies a minimum number of working states that CFP shall support. In association with these working states, a set of input and a set of output signals are also defined.

4.1.1 Signals that affect transition of working states Three inputs and one internally generated signal are defined and each of them is a logical combination of connector pin status, MDIO register bit status, and module internally generated logic signals in some cases.

4.1.1.1 Combined module reset signal

MOD_RSTs = NOT(MOD_RSTn) OR Mod_Reset OR Vcc_Low, where,

MOD_RSTn is the hardware pin input, Mod_Reset is the MDIO register bit, de-asserted in Reset and, Vcc_Low is the CFP internally generated logic signal indicating the validity of

Vcc2, Vcc_Low = 1 if Vcc at connector is lower than a specified threshold,

= 0 if Vcc is within range.

4.1.1.2 Combined module low power signal MOD_LOPWRs = MOD_LOPWR OR Mod_Low_Power OR HW_Interlock, where, MOD_LOPWR is the hardware pin input, MOD_Low_Power is the MDIO register bit, de-asserted in Reset HW_Interlock is the internally generated logic signal based on hardware Interlock MSB and LSB pins which are the MSA defaults of PRG_CNTL2 and PRG_CNTL3. HW_Interlock = 1 if mod power > Host cooling capacity HW_Interlock = 0 if mod power < Host cooling capacity or if hardware Interlock is not used.

4.1.1.3 Combined transmitter disable signal

2 Vcc_Low does not correspond to the operating voltage range specified in the CFP MSA Hardware specification. Vcc_Low is the threshold voltage below which the module is held in reset, and above which normal operation can be initiated. The threshold for Vcc_Low is vendor specific, but is expected to be below the operating voltage of the module.



TX_DISs = TX_DIS OR TX_Disable, where,

TX_DIS is the hardware pin, TX_Disable is the MDIO register bit, de-asserted in Reset.

4.1.1.4 Fault condition(s) Fault condition signal is a combination of a variety of fatal failures which may occur during module startup sequence or normal operation. It is the logic OR of all the effective bits in MDIO Register A013h.

4.1.2 Output signals that are affected by module insertion or state transition Hardware pins MOD_ABS, GLB_ALRM, PRG_ALRM2 (programmed as MSA default HIPWR_ON), PRG_ALRM3 (programmed as MSA default MOD_READY), and MDIO register bits are used to signal the host the transitions among states. In the case user chooses to program these pins for other purposes their corresponding counterpart MDIO register bits can be used for reporting state transitions.

4.1.2.1 MOD_ABS This signal reports the event of module insertion, which informs the presence of the module at connector. There is no MDIO register counterpart of it.

4.1.2.2 GLB_ALRM This signal, as an interrupt request to host, reports all the alarm/warning conditions (see Section 4.6 of this document). It is cleared upon module reset. During normal operation, the presence of any 1 value in the flag registers A023 -- A026 will assert this pin. The hardware pin GLB_ALRMn reports the invert of GLB_ALRM. During module startup, the completion of “Initialize” asserts this pin and its corresponding MDIO register bit (A01D.10). This pin is cleared upon host reading corresponding flag register, including the flag bit of “Init_Complete” in register A023.

4.1.2.3 HIPWR_ON HIPWR_ON is the MSA default function of PRG_ALRM2 hardware pin. The MDIO register bit is at register A023. Both of them are set upon the successful exit of High-Power-up state. Both of them are cleared upon host reading the soft bit at register A023.

4.1.2.4 MOD_READY MOD_READY is the MSA default function of PRG_ALRM3 hardware pin. The soft bit is at MDIO register A023. Both of them are set upon the exit of the TX-Turn-on state. Both of them are cleared upon host reading the soft bit at register A023.

4.1.2.5 Mod_Fault Mod_Fault is a soft bit 3 of MDIO register A023. This bit informs the occurrence of any fatal error upon which module must enter “Fault” state. It is set upon occurrence of any fatal fault



value at register A024 and it gets cleared upon host reading register A024. If this signal is assigned to a hardware programmable alarm pin it will be designated as MOD_FAULT.

4.1.3 CFP Working States MSA specifies a minimum number of 10 working states in the context of defining the startup and turn-off sequences. Of the 10 states, 5 of them are steady states and 5 of them are transient states. For each one of the states, the behavior of each input, output, and the state shall be defined for the clear hand-shaking between the host and the module.

4.1.3.1 Reset State (Steady) MOD_RSTs assertion causes a complete reset of the CFP module, including any digital circuitry that may consist of module control function and MDIO interface, as well as any high speed circuitry if they are resettable. All circuits are in low power mode and stay in reset whenever MOD_RSTs is asserted. When it is asserted, it overrides the status of other input such as MOD_LOPWRs and TX_DISs. Module reset shall happen not only when MOD_RSTs is asserted, but also when module is powered on or when it is hot-plugged in to the connector. When CFP module is already in connector, MOD_RSTs assertion can be used to resolve any hardware hang-up, particularly a communication hang-up or other types of control hang-ups. The de-assertion of MOD_RSTs drives CFP out Reset state. Regardless of other pins and conditions, CFP enters Initialize State.

4.1.3.2 Initialize State (Transient) The de-assertion transition of MOD_RSTs drives CFP to enter Initialize State. In this state, the control circuits and MDIO communication circuit shall be initialized and become fully functional. All the MDIO Registers shall also be initialized with default values stored in non-volatile memory. All the other circuits shall be kept in low power mode regardless the status of MOD_LOPWRs. Upon successful initialization, CFP shall assert GLB_ALRM pin to signal the Host the completion of Initialization. Then CFP shall enter either Low-Power State or High-Power-up state depending upon the status of MOD_LOPWRs. However, if initialization fails, CFP module shall enter Fault State. Initialize is a transient state. MSA specifies the maximum initialization time to be 300 ms. MSA also specifies a MDIO register at address 8054h where vendor can put in their recommended maximum waiting time for the host.

4.1.3.3 Low-Power State (Steady) CFP enters and stays in the Low-Power State whenever MOD_LOPWRs is asserted. In Low-Power State, the MDIO interface and control circuits shall remain powered and fully functional. All the other power consuming circuits shall be put in low power. In this state, the PHYs are powered down and loopback is not possible. The nAUI outputs shall go to a steady state (no transitions).



Low-Power State is a steady state and it shall exit to High-Power-up State upon the de-assertion of MOD_LOPWRs.

4.1.3.4 High-Power-up State (Transient) Host drives CFP into High-Power-up State by the transition of de-asserting MOD_LOPWRs signal from Low-Power State. In this state CFP module powers up all the functional circuitry and completes all required initialization such as inrush current control, TEC temperature stabilization, etc. Upon successfully powering up the module CFP shall assert HIPWR_ON pin to signal the host. The CFP shall either enter TX-Off State or TX-Turn-on State depending upon the status of TX_DISs. If the powering up process fails CFP shall enter the Fault State and keep HIPWR_ON de-asserted. High-Power-up is a transient state. The time it takes to finishes these processes varies from module to module depending upon applications. MSA specifies a parameter of T_High-Power_up at register address 80CEh where vendor can put in their recommended maximal waiting time for the host to read.

4.1.3.5 TX-Off State (Steady) CFP enters and stays in the TX-Off State whenever TX_DISs is asserted. In TX-Off state, the transmitters in all the channels are turned off but all other parts of the module remain high powered and functional. TX-Off State is a steady state and it only will exit to TX-Turn-on State upon the de-assertion of TX_DISs.

4.1.3.6 TX-Turn-on State (Transient) Host drives CFP into TX-Turn-on State by the transition of de-asserting TX_DISs signal from TX-Off State. While TX disable is a global action that turns off all the transmitters cross all the network (optical) channels the TX turn-on is selective pending upon the status of Ch n Disable bits in register A013h. Register A013h is the “Individual Ch Soft TX_DIS Control” register. Bits 0 to 11 disable a total maximum 12 optical transmitters individually. If any bit is set to disable status then the corresponding channel shall remain disabled after the module enters the TX-Turn-on State. De-asserting TX_DISs shall not clear any bit in register A013h until a specific MDIO frame is issued to reset this bit. Upon successfully turning on the desired transmitters CFP shall assert MOD_READY pin to signal the host. The CFP shall enter Ready State. If the turning on TX process fails CFP shall enter the Fault State and keep MOD_READY pin de-asserted. TX-Turn-on is a transient state. The time it takes to complete the turn-on varies from module to module depending upon the applications. MSA specifies a parameter of T_TX-Turn-on at



register address 80CFh where vendor can put in their recommended maximal waiting time for the host to read.

4.1.3.7 Ready State (Steady) CFP enters from TX-Turn-on State and stays in Ready State upon successful transmitter turning on. In this state CFP is fully ready or already passes data. All the DDM and MDIO and other functions are fully functional in this state. Ready State is a steady state and it exits upon the assertion of MOD_RSTs, MOD_LOPWRs, TX_DISs, and fault conditions.

4.1.3.8 TX-Turn-off State (Transient) Host drives CFP into TX-Turn-off State by the transition of asserting TX_DISs, MOD_LOPWRs, and MOD_RSTs signals. In this state CFP module turns off all the transmitters regardless the setting of Register A013h Individual Ch Soft TX_DIS Control. Upon turning off all the transmitter channels CFP shall de-assert MOD_READY pin to signal the host. The CFP shall enter TX-Off State. TX-Turn-off is a transient state. The time it takes to complete the turn-off shall be short as listed in Table 4: Timing for MDIO Control and Status.

4.1.3.9 High-Power-Down State (Transient) CFP enters High-Power-down State by the transition of asserting MOD_LOPWRs and MOD_RSTs signals. In this state, CFP module powers down all the power-consuming circuitry to maintain the overall power consumption less than 2 Watt. CFP shall maintain control circuitry and MDIO interface fully functional. Upon powering down the module CFP shall de-assert HIPWR_ON pin to signal the host. The CFP shall either enter Low-Power State or Reset State depending upon the status of MOD_RSTs. High-Power-down is a transient state. The time it takes to finish this process is listed in Table 4: Timing for MDIO Control and Status.

4.1.3.10 Fault State (Steady) CFP enters this state from any states upon the assertion of Mod_Fault bit in MDIO register at address A01Eh. In entering this state, CFP shall immediately de-assert MOD_READY pin or bit to signal the host. Meanwhile depending upon the nature of the fault and vendor’s implementation, CFP shall enter in Low-Power mode to avoid potential damage to the module. Further diagnosis of the failure can be done by interrogating MDIO registers.

4.2 State Transition Diagram Using MSA specified working states a CFP module startup sequence can be defined and this definition is the common protocol between host and the module. In Figure 3: State Transition



Diagram during Startup and Turn-off the middle row of states and the associated transition paths capture the possible cinereous of a module startup sequence. Use this definition, host can power up the module into the Low-Power State, the TX-Off State, or a fully functional Ready State by setting up the initial conditions of MOD_RSTs, MOD_LOPWRs, and TX_DISs. A Fault State is defined to capture all the possible fault condition occurred in the process of module startup.

Figure 3: State Transition Diagram during Startup and Turn-off

Two circles in the bottom row are TX-Turn-off State and High-Power-down State. When TX_DISs is asserted, CFP enters TX-Turn-off state. After proper TX turn off procedure is performed CFP module enters TX_Off State. If MOD_LOPWRs is asserted CFP will also enter TX-Turn-off State and then enters High-Power-down State. After both TX turn off procedure and power down procedure are performed, CFP module enters Low-Power State. If MOD_RSTs is asserted, CFP shall enter Reset State after power down procedure is performed. Three signal pins GLB_ALRM, HIPWR_ON (defaulted to PRG_ALRM2), and MOD_READY (defaulted to PRG_ALRM3) are used to report the milestones of startup sequence, initialization completed, module fully powered up, and module ready, respectively. The timing diagrams of these pins are depicted at the bottom of Figure 3: State Transition Diagram during Startup and Turn-off. In the case of TX turn off, power down, or reset, three signal



pins shall reversely report the status of the state transition if they remain programmed with MSA default functions. MDIO register bits are allocated and can perform same functions as the hardware control and signal pins, as those stated in previous sections of this MSA. Additionally, MDIO register CFP Startup and Shutdown Status at A01Dh provides state history (bits 15 through 7) and current state number (bits 3 through 0).

4.3 Example Module Startup sequences

With the defined working states and the transition paths, host is able to control the startup sequence by setting the initial conditions of the three control signals, MOD_RSTs, MOD_LOPWRs, and TX_DISs.

4.3.1 Power up CFP Module to Ready State without Host Transition Control Figure 4: Startup Sequence Example 1: No Host Transition Control illustrates a MSA specified startup sequence for host to power up the CFP module all the way to Ready State without needing host intervention. In this instance, host sets up the connector initial condition by applying Vcc to the connector and de-asserting all three control pins MOD_RSTn, MOD_LOPWR, and TX_DIS. The staggering arrangement causes ground and Vcc pins to first contact CFP module pins. Since Vcc becomes available the pull-up resistors in the module assert all three control signals first. As the “Plug-in” action progresses, MOD_RSTn and TX_DIS pins are in contact with host pins and hence they are de-asserted. Finally MOD_ABS and MOD_LOPWR are engaged. This causes MOD_LOPWR de-assertion. Hence the initial conditions host applies to the CFP module take effect. The CFP module, under these initial conditions, goes through Reset, Initialize, High-Power-up, and TX-Turn-on States and finally enters Ready State. During this course, the CFP module asserts GLB_ALRM, HIPWR_ON, and MOD_READY pins subsequently. These signals inform host the completion of control circuit initialization and MDIO availability, module fully powered up, and module ready for data, respectively. MSA specifies 2 timing parameters Maximum High-Power-up Time (80CEh) and Maximum TX-Turn-on Time (80CFh). Host uses these two parameters to determine how long it shall wait at each stage if using HIPWR_ON and MOD_READY as the signals of progress monitor is not desirable or not available. Vendor should provide these parameters as they may vary from product to product and from vendor to vendor.



Figure 4: Startup Sequence Example 1: No Host Transition Control

4.3.2 Power up the module with full host transition control In contrast to the case presented in 3.1.14.1, host can apply full control over the course of power-up sequence. In this case host controls the startup sequence by asserting all the control signals as the startup initial conditions. After the plug-in action, host then de-asserts them sequentially such that the startup sequence stops before each transient state and wait for host’s inputs. This example is illustrated by Figure 5: Startup Sequence Example 2: Full Host Transition Control.



Figure 5: Startup Sequence Example 2: Full Host Transition Control

4.3.3 Power up the module with some host transition control In some case, it is desirable to power up the module to Low-Power State. In this state, host reads T_High-Power-up and T_TX-Turn-on registers, changes PRG_ALRMs and PRG_CNTLs, before de-asserts MOD_LOPWRs. This example is illustrated in Figure 6: Startup Sequence Example 3: Some Host Transition Control.



Figure 6: Startup Sequence Example 3: Some Host Transition Control



4.4 Module Turn-off Sequence Example Figure 7: Example of Turn-off Sequence: No Host Transition Control illustrates the example of Turn off sequence without host transition control by hot-un-plug. In this case, un-plug action causes assertions of MOD_ABS and MOD_LOPWR pins first. Then due to module extraction, MOD_RSTn is asserted. CFP enters TX-Turn-off State and High-Power-down State subsequently. In between these events, CFP module de-asserts MOD_READY, HIPWR, and GLB_ALRM sequentially and enters Reset. Finally Vcc is disconnected.

Figure 7: Example of Turn-off Sequence: No Host Transition Control

4.5 Special Modes of Operation CFP MSA defines additional operation modes such as transmitting only and receiving only for a CFP module. To power up the module in receiving only mode, host needs to assert TX_DISs signal and keeps other control signals as required. In this way CFP module will power up to TX-Off State and uses HIPWR_ON to signal host it is ready for receiving data.



Figure 8: Power-up Sequence for CFP Module Operating in Receiving Only Mode depicts this application. Figure 8: Power-up Sequence for CFP Module Operating in Receiving Only Mode

The support of transmitting only mode is no different from normal working mode except host may expect CFP module to squelch the electrical outputs.

4.6 Global Alarm System Logic The CFP implements a quasi-real-time hardware GLB_ALRMn interrupt pin to alert the host to any condition outside normal operating conditions, a function similar to LASI signal pin defined in the XENPAK MSA. This Global Alarm System Logic involves 3 sets of status/warning/alarm/fault register, the Source Registers, the Latch Registers, and the Enable Registers, all listed in Table 2: Global Alarm Related Registers.



Figure 9: Global Alarm Signal Aggregation depicts the system logic of Global Alarm. In this system Source Registers drive the Latch Registers on a bit-by-bit base. The logic OR of all bits in the Latched Registers drives the GLB_ALRMn pin. This simple and flat OR combinational logic minimizes the assert time after a Global Alarm condition happens. Also shown in Figure 9, the host may control which latched bits result in a global alarm interrupt by setting high individual bits from the Enable Registers listed in Table 2. All enabling bits shall be volatile and startup with all enabled. (= 1). Existence of any status/warning/alarm/fault conditions represented by the Source Registers shall lead to latched bits in the Latch Registers in a bit-by-bit correspondence. The presence of any “1” values will assert the hardware GLB_ALRMn pin (active low). When the GLB_ALRMn pin alerts the host system to a latched condition, the host may query the latched register to allocate the condition. The latched bits are cleared on the read of the corresponding register. Thus a read of all latched registers can be used to reset all latched register bits and de-assert the hardware GLB_ALRMn pin. In order to minimize the number of reads for allocating the origin of the global alarm condition, host uses the global alarm query hierarchy listed in Table 3: Global Alarm Query Hierarchy. Upon servicing the GLB_ALRMn interrupt, host reads Global Alarm Summary register to identify whether the condition happens at module level or at channel level. If it is the latter, host reads the Channel TX Alarm Summary and Channel RX Alarm Summary registers to further allocate the source of condition. And finally host can read the latched channel registers to finalize the search.

Table 2: Global Alarm Related Registers

Description MDIO Register Addresses Source Registers

Module General Status A01D Module Fatal Fault A01E Module Alarms/Warnings 1 A01F Module Alarms/Warnings 2 A020 Channel n Tx Alarm A200 + n × 80, n=0, 1, …, N. Channel n Rx Alarm A201 + n × 80, n=0, 1, …, N.

Latch Registers Module General Status Latch A023 Module Fatal Fault Latch A024 Module Alarms/Warnings 1 Latch A025 Module Alarms/Warnings 2 Latch A026 Channel n Tx Alarm Latch A202 + n × 80, n=0, 1, …, N. Channel n Rx Alarm Latch A203 + n × 80, n=0, 1, …, N.



Enable Registers Module General Status Enable A029 Module Fatal Fault Enable A02A Module Alarms/Warnings 1 Enable A02B Module Alarms/Warnings 2 Enable A02C Channel n Tx Alarm Enable A204 + n × 80, n=0, 1, …, N. Channel n Rx Alarm Enable A205 + n × 80, n=0, 1, …, N. Notes: 1. All addresses and numbers are in hex format. 2. “n” denotes the optical channel index. 3. “N” is the total number of optical channel supported in the CFP module.

Table 3: Global Alarm Query Hierarchy

Query Level Register Name Register Addresses 1 Global Alarm Summary A018 2 Tx Channel Alarm Summary A019 2 Rx Channel Alarm Summary A01A 3 Channel n Tx Alarm Latch A202 + n × 80, n=0, 1, …, N. 3 Channel n Rx Alarm Latch A203 + n × 80, n=0, 1, …, N.



Figure 9: Global Alarm Signal Aggregation

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4.7 Timing for MDIO Control and Status Detail timing for soft control and status functions are described in Table 4: Timing for MDIO Control and Status. The timing parameters are closely related to the timing required by state transition time as noted in the table.

Table 4: Timing for MDIO Control and Status Parameter Min Max Unit Conditions Soft Module Reset assert time

250 ms Time from Soft Module Reset bit set until CFP module enters Reset State.

Soft TX_Disable assert time 250 ms Time from TX_Disable bit set until CFP module enters TX-turn-off State.

Soft TX_Disable de-assert time

250 ms Time from TX_Disable bit cleared until CFP module enters TX-Turn-on State.

Mod_Low_Power assert time 250 ms Time from Mod_Low_Power bit set until module enters Low-Power State

Mod_Low_Power de-assert time

250 ms Time from Mod_Low_Power bit cleared until module enters High-Power-on State.

RX_LOS assert time 150 ms Time from RX_LOS state to RX_LOS bit set. RX_LOS de-assert time 150 ms Time from non-LOS state to RX_LOS bit cleared. Analog parameter data ready 500 ms Time from de-assert of MOD_RSTs until A/D value

available in MDIO A2D value registers. Global_Alarm assert time 150 ms Time from GLB_ALRM assert Global_Alarm de-assert time 150 ms Time from GLB_ALRM de-assert Prog_Alarm1 assert time 150 ms Time from PRG_ALRM1 assert Prog_Alarm2 assert time 150 ms Time from PRG_ALRM2 assert Prog_Alarm3 assert time 150 ms Time from PRG_ALRM3 assert Prog_Alarm1 de-assert time 150 ms Time from PRG_ALRM1 de-assert Prog_Alarm2 de-assert time 150 ms Time from PRG_ALRM2 de-assert Prog_Alarm3 de-assert time 150 ms Time from PRG_ALRM3 de-assert Prog_Control1 assert time 150 ms Time from PRG_CNTL1 assert Prog_Control2 assert time 150 ms Time from PRG_CNTL2 assert Prog_Control3 assert time 150 ms Time from PRG_CNTL3 assert Prog_Control1 de-assert time 150 ms Time from PRG_CNTL1 de-assert Prog_Control2 de-assert time 150 ms Time from PRG_CNTL2 de-assert Prog_Control3 de-assert time 150 ms Time from PRG_CNTL3 de-assert Mod_Fault 250 ms Time from module enters Fault State High_Power_on 250 ms Time from module exits High-Power-up State. Mod_Ready 250 ms Time from module enters Ready State.

4.8 CFP Register Access With regular MDIO command frame user can read the MSA register content stored in register shadow. These user readable registers are CFP NVRs, User NVRs, and Vendor NVRs on page 8000h. User also has full read access to shadow registers on Page A000h for control, status, and DDM information.



User can write to the writable addresses on page A000h for control purpose. User can write to User NVRs in register shadow. However writing via MDIO frame only results in volatile values. Writing permanently requires using NVR Control and Status Register at A004h. MDIO Register A004h provides two NVR access functions, Save and Restore. The “Save” operation stores the specified NVR shadow table into NVM. The “Restore” operation uploads the specified NVM image into shadow NVR table. The function and usage of register A004h is similar to that of XENPAK NVR Control/Status Register (0x8000). The difference is the addition of bits 7~6. Bits 7~6 select which NVR table to access. This MSA recommends user to reference Clause 10.9 for further information.

4.9 Password Control Password is optionally provided in this MSA to allow vendor and user control the access to the information in the register shadow. Registers A000h ~ A001h are reserved for the password entry. The Password entry registers are write-only (WO) and will be retained until Reset or rewritten by host. Password is a 2-word long data with the most significant word occupying the lower register address. All user passwords shall be in the range of 00000000h to 7FFFFFFFh while all vendor passwords shall be in the range of 80000000h to FFFFFFFFh. A MSA default password 01011100h is given for any new module shipped. Table 5: Register Access under Password Control lists the access control needed for accessing various parts of the register shadow. Password can be changed by user writing to Password Change register at A002h and A003h. On power up and reset the password entry register shall be set to 00000000h.

Table 5: Register Access under Password Control

Register Read Write Restore Save Note CFP NVR 1 MSA Default N/A User* N/A CFP NVR 2 MSA Default N/A User* N/A Vendor NVR MSA Default N/A User* N/A User NVR MSA Default User* User* User*

*Using register A004h to operate.



5 DETAILED REGISTER DESCRIPTION

The detailed MDIO register descriptions are listed in Table 7, 8, 9 and 10. Each table has 7 data columns with the following definition.

Table 6: Register Details Table Column Description

Column Description Hex Add Starting address of each register in hex number format, device number

defaults to 1. Size Number of MDIO addresses each register occupies. Access Type RO = Read Only; RW = Read and Write; LH = Latched High; COR =

Clear On Read. Bit This field indicates the range of bits used for a particular data field in

the format of m~n, where m is starting high bit and n is the ending low bit.

Register Name

This is the name of a register. Full English words are used for maximum clarity. Acronym use is minimized.

Bit Field Name

This is the name of a specific bit data field. Full English words are used for maximum clarity. Acronym use is minimized. Normally in non-bold face.

Description Details of each Register field and/or behavior of a bit. LSB Unit

This column contains the unit of a physical quantity represented by the list significant bit of the register field.

Init Value The initial value of each volatile register takes after module boots up.

5.1 CFP NVR Table 1: Base ID Information

5.1.1 CFP NVR Content CFP Non Volatile Registers contain the module basic ID information and extended ID information about the CFP product, provided by CFP module vendor. The basic ID information area is also termed as CFP NVR 1 Table occupying register addresses 8000h through 806Dh with a checksum located at 807Fh. The extended ID area is also termed as CFP NVR 2 Table occupying register addresses 8080h through 80D0h with a checksum located at 80FFh.

5.1.2 CFP Data Bit-width All the NVR registers in CFP NVR 1 and 2, (also true for User NVR and Vendor NVR tables) use 8-bit data representation occupying the lower 8-bit space of each register address. The higher 8-bit space shall be read as 0 and write as “don’t care”.



5.1.3 ASCII Coded Text The data in CFP NVR 1 and 2 are in two forms, an 8-bit bit pattern or an 8-bit ASCII code. The bit pattern is used to code the ID information with individual bit or a group of bits discretely. The 8-bit ASCII code represents a character, either a letter or a number. All the registers that contain ASCII characters have one character at each MDIO address lower-address-aligned and padded with ASCII <space> characters at unused higher addresses.

5.1.4 Module Identifier (8000h) For CFP MSA compliant modules, this value shall be 0Eh. Other module form factors used in the industry are identified with other values in this register. For details, please see Register 8000h in Table 7.

5.1.5 Extended Identifier (8001h) The extended identifier provides additional information about the transceiver module.

5.1.5.1 Power Class As outlined in the CFP MSA Hardware Specification, there are four power classes identified for the CFP MSA. The power classes are provided to allow the user to identify the power requirements of the module and determine if the system is capable of providing and dissipating the specified power class. For a more detailed description, please refer to the CFP MSA Hardware Specification.

5.1.5.2 Lane Ratio Type The CFP module shall support a network interface which may comply to various IEEE PMD, SONET/SDH, OTN or other standards body physical interfaces. For example, in the case of 100GBASE-LR4 the network interface corresponds to the optical PMD specified in IEEE clause 88. The CFP module shall also support a host interface which is instantiated as an electrical interface with multiple lanes operating at a nominal 10Gbit/s. This register is implemented to record the ratio of network lanes to host lanes: 00 = Network Lanes equals 1 and Number of Host Lanes is >1 (Serial); 01 = Number of Network Lanes does not equal Number of Host Lanes (Gearbox); 10 = Number of Network Lanes equals Number of Host Lanes (Parallel).

5.1.5.3 WDM Type In this register, the CFP module shall identify any optical grid spacing which is in use by the CFP module.

5.1.6 Connector Type Code (8002h) In this register, the CFP module shall identify the connector technology used for the network interface. Early iterations of the CFP MSA have identified SC optical connectors, and it is expected that further connectors will be identified.



5.1.7 Ethernet Application Code (8003h) In this register, the CFP module shall identify what if any Ethernet PMD application is supported. Any CFP module which supports an application not including Ethernet such as SONET/SDH, OTN, Fibre Channel or other, shall record a “00h” to signify that the Ethernet application is undefined. Any CFP module which supports an application which includes Ethernet and additional applications such as SONET/SDH, OTN, Fibre Channel or other, shall record the value in this register which corresponds to the Ethernet application which is supported.

5.1.8 Fibre Channel Application Code (8004h) In this register, the CFP module shall identify what if any Fibre Channel PMD application is supported. Any CFP module which supports an application not including Fibre Channel such as SONET/SDH, OTN, Ethernet or other, shall record a “00h” to signify that the Fibre Channel application is undefined. Any CFP module which supports an application which includes Fibre Channel and additional applications such as SONET/SDH, OTN, Ethernet or other, shall record the value in this register which corresponds to the Fibre Channel application which is supported.

5.1.9 Copper Application Code (8005h) In this register, the CFP module shall identify what if any non-Ethernet Copper based PMD application which is supported. At the time of the writing, this application is undefined.

5.1.10 SONET/SDH Application Code (8006h) In this register, the CFP module shall identify what if any SONET/SDH PMD application is supported. Any CFP module which supports an application not including SONET/SDH such as Ethernet, OTN, Fibre Channel or other, shall record a “00h” to signify that the SONET/SDH application is undefined. Any CFP module which supports an application which includes SONET/SDH and additional applications such as Ethernet, OTN, Fibre Channel or other, shall record the value in this register which corresponds to the SONET/SDH application which is supported.

5.1.11 OTN Application Code (8007h) In this register, the CFP module shall identify what if any OTN PMD application is supported. Any CFP module which supports an application not including OTN such as SONET/SDH, Ethernet, Fibre Channel or other, shall record a “00h” to signify that the OTN application is undefined. Any CFP module which supports an application which includes OTN and additional applications such as SONET/SDH, Ethernet, Fibre Channel or other, shall record the value in this register which corresponds to the OTN application which is supported.



5.1.12 Additional Data Rate Capabilities (8008h)

5.1.13 Network and Host Lane Number (8009h) In this register, the CFP module shall indicate the numbers of lanes in the Network interface and Host interface. For example, in the case of a CFP module supporting 100GBASE-LR4 there are 4 lanes in the network (optical) interface, and 10 lanes in the host (CAUI) interface. the value “0” for lane number is considered undefined.

5.1.14 Media Type and Number (800Ah)

5.1.14.1 Media Type In this register, the CFP module shall identify the type of transmission media for the supported application.

5.1.14.2 Directionality In this register, the CFP module shall identify if supported application uses the same transmission media for the transmit/receive network interfaces (Bi-Directional) or if separate transmission media are required for the transmit and receive network interfaces.

5.1.14.3 Optical Multiplexing and De-Multiplexing In this register, the CFP module shall identify if optical multiplexing and optical de-multiplexing are supported within the module.

5.1.14.4 Active Fiber per Connector In this register, the CFP module shall identify the number of active fibers in an optical connector. For example, in a CFP supporting the 100GBASE-SR10 application using an MPO connector this register shall report ten active ferrules in use, or a value of “110h”.

5.1.15 Maximum Network Interface (Optical) Lane bit rate (800Bh) In this register, the CFP module shall identify maximum data rate supported per network interface lane. For more complex modulation schemes than OOK (on/off keying), the value reported shall be the bit rate and not the baud rate. The value stored in the register shall be based upon units of 0.1 Gbit/s. A value of all “0” in this register is considered undefined.

5.1.16 Maximum Host Interface Lane (Electrical) bit rate (800Ch) In this register, the CFP module shall identify maximum data rate supported per host interface lane. The value stored in the register shall be based upon units of 0.1 Gbit/s. The nominal lane rate suggested in the CFP MSA HW Specification is 10Gbit/s. However, various applications such as support for OTU4 and future applications will require higher lane rates. A value of all “0” in this register is considered undefined.



5.1.17 Single Mode Optical Fiber Length (800Dh) In this register, the CFP module shall identify the specified maximum reach supported by the application for transmission over single mode fiber. The value stored in the register shall be based upon units of 1km. For applications which operate over compensated transmission systems, it is suggested to enter an undefined value. A value of all “0” in this register is considered undefined.

5.1.18 Multimode Optical Fiber Length (800Eh) In this register, the CFP module shall identify the specified maximum reach supported by the application for transmission over OM3 multimode fiber. The value stored in the register shall be based upon units of 10m. A value of all “0” in this register is considered undefined.

5.1.19 Copper Cable Length (800Fh) In this register, the CFP module shall identify the specified maximum reach supported by the application for transmission over copper cable. The value stored in the register shall be based upon units of 10cm. A value of all “0” in this register is considered undefined.

5.1.20 Heat Sink Type (8010h) In this register, the CFP module shall identify if the top surface of the CFP MSA module has a flat top or integrated heat sink. The CFP MSA supports various networking applications which may require different thermal management solutions. The default top surface of the CFP MSA module is a flat top, however, some networking applications will benefit from an integrated heat sink. An integrated heat sink complies to the total module height requirements and shall not disrupt, disable nor damage any riding heat sink system. For further details, please refer to the CFP MSA Hardware specification.

5.1.21 Transmitter Spectral Characteristics (8011h)

5.1.21.1 Number of Wavelengths In this register, the CFP module shall identify the number of optical wavelengths which are supported per optical fiber output. The register is 4 bits in size. For the case of 100GBASE-LR4, the value would be four, or “0100h”. A value of all “0” in this register is considered undefined.

5.1.21.2 Number of Active Transmit Fibers In this register, the CFP module shall identify the number of optical fiber outputs which are supported. The register is 4 bits in size. For the case of 100GBASE-SR10, the value would be ten, or “1010h”. A value of all “0” in this register is considered undefined.



5.1.22 Minimum Wavelength per Active Fiber (8012h, 8013h) In this register, the CFP module shall identify the minimum wavelength of any supported optical fiber output per the application. The register is 16 bits in size with units of 25pm per value. For the case of 100GBASE-LR4 which has a minimum specified wavelength of 1294.53nm, the value would be 51,781, or “1100101001000101b”. A value of all “0” in this register is considered undefined.

5.1.23 Maximum Wavelength per Active Fiber (8014h, 8015h) In this register, the CFP module shall identify the maximum wavelength of any supported optical fiber output per the application. The register is 16 bits in size with units of 25pm per value. For the case of 100GBASE-LR4 which has a maximum specified wavelength of 1310.19nm, the value would be 52,408, or “1100110010110111b. A value of all “0” in this register is considered undefined.

5.1.24 Maximum per Channel Optical Width (8016h, 8017h) In this register, the CFP module shall identify the maximum optical channel wavelength width of any supported optical fiber output per the application. The register is 16 bits in size with units of 1pm per value. For the case of 100GBASE-LR4 which has a maximum specified optical wavelength width of 2.1nm for channel L3, the value would be 2100, or “0000100000110100b”. A value of all “0” in this register is considered undefined.

5.1.25 Device Technology 1 (8018h)

5.1.25.1 Laser Source Technology In this register, the CFP module shall identify the type of laser technology which is used. There is a register value for electrical/copper (non-laser) transmission, as well as additional reserved space for as of yet undefined laser types.

5.1.25.2 Transmitter Modulation Technology In this register, the CFP module shall identify the type of modulation technology which is used. There is a register value for electrical/copper (non-laser) transmission, as well as additional reserved space for as of yet undefined modulator types.

5.1.26 Device Technology 2 (8019h)

5.1.26.1 Wavelength Control In this register, the CFP module shall identify if the wavelength of the laser technology which is used includes an active wavelength control mechanism. Active wavelength control mechanism is defined to be a wavelength sensitive device which can be used to compare the actual transmitted wavelength from the expected transmitted wavelength. This register is a single bit with “0” signifying no control mechanism and “1” indicating the presence of such a mechanism within the CFP module.



5.1.26.2 Cooled Transmitter In this register, the CFP module shall identify if the transmitter is coupled to a cooling mechanism within the module. A popular implementation for such a coupled cooling mechanism is to mount a laser such that it is thermally coupled to a thermoelectric cooler which is controlled to keep the laser within a defined temperature range. If any cooling mechanism is present the transmitter is considered to be cooled. A transmitter is considered to be cooled even if the cooling mechanism is not always active. This register is a single bit with “0” signifying no cooling mechanism and “1” indicating the presence of such a cooling mechanism within the CFP module.

5.1.26.3 Wavelength Tunability In this register, the CFP module shall identify if the transmitted optical wavelength may be tuned over a specified spectral range. This register is a single bit with “0” signifying no tuning mechanism and “1” indicating the presence of such a tuning mechanism within the CFP module.

5.1.26.4 VOA Implemented In this register, the CFP module shall identify if the optical receiver implements a variable optical attenuator (VOA) within the optical receive chain. This register is a single bit with “0” signifying no VOA mechanism and “1” indicating the presence of such a VOA mechanism within the CFP module.

5.1.26.5 Detector Type In this register, the CFP module shall identify the type of detector technology which is used. There is a register value for undefined detector types.

5.1.26.6 EDC Enhanced Receiver In this register, the CFP module shall identify if the Clock and Data Recovery (CDR) circuitry within the CFP module receive path contains any electronic dispersion compensation (EDC) techniques to improve the receiver performance. It is recognized that there exist a variety of EDC techniques with varying performance enhancements and tradeoffs – this register does not convey any detail, only if the CFP module implements EDC within the receiver. This register is a single bit with “0” signifying no EDC mechanism and “1” indicating the presence of such an EDC mechanism within the CFP module.

5.1.27 Signal Code (801Ah)

5.1.27.1 Modulation Polarity In this register, the CFP module shall identify the polarity coding used in the optical modulation. There is a register value for Non-Return to Zero transmission, Return to Zero transmission as well as additional reserved space for as of yet undefined coding types. A value of all “0” in this register is considered undefined.



5.1.27.2 Signal coding In this register, the CFP module shall identify the signaling coding used in the optical modulation. There is a register space for various types of phase key signaling and quadrature amplitude modulation as well as additional reserved space for as of yet undefined signaling types. A value of all “0” in this register is considered undefined.

5.1.28 Absolute Maximum Total Optical Output Power per Connector (801Bh) In this register, the CFP module shall identify the maximum optical output power of any supported optical fiber output per the application. The register is 8 bits in size with units of 100 µW per value. A value of all “0” in this register is considered undefined.

5.1.29 Absolute Maximum Total Optical Input Power per Connector (801Ch) In this register, the CFP module shall identify the maximum optical input power of any supported optical fiber input per the application. The register is 8 bits in size with units of 100 µW per value. A value of all “0” in this register is considered undefined.

5.1.30 Maximum Power Dissipation (801Dh) In this register, the CFP module shall identify the maximum power dissipation of any supported application. The register is 8 bits in size with units of 200 mW per value. A value of all “0” in this register is considered undefined.

5.1.31 Maximum Power Consumption in Low Power Mode (801Eh) In this register, the CFP module shall identify the maximum power dissipation of the low power mode state. The low power mode state is described in detail in the CFP MSA Hardware specification. The register is 8 bits in size with units of 20 mW per value. A value of all “0” in this register is considered undefined.

5.1.32 Maximum Operating Case Temperature (801Fh) In this register, the CFP module shall identify the maximum operating case temperature specified of any supported application. The register is 8 bits in size with units of 1 degC per value. A value of all “0” in this register is considered undefined.

5.1.33 Minimum Operating Case Temperature (8020h) In this register, the CFP module shall identify the minimum operating case temperature specified of any supported application. The register is 8 bits in size with units of 1 degC per value. A value of all “0” in this register is considered to be defined as -50 degC. A value of all “1” in this register is considered to be undefined.

5.1.34 Vendor Name (8021h ~ 8030h) In this register, the CFP module shall identify the CFP module Vendor name in ASCII code. The vendor name is a 16 byte field that contains ASCII characters, left aligned and padded



on the right with ASCII spaces (20h). The vendor name shall be the full name of the corporation, a commonly accepted abbreviation of the name or the stock exchange code for the corporation. Vendor is the CFP Module Vendor.

5.1.35 Vendor OUI (8031h, 8032h, 8033h) The vendor organizationally unique identifier field (vendor OUI) is a 3 byte field that contains the IEEE Company Identifier for the transceiver vendor (as opposed to the OUI of any third party ICs which may be used therein). Bit order for the OUI follows the format of IEEE802.3 2000 Clause 22.2.4.3.1 and is therefore reversed in comparison to other non-volatile registers. A value of all zero in the 3 byte field indicates that the Vendor OUI is unspecified. Vendor is the CFP Module Vendor.

5.1.36 Vendor Part Number (8034h ~ 8043h) The vendor part number (vendor PN) is a 16 byte field that contains ASCII characters, left aligned and padded on the right with ASCII spaces (20h), defining the vendor part number or product name. A value of all zero in the 16 byte field indicates that the Vendor OUI is unspecified. Vendor is the CFP Module Vendor.

5.1.37 Vendor Serial Number (8044h ~ 8053h) The vendor revision number (vendor SN) is a 16 byte field that contains ASCII characters, left aligned and padded on the right with ASCII spaces (20h), defining the vendor’s serial number. A value of all zero in the 16 byte field indicates that the Vendor SN is unspecified. Vendor is the CFP Module Vendor.

5.1.38 Date Code (8054h ~ 805Bh) The date code is an 8 byte field that contains the vendor’s date code in ASCII characters. A value of all zero in the 8 byte field indicates that the Vendor date code is unspecified. Vendor is the CFP Module Vendor.

Register Date Value Example of March 10, 2009. (Bit 7 = MSB, bit 0 = LSB)

8058 2 8059 0 805A 0 805B 9 805C 0 805D 3 805E 1 805F 0



5.1.39 Lot Code (805Ch, 805Dh) The lot code is an 8 byte field that contains the vendor’s lot code in ASCII characters. A value of all zero in the 8 byte field indicates that the Vendor lot code is unspecified. Vendor is the CFP Module Vendor.

5.1.40 CLEI Code (805Eh ~ 8067h) The CLEI code is a 10 byte field that contains the Common Language Equipment Identifier code in ASCII characters. A value of all zero in the 10 byte field indicates that the CLEI code is unspecified.

5.1.41 MSA Revision Number (8068h)

5.1.41.1 CFP MSA Hardware Specification Revision Number The CFP MSA Hardware Specification Revision number (MSA HW rev) is a 2 byte field in the format of “x.y”. The “x” value is contained within the lower address. The “y” value is contained in the upper address. A value of all zero in the 2 byte field indicates that the MSA HW rev number is unspecified.

5.1.42 Module Vendor Hardware Revision Number (Optional) (8069h) The CFP Vendor Hardware Revision number (vendor HW rev) is a 2 byte field in the format of “x.y”. The “x” value is contained within the lower address. The “y” value is contained in the upper address. A value of all zero in the 2 byte field indicates that the vendor HW rev number is unspecified. This field is optional.

5.1.43 Module Vendor Firmware/Software Revision Number (Optional) (806B) The CFP Vendor Firmware Revision number (vendor FW rev) is a 2 byte field in the format of “x.y”. The “x” value is contained within the lower address. The “y” value is contained in the upper address. A value of all zero in the 2 byte field indicates that the vendor FW rev number is unspecified. This field is optional.

5.1.44 Diagnostic Monitoring Type (806Dh) The Diagnostic Monitoring Type is a one byte field with 8 single bit indicators describing how diagnostic monitors are implemented in the particular transceiver. Bit indicators are detailed at the register 8086h.

5.1.45 Diagnostic Monitoring Capability 1 (806Eh) This register contains bit indicators describing what digital diagnostic functions are implemented in the particular transceiver at module level.

5.1.46 Diagnostic Monitoring Capability 2 (806Fh) This register contains bit indicators describing what digital diagnostic functions are implemented in the particular transceiver at network lane level.



5.1.47 Module Enhanced Options (8070h) This register is a one-byte field containing bit indicators describing what other enhance optional functions are implemented in the particular transceiver module. Three bits are specified for FEC controls.

5.1.48 Maximum High-Power-up Time (8071h) This register is an 8-bit unsigned value of maximum High-Power-up time provided by module vendor per its particular implementation.

5.1.49 Maximum TX-Turn-on Time (8072h) This register is an 8-bit unsigned value of maximum TX-Turn-on time provided by module vendor per its particular implementation.

5.1.50 CFP NVR 1 Checksum (807Fh) This register is the 8 bit unsigned result of the checksum of all of the MDIO register LSB contents from addresses 1.8000 to 1.807E inclusive. Note that all the reserved registers have zero value contribution to the calculation of this Checksum.



Table 7: CFP Non Volatile Register Table 1 Details

CFP Non-Volatile Register Table1 Details Hex Add

Size Access Type

Bit Register Name Bit Filed Name

Description LSB Unit

Base ID Information 8000 1 RO 7~0 Module Identifier 00h: Unknown or unspecified,

01h: GBIC, 02h: Module/connector soldered to motherboard 03h: SFP 04h: 300 pin XSBI, 05h: XENPAK 06h: XFP, 07h: XFF, 08h: XFP-E, 09h: XPAK, 0Ah: X2, 0Bh: DWDM-SFP, 0Ch: QSFP, 0Dh: QSFP+, 0Eh: CFP, 0Fh ~ FFh : Reserved

N/A

Extended Identifier N/A 7~6 Power Class 00: Power Class 1 Module (8 W max),

01: Power Class 2 Module (16 W max), 10: Power Class 3 Module (24 W max), 11: Power Class 4 Module (Higher than 24W)

N/A

5~4 Lane Ratio Type 00: Network lane : Host lane = 1 : n (Mux type) , 01: Network lane : Host lane = n : m (Gear Box type) 10: Network lane : Host lane = n : n (Parallel type) 11: Reserved

N/A

3~1 WDM Type 000:non WDM, 001:CWDM, 010:LANWDM, 011:DWDM on 200G-grid, 100:DWDM on 100G-grid, 101:DWDM on 50G-grid, 110:DWDM on 25G-grid, 111:Other type WDM

N/A

8001 1 RO

0 CLEI Presence 0: No CLEI code present, 1: CLEI code present

N/A

8002 1 RO 7~0 Connector Type Code 00h: Undefined, 01h : SC, 07h : LC, 08h : MT-RJ, 09h : MPO Other Codes : Reserved

N/A




Size Access Type



8003 1 RO 7~0 Ethernet Application Code 00h: Undefined type, 01h: 100GE SMF 10km, 02h: 100GE SMF 40km, 03h: 100GE MMF 100m OM3, 04h: FFU, 05h: 40GE SMF 10km, 06h: 2x40GE SMF 10km, 07h: 40GE MMF 100m OM3, 08h: 2x40GE MMF 100m OM3 09h: 3x40GE-LR1 SMF 10km, 0Ah: 40GE-SR4 MMF 100m OM3, 0Bh: 2x40GE-SR4 MMF 100m OM3, 0Ch: 3x40GE-SR4 MMF 100m OM3, 0Dh: 40GE-CR4 Copper 0Eh: 100GE-CR10 Copper 0Fh~FFh:Reserved

N/A

8004 1 RO 7~0 Fiber Channel Application Code

00h: Undefined type N/A

8005 1 RO 7~0 Copper Link Application Code 00h: Undefined type N/A 8006 1 RO 7~0 SONET/SDH Application Code 00h: Undefined type,

01h: VSR2000-3R2, 02h: VSR2000-3R3, 03h: VSR2000-3R5, 04h ~ 0FFh: Reserved.

N/A

8007 1 RO OTN Application Code 00h: Undefined type, 01h: VSR2000-3R2F, 02h: VSR2000-3R3F, 03h: VSR2000-3R5F, 04h ~ 0FFh: Reserved.

N/A

Additional Capable Rates Supported

Additional application rates module supporting

N/A

7~5 Reserved N/A 4 111.8 Gb/s 0: Un-supported, 1: Supported. N/A 3 103.125 Gb/s 0: Un-supported, 1: Supported. N/A 2 41.25 Gb/s 0: Un-supported, 1: Supported. N/A 1 43 Gb/s 0: Un-supported, 1: Supported. N/A

8008 1 RO

0 39.8 Gb/s 0: Un-supported, 1: Supported. N/A Network and Host Lane

Number For optical transceivers, "Network" = Optical, "Host" in most cases mean "Electrical".

N/A

7~4 Network Lane Number Number of Network Data I/O. 4 bit value of channel number

N/A

8009 1 RO

3~0 Host Lane Number Number of high speed Host Data I/O. 4 bit value of channel number

N/A

Media Type Number N/A 7~6 Media Type 00b: SMF ,

01b: MMF (OM3), 10b: Reserved , 11b: Copper

N/A

5 Directionality 0h: Normal, 1h: BiDi

N/A

4 Optical Multiplexing and De-multiplexing

0h: Without optical MUX/DEMUX 1h: With optical MUX/DEMUX

N/A

800A 1 RO

3~0 Active Fiber per Connector Active Fiber number per connector (normal = 1, 4 lane type = 4 or 8, 10 lane type = 10). 4 bit value.

N/A

800B 1 RO 7~0 Maximum Network (Optical) lane bit rate

8-bit value x 0.2 Gb/s 0.2 Gb/s




Size Access Type



800C 1 RO 7~0 Maximum Host (Electrical) lane bit rate

8-bit value x 0.1 Gb/s 0.1 Gb/s

800D 1 RO 7~0 Single Mode Optical Fiber Length

8-bit value x 1 km for single mode fiber length

1 km

800E 1 RO 7~0 Multi mode optical fiber length 8-bit value x 10 m for multi mode fiber length

10 m

800F 1 RO 7~0 Copper Cable Length 8-bit value x 10 cm for copper cable length 10 cm

Heat Sink Type N/A 7~1 Reserved N/A

8010 1 RO

0 Heat Sink Type 0: Flat top 1: Integrated heat sink

N/A

Transmitter Spectral Characteristics

N/A

7~4 Number of Wavelengths per active Transmit Fiber

4 bit value. 0000b: Undefined.

N/A

8011 1 RO

3~0 Number of Active Transmit Fibers

4-bit value. 0000b: Undefined.

N/A

8012 2 RO 7~0 Minimum Wavelength per Active Fiber

16-bit unsigned value x 0.025 nm. (MSB is at 8012h, LSB is at 8013h).

0.025 nm

8014 2 RO 7~0 Maximum Wavelength per Active Fiber

16-bit unsigned value x 0.025 nm. (MSB is at 8014h, LSB is at 8015h).

0.025 nm

8016 2 RO 7~0 Maximum per channel optical width

Guaranteed range of laser wavelength. 16-bit unsigned value x 1 pm. MSB is at 8016h, LSB is at 8017h.

1 pm

Device Technology 1 N/A 7~4 Laser Source Technology 0000b:VCSEL,

0001b:FP, 0010b:DFB, 0011b:DBR, 0100b:Copper, 0101b ~ 1111b:Reserved

N/A 8018 1 RO

3~0 Transmitter modulation technology

0000b:DML, 0001b:EML, 0010b:InP-MZ, 0011b:LN-MZ 0100b:Copper, 0101b ~ 1111b:Reserved

N/A

Device Technology 2 N/A 7 Wavelength control 0: No wavelength control,

1: Active wavelength control N/A

6 Cooled transmitter 0: Un-cooled transmitter device, 1: Cooled or Semi-cooled transmitter

N/A

5 Tunability 0: Transmitter not Tunable, 1: Transmitter Tunable

N/A

4 VOA implemented 0: Detector side VOA not implement, 1: Detector side VOA implement

N/A

3~2 Detector Type 00: Undefined, 01: PIN detector, 10: APD detector 11: Optical Amplifier + PIN detector

N/A

1 CDR with EDC 0: CDR without EDC, 1: CDR with EDC

N/A

8019 1 RO

0 Reserved N/A 801A 1 RO Signal Code N/A




Size Access Type



7~6 Modulation Polarity 00b:Undefined 01b:NRZ, 10b:RZ, 11b:Reserved

N/A

5~2 Signal coding 0000b:non PSK, 0001b:ODB, 0010b:DPSK, 0011b:QPSK, 0100b:DQPSK, 0101b:DPQPSK, 0110~1010b:Reserved, 1011b:16QAM, 1100b:64QAM, 1101b:256QAM, 1110~1111b:Reserved

N/A

1~0 Reserved N/A 801B 1 RO 7~0 Absolute Maximum Total

Optical Output Power per Connector

Unsigned 8 bit value * 100 uW.

100 uW

801C 1 RO 7~0 Absolute Maximum Optical Input Power per Channel

Unsigned 8 bit value * 100 uW. 100 uW

801D 1 RO 7~0 Maximum Power Consumption Unsigned 8 bit value * 200 mW. 200 mW

801E 1 RO 7~0 Maximum Power Consumption in Low Power Mode

Unsigned 8 bit value * 20 mW. 20 mW

801F 1 RO 7~0 Maximum Operating Case Temp Range

Unsigned 8 bit value of * 1 degC. 0 ~ 100 degC.

1 degC

8020 1 RO 7~0 Minimum Operating Case Temp Range

Signed 8 bit value. Increments of * 1 degC valid –40 ~ +40 degC.

1 degC

8021 16 RO 7~0 Vender Name Vendor (manufacturer) Name in any combination of letters and/or digits in ASCII code.

N/A

8031 3 RO 7~0 Vendor OUI The vendor organizationally unique identifier field (vendor OUI) is a 3-word field that contains the IEEE Company Identifier for the vendor.

N/A

8034 16 RO 7~0 Vendor Part Name Vendor (manufacturer) part name in any combination of letters and/or digits in ASCII code.

N/A

8044 16 RO 7~0 Vender Serial number Vendor (manufacturer) serial number in any combination of letters and/or digits in ASCII code.

N/A

8054 8 RO 7~0 Date Code Vendor (manufacturer) date code in ASCII characters, in the format YYYYMMDD (e.g., 20090310 for March 10, 2009). One character at each MDIO address.

N/A

805C 2 RO 7~0 Lot Code Lot code in any combination of letters and/or digits in ASCII code.

N/A

805E 10 RO 7~0 CLEI Code CLEI Code in any combination of letters and/or digits in ASCII code.

N/A

8068 1 RO 7~0 MSA Version Number This register indicates the CFP MSA version number supported by the transceiver. The 8 bits are used to represent the version number times 10. This yields a max of 25.5 revisions.

N/A

8069 2 RO 7~0 Vendor hardware version number (Optional)

A two-register number in the format of x.y with x at lower address and y at higher

N/A




Size Access Type



address

806B 2 RO 7~0 Vendor soft/firmware version number (Optional)

A two-register number in the format of x.y with x at lower address and y at higher address

N/A

Diagnostic Monitoring Type N/A 7~4 Reserved N/A

3 Received power measurement type

0:OMA, 1:Average Power N/A

2 Transmitted power measurement type

0:OMA, 1:Average Power N/A

806D 1 RO

1~0 Reserved N/A Diagnostic Monitoring

Capability 1 Module level DDM capability N/A

7~6 Transceiver auxiliary monitor 2 00b: Not supported. 01b ~ 11b: TBD.

N/A

5~4 Transceiver auxiliary monitor 1 00b: Not supported. 01b ~ 11b: TBD.

N/A

3 Reserved N/A 2 Transceiver SOA bias current

monitor 0: not supported, 1: supported N/A

1 Transceiver power supply voltage monitor

0: not supported, 1: supported N/A

806E 1 RO

0 Transceiver temperature monitor 0: not supported, 1: supported N/A Diagnostic Monitoring

Capability 2 Per lane DDM capability N/A

7~4 Reserved N/A 3 Channel received power monitor 0: not supported, 1: supported N/A 2 Channel laser output power

monitor 0: not supported, 1: supported N/A

1 Channel laser bias current monitor


806F 1 RO

0 Channel laser temperature monitor


Module Enhanced Options N/A 7~4 Reserved N/A

3 Automatic Decision Voltage and Phase control functions implemented

Supported for every network channel. 0: not supported, 1: supported

N/A

2 Decision Threshold Voltage control functions implemented


N/A

1 Decision Phase control functions implemented


N/A

8070 1 RO

0 Reserved N/A 8071 1 RO 7~0 Maximum High-Power-up Time Fully power up time required by module.

Unsigned 8-bit value * 1 s. Use 1 s if the actual time is less than 1 s.

1 s

8072 1 RO 7~0 Maximum TX-Turn-on Time Maximum Time required to turn on all TX channels and to let them reach stability. Unsigned 8-bit value * 10 ms. Use 10 ms if it is less than 10 ms.

10 ms

8073 12 RO Reserved N/A 807F 1 RO 7~0 CFP NVR 1 Checksum This is the 8-bit unsigned result of the 8-bit

sum of all MDIO register contents from address 1.8000 through 1.807E inclusive.

N/A



5.2 CFP NVR Table 2: Extended ID Information This whole table contains alarm and warning thresholds for the digital diagnostic monitoring A/D measurement values, listed in registers 8080h through 80C8h. Each register field is a 16-bit value with the type of signed and unsigned depending upon the A/D quantity. Each register field uses two addresses with MSB at lower address. Each A/D value has a corresponding high alarm, low alarm, high warning and low warning threshold. These factory-preset values allow the user to determine when a particular value is out side of “normal” limits as determined by the transceiver manufacturer. It is assumed that these values will vary with different technologies and different implementations. All of the alarm and warning thresholds are listed in Table 8: CFP Non-Volatile Register Table 2 Details.

Table 8: CFP Non-Volatile Register Table 2 Details

CFP Non-Volatile Register 2 Details Hex Add

Size Access Type



Alarm/Warning Threshold Registers 8080 2 RO 7~0 Transceiver Temp High Alarm Threshold 8082 2 RO 7~0 Transceiver Temp Low Alarm Threshold 8084 2 RO 7~0 Transceiver Temp High Warning

Threshold 8086 2 RO 7~0 Transceiver Temp Low Warning

Threshold

These thresholds are a signed 16-bit integer with LSB = 1/256 of a degree Celsius representing a range from -128 to + 127 255/256 degree C. MSA valid range is between –40 and +125C." MSB stored at low address, LSB stored at high address.

1/256 degC

8088 2 RO 7~0 VCC High Alarm Threshold 808A 2 RO 7~0 VCC High Warning Threshold 808C 2 RO 7~0 VCC Low Warning Threshold 808E 2 RO 7~0 VCC Monitor Low Alarm Threshold

These thresholds are an unsigned 16-bit integer with LSB = 0.1 mV, representing a range of voltage from 0 to 6.5535 V. MSB stored at low address, LSB stored at high address.

0.1 mV

8090 2 RO 7~0 SOA Bias Current High Alarm Threshold 8092 2 RO 7~0 SOA Bias Current High Warning

Threshold 8094 2 RO 7~0 SOA Bias Current Low Warning

Threshold 8096 2 RO 7~0 SOA Bias Current Low Alarm Threshold

These threshold values are an unsigned 16-bit integer with LSB = 2 uA, representing a range of current from 0 to 131.072 mA. MSB stored at low address, LSB stored at high address.

2 uA

8098 2 RO 7~0 Auxiliary 1 Monitor High Alarm Threshold

TBD

809A 2 RO 7~0 Auxiliary 1 Monitor High Warning Threshold

TBD

809C 2 RO 7~0 Auxiliary 1 Monitor Low Warning Threshold

TBD

809E 2 RO 7~0 Auxiliary 1 Monitor Low Alarm Threshold

TBD

TBD

80A0 2 RO 7~0 Auxiliary 2 Monitor High Alarm Threshold

TBD

80A2 2 RO 7~0 Auxiliary 2 Monitor High Warning Threshold

TBD

80A4 2 RO 7~0 Auxiliary 2 Monitor Low Warning Threshold

TBD

TBD



CFP Non-Volatile Register 2 Details Hex Add

Size Access Type



80A6 2 RO 7~0 Auxiliary 2 Monitor Low Alarm Threshold

TBD

80A8 2 RO 7~0 Laser Bias Current High Alarm Threshold

80AA 2 RO 7~0 Laser Bias Current High Warning Threshold

80AC 2 RO 7~0 Laser Bias Current Low Warning Threshold

80AE 2 RO 7~0 Laser Bias Current Low Alarm Threshold

Alarm and warning thresholds for measured laser bias current. Reference Register A207h Description for additional information. MSB stored at low address, LSB stored at high address.

rf. A207h

80B0 2 RO 7~0 Laser Output Power High Alarm Threshold

80B2 2 RO 7~0 Laser Output Power High Warning Threshold

80B4 2 RO 7~0 Laser Output Power Low Warning Threshold

80B6 2 RO 7~0 Laser Output Power Low Alarm Threshold

Alarm and warning thresholds for measured laser output power. Reference Register A208h Description for additional information. MSB stored at low address, LSB stored at high address.

rf. A208h

80B8 2 RO 7~0 Laser Wavelength High Alarm Threshold 80BA 2 RO 7~0 Laser Wavelength High Warning

Threshold 80BC 2 RO 7~0 Laser Wavelength Low Warning

Threshold 80BE 2 RO 7~0 Laser Wavelength Low Alarm Threshold

These threshold values are a signed 16-bit integer with LSB = 1 pico meter, representing a range of wavelength deviation from -32.767 to +32.767 nm, deviated from the nominal center wavelength. Though the implementation of these thresholds is vendor dependent, they are often derived from measured laser temperature. MSB stored at low address, LSB stored at high address.

1

80C0 2 RO 7~0 Receive Optical Power High Alarm Threshold

80C2 2 RO 7~0 Receive Optical Power High Warning Threshold

80C4 2 RO 7~0 Receive Optical Power Low Warning Threshold

80C6 2 RO 7~0 Receive Optical Power Low Alarm Threshold

Alarm and warning thresholds for measured received input power. Reference Register A208h Description for additional information. MSB stored at low address, LSB stored at high address.

rf. A208h

80C8 55 RO 7~0 Reserved 00h 80FF 1 RO 7~0 CFP NVR 2 Checksum This is the 8-bit unsigned result of the 8-

bit sum of all MDIO register contents from address 1.8080 thru 1.80FE, inclusive

N/A

5.3 CFP Control, Status, and DDM Register Table Table 9: Control, Status, and DDM Register Details lists all the registers in several distinctive groups in terms of their function. All of the registers in this Table use 16-bit data format. The description of each register field consists of three parts. The “Description” column of this Table provides some rudimentary information about each register. For more involved description, a dedicated section of discussion is presented in “CFP Control and Signaling Theory”. The sections presented in this chapter, provides additional information whenever it is appropriate.



Many CFP Control, Status and DDM registers are application specific. The MSA intent is to identify registers. MSA compliant modules need not support all registers defined here. MSA compliant modules shall not use the specified registers for alternate purposes.

5.3.1 CFP Command/Setup Registers This group includes 8 registers that user may need to access at the beginning of a MDIO session.

5.3.1.1 Password Entry and Password Change (A000h and A002h) This register field is a 32-bit data field with all the details described in §4.9.

5.3.1.2 NVR Access Control (A004h) This is a one address register with all the details documented in §4.8.

5.3.1.3 PRG_CNTLs Function Select (A005h, A006, A007h) Registers A005h through A007h are the programmable control function selecting registers. Each register is used to assign a particular soft control function contained in CFP Control Registers A011h, A012h, and A013h. Bits 15 to 12 is a 4-bit data field, Control Register Bit Number, specifying which bit of the CFP Control Register is mapped onto a programmable control pin. Bits 11 through 0 are a 12-bit field, Control Register Address Offset, representing the lower 12-bit address of these CFP Control Registers in the A000 Page. The MSA default function is assigned to each pin when this Control Register Address Offset is set to the lower 12-bit address of the register itself, while the value of Control Register Bit Number does not matter. Note if a soft control function requires multiple bits, such as RX MCLK1, RX MCLK0, two programmable control pins shall be selected correspondingly to accomplish this purpose. For those soft control functions that requires more 3 bits, only 3 pins can be programmed maximally with limited function.

5.3.1.4 PRG_ALRMs Source Select (A008h, A009h, A00Ah) Registers A008h through A00Ah are the programmable alarm function selecting registers. Each register is used to assign a particular soft alarm function contained in CFP alarm/status Registers A016h through A026h, except those reserved. Bits 15 to 12 is a 4-bit data field, Alarm Register Bit Number, specifying which bit of the CFP Alarm/Status Register is mapped onto a programmable alarm pin. Bits 11 through 0 are a 12-bit field, AlarmRegister Address Offset, representing the lower 12-bit address of these CFP Alarm/Stutas Registers in the A000 Page. The MSA default function is assigned to each pin when this Alarm Register Address Offset is set to the lower 12-bit address of the register itself, while the value of Alarm Register Bit Number does not matter.



5.3.1.5 Module Bi-/Uni- Directional Operating Mode Select (A00Bh) CFP module users may seek special applications where the CFP module may be used for uni-directional operation. In addition to the “Description” column of this register more information is referenced to §4.5 Special Mode of Operation.

5.3.2 CFP Control Registers (A010h, A011h, A012h, A013h) General Control Register (A010h) provides an alternative to hardware control pins on the connector over MDIO interface. The Soft TX Control (A011h), Soft RX Control (A012h), and Individual Ch Soft TX_DIS Control (A013h) provide full control over MDIO interface. While there is no hardware equivalent, most of the functions can be mapped onto PRG_CNTLs pins. More information is documented in the “Description” column in Table 9.

5.3.3 Module State Register (A016h) Module State register is provided with both real time states of the module operation (bits 15~12) and the latched equivalent bits (bits 8 ~ 0) in the same register to enable user exploring the status and history of the module during the startup and turn-off processes. Its applications have been discussed in detail in §4.1 CFP Module Working States.

5.3.4 Data_Ready (A017h) This specific register was added to indicate the readiness of the MDIO interface and the availability of DDM data. If the data word host reads matches the pattern “89ABh”, then the Data_Ready condition is met. When this condition is met module shall also assert the Data_Ready bit in Module General Status register (bit 3).

5.3.5 Alarm/Status Summary Registers (A018h, A019h, A020h) This set of registers enable the fast diagnosis of locating the origin of an alarm/status/fault condition for the host in response to a global alarm interrupt request generated by GLB_ALRMn pin. This set of registers is at the top level of the global alarm aggregation hierarchy. User can use this set of registers as the top-level index for tracking down the origin of the interrupt request. Detailed discussion of this topic shall be found in §4.6 Global Alarm System Logic.

5.3.6 Module Alarm/Status Registers (A01Dh, A01Eh, A01Fh, A020h) This set of registers is the main source of module status and alarm/warning conditions. It contains the following 4 registers.

5.3.6.1 Module General Status In this register, bits 15 ~ 6 are the mirrored digital states of the hardware connector pins, including both inputs and outputs. The allocation of these pins provides user a means to exam the status of hardware pin status over MDIO interface.



Bit 5 and 4 are the lost of lock signal summaries over all the installed network channels – the bits that help the further allocation of the link error sources. Bit 3 is the flag bit for register A017h Data_Ready. Its function has been described in §5.3.4 Data_Ready (A017h). Bits 2 and 1 are the soft version of the default functions of PRG_ALRM2 and PRG_ALRM3, respectively during startup and turn-off processes. They report the MOD_READY and HIPWR_ON conditions even PRG_ALRM2 and PRG_ALRM3 are programmed for other functions. Bit 0 is the indicator of “Initialize Complete” as the mirror bit of GLB_ALRMn during startup and turn-off processes. (Its role is mute and it will be subject to deletion.)

5.3.6.2 Module Fatal Fault Status Register A01Eh in Table 9 completely describes its function.

5.3.6.3 Module Alarms and Warnings 1 Register A01Fh in Table 9 completely describes its function.

5.3.6.4 Module Alarms and Warnings 2 Register A020h in Table 9 completely describes its function.

5.3.7 Module Alarm/Status Latch Registers (A023h, A024h, A025h, A026h) All the registers in this group contain the latched version of Module Alarm/Status Registers described above. Global Alarm uses these latched bits to report to host as depicted by Figure 9: Global Alarm Signal Aggregation. All of the bits in these registers are cleared upon host reading.

5.3.8 Module Alarm/Status Enable Registers (A029h, A02Ah, A02Bh, A02Ch) All the registers in this group are the enable registers for Module Alarm/Status Register group (A01Dh, A01Eh, A01Fh, A020h). These registers allow user to enable or disable any particular alarm/warning/status/fault bits to contribute to GLB_ALRMn.

5.3.9 Analog AD Value Registers Three analog quantities, Module Temperature Monitor A/D Value, Module Power Supply 3.3V Monitor A/D Value, and SOA Bias Current A/D Value, are supported by this group of registers. These monitoring quantities are at module level and non-channel specific. Two additional auxiliary monitoring quantities are specified for vendor and user to use.



Table 9: Control, Status, and DDM Register Details

Control, Status, and DDM Register Details Hex Add

Size Access Type


Description Init Value

CFP Command/Setup Registers A000 2 WO Password Entry Password for MDIO register access

control. 2-word value. MSW is in lower address.

0000h0000h

A002 2 WO 15~0 Password Change New password entry. A 2-word value. MSW is in lower address.

0000h0000h

NVR Access Control CFP command parameter for NVR Save/Restore control

0003h

RO 15~8 Reserved 00h RW 7~6 NVR Section Code 00: CFP NVR 1 - requires vendor password

01: CFP NVR 2 - requires vendor password10: User NVR - requires user password 11: Vendor NVR - requires vendor password

00b

RW 5 Command 0: Save the specified NVR section, 1: Restore the specified NVR section,

0

RO 4 Reserved 0 RO/LH 3~2 Command Status 00: Idle.

01: Command completed successfully. 10: Command in progress. 11: Command failed.

00b

A004 1

RW 1~0 Extended Command 11 = R/W whole table of NVR contents. Other: reserved.

11b

RW PRG_CNTL3 Function Select Selects which control register and bit are associated with PRG_CNTL3.

0005h

15~12

Control Register Bit Number A 4-bit unsigned value indicating the bit number of any CFP Control register the Control Register Address Offset points to.

0

A005 1

11~0 Control Register Address Offset The lower 12-bit address of the CFP Control Registers on Page A000, e. g., 011h means A011h. When this address points to this register, that is, 005h, the MSA default function of Hardware Interlock MSB is selected.

005h


0006h

15~12


0

A006 1

11~0 Control Register Address Offset The lower 12-bit address of the CFP Control Registers on Page A000, e. g., 011h means A011h. When this address points to this register, that is, 006h, the MSA default function of Hardware Interlock LSB is selected.

006h


0007h

15~12


0

A007 1

11~0 Control Register Address Offset The lower 12-bit address of the CFP Control Registers on Page A000, e. g., 011h means A011h. When this address points to this register, that is, 007h, the MSA default function of TRXIC_RSTn, TX & RX ICs reset is selected.

007h




Size Access Type



RW PRG_ALRM3 Source Select Select which alarm source register and which bit are associated with PRG_ALRM3.

0008h

15~12

Alarm Register Bit Number A 4-bit unsigned value representing the selected bit in the CFP Alarm register the Alarm Register Address Offset points to.

0b

A008 1

11~0 Alarm Register Address Offset The lower 12-bit address of the CFP Alarm Register on Page A000, e. g., 01Eh means A01Eh. If this value is set to the lower 12-bit address of this register, that is, 008h, then MSA default function MOD_READY (Module finishes and exits Initialize state) is selected.

008h

RW PRG_ALRM2 Source Select Select which alarm source register and which bit are associated with PRG_ALRM2. Number 15 is always for MSA default function.

0009h

15~12


0b

A009 1

11~0 Alarm Register Address Offset The lower 12-bit address of the CFP Alarm Register on Page A000, e. g., 01Eh means A01Eh. If this value is set to the lower 12-bit address of this register, that is, 009h, then MSA default function HIPWR_ON (Module finishes and exits Hi-Power-on state) is selected.

009h

RW PRG_ALRM1 Source Select Select which alarm source register and which bit are associated with PRG_ALRM1. Number 15 is always for MSA default function.

000Ah

15~12


0b

A00A 1

11~0 Alarm Register Address Offset The lower 12-bit address of the CFP Alarm Register on Page A000, e. g., 01Eh means A01Eh. If this value is set to the lower 12-bit address of this register, that is, 00Ah, then MSA default function RXS (RX XDR Lock indicator) is selected.

00000b

A00B 1 RW Module Bi-/Uni- Directional Operating Mode Select

0000h

15~3 Reserved 0 2~0 Module Bi/uni-direction mode Select 000: Normal bidirectional mode

001: Uni-direction TX only mode 010: Uni-direction RX only mode 011: Special bidirectional mode 100~111: Reserved

000b

A00C 4 RO Reserved 0 CFP Control Registers

Module General Control 0 RW/SC 15 Soft Module Reset Register bit for module reset function. This

bit is self-clearing. Internally, the bit is OR'ed with hw reset pin*. 1: Module Reset asserted.

0 A010 1

RW 14 Soft TX Disable Register bit for TX Disable function. OR'ed with hw TX_DIS pin*. 1: Asserted.

0




Size Access Type



RW 13 Soft Mod Low Power Register bit for module low power function. OR'ed with hw MOD_LOPWR pin. 1: Asserted.

0

RW 12 Soft PRG_CNTL3 Control Register bit for PRG_CNTL3 control function. OR'ed with hw pin. 1: Asserted.

0


0


0

RO 9~0 Reserved Note bit 0 is reserved ever for PRG_CNTLs default functins

0

Soft TX Control This control acts upon all the channels. 0 15 Reserved Number 15 is reserved for PRG_CNTLs

default functions 0

14 TX PRBS Enable 0:Normal operation, 1:PRBS mode 13 TX PRBS Pattern 1 00:2^7, 01:2^15, 10:2^23, 11:2^31

00b

12 TX PRBS Pattern 0 0 11 TX De-skew Enable 0:Normal, 1:Disable 0 10 TX FIFO Reset 0:Normal operation, 1:Reset 0 9 TX Auto FIFO Reset 0:Normal operation, 1:Reset 0 8 TX Reset 0:Normal operation, 1:Reset 0 7 TX MCLK1 6 TX MCLK0

00:1/8, 01:1/32, 10:1/16, 11:disable 00b

5~4 Reserved 00b 3 Rate Select 2 (10G lane rate) 2 Rate Select 1 1 Rate Select 0

000:GbE=10.31, 001:SDH=9.95, 010:OTU3=10.7 011:OTU4=11.2, 100~111:Reserved

000b

A011 1 RW

0 Reference CLK rate Select 0:1/16, 1:1/64 0 1 Soft RX Control This control acts upon all the channels. 0000h

15 Reserved 14 RX PRBS Enable 0:Normal operation, 1:PRBS mode 0 13 RX PRBS Pattern 1 12 RX PRBS Pattern 0

00:2^7, 01:2^15, 10:2^23, 11:2^31 00b

11 RX Lock RX_MCLK to Reference CLK

0:Normal operation, 1:Lock RX_MCLK to REFCLK

0b

10~9 Reserved 000b 8 RX Reset 0:Normal operation, 1:Reset 0b 7 RX MCLK1 6 RX MCLK0

00:1/8, 01:1/32, 10:1/16, 11:disable 00b

5~4 Reserved 00b 3 Active Decision Voltage and Phase

function 0:not active, 1:active 0

2 Decision Threshold Voltage control function

0:not active, 1:active 0

1 Decision Phase control function 0:not active, 1:active 0

A012 1 RW

0 Reserved 0 Individual Ch Soft TX_DIS Control This register acts upon individual

channels. 0000h

15 Reserved 0 14~1

2 Reserved

11 ch 11 Disable 0:Normal, 1:Disable 0 10 ch 10 Disable 0:Normal, 1:Disable 0 9 ch 9 Disable 0:Normal, 1:Disable 0 8 ch 8 Disable 0:Normal, 1:Disable 0

A013 1 RW

7 ch 7 Disable 0:Normal, 1:Disable 0




Size Access Type



6 ch 6 Disable 0:Normal, 1:Disable 0 5 ch 5 Disable 0:Normal, 1:Disable 0 4 ch 4 Disable 0:Normal, 1:Disable 0 3 ch 3 Disable 0:Normal, 1:Disable 0 2 ch 2 Disable 0:Normal, 1:Disable 0 1 ch 1 Disable 0:Normal, 1:Disable 0 0 ch 0 Disable 0:Normal, 1:Disable 0

A014 2 RO Reserved 0000h Module State Register

Module State CFP Startup and Turn-off status. Both real time and latched status register.

0000h

RO 15~12

Current State 0000: Default value 0001: Initialize 0010: Low-Power 0011: High-Power-up 0100: TX-Off 0101: TX-Turn-on 0110: Ready 0111: Fault 1000: TX-Turn-off 1001: High-Power-Down

0000b

RO 11~9 Reserved 0 RO/LH/C

OR 8 High-Power-down Detected 0 or 1: Has not or has been in the state

since last reset 0

RO/LH/COR

7 TX-Turn-off State Detected 0 or 1: Has not or has been in the state since last reset

0

RO/LH/COR

6 Fault State Detected 0 or 1: Has not or has been in the state since last reset

0

RO/LH/COR

5 Ready State Detected 0 or 1: Has not or has been in the state since last reset

0

RO/LH/COR

4 TX-Turn-on State Detected 0 or 1: Has not or has been in the state since last reset

0

RO/LH/COR

3 TX-Off State Detected 0 or 1: Has not or has been in the state since last reset

0

RO/LH/COR

2 High-Power-on State Detected 0 or 1: Has not or has been in the state since last reset since last reset

0

RO/LH/COR

1 Low-Power State Detected 0 or 1: Has not or has been in the state 0

A016 1

RO/LH/COR

0 Initialize State Detected 0 or 1: Has not or has been in the state. All 9 bits above are latched and cleared upon read or reset.

0

Data_Ready and Alarm Summaries, not included in GLB_ALRMn A017 1 RO Data_Ready MDIO Port data ready code.

Confirmation code = 0x89AB 0000h

Global Alarm Summary 15 Reserved 0 14 TX Channel Alarm Summary Logical OR of all the bits in the TX Channel

Alarms Summary register 0

13 RX Channel Alarm Summary Logical OR of all the bits in the RX Channel Alarms Summary register

0

12 ModAlarms2Summary Logical OR of all the effective (enabled) bits of Module Alarms and Warnings 2 register

0

11 ModAlarms1Summary Logical OR of all the effective (enabled) bits of Module Alarms and Warnings 1 register

0

A018 1 RO

10 Mod Fatal Fault Summary Logical OR of all the effective (enabled) bits of Module Fatal Fault Status register

0




Size Access Type



9 Mod General Status Alarm Summary Logical OR of all the effective (enabled) bits of Module General Status register

0

8 Mod State Status Summary Logical OR of all the effective (enabled) bits of Module State Status register

0

7~0 Reserved 0 TX Channel Alarm Summary Each bit is the logical OR of all enabled

Latched Ch TX Alarm bits (A202, A302, etc)

15~12

Reserved 0000b

11 Ch 11 TX alarm summary Logical OR of all enabled bits in Latched Ch 11 TX Alarm register. 1=Fault asserted

0


0


0


0


0


0


0


0


0


0


0

A019 1 RO


0

RX Channel Alarm Summary Each bit is the logical OR of all enabled Latched Ch TX Alarm bits (A203, A303, etc)

0000h

15~12

Reserved 0000b

11 Ch 11 RX alarm summary Logical OR of all enabled bits in Latched Ch 11 RX Alarm register. 1=Fault asserted

0


0


0


0


0


0


0

A01A 1 RO


0




Size Access Type




0


0


0


0

A01B 2 RO Reserved CFP Alarm/Status Registers

Module General Status 0000h RO 15 MOD_LOPWR state Logical state of the MOD_LOPWR input

pin. 1 = asserted 0

RO 14 TX_DIS state Logical state of the TX_DIS input pin. 1 = asserted

0

RO 13 PRG_CNTL3 Control State Logical state of the PRG_CNTL3 input pin. 1 = asserted

0


0


0

RO 10 GLB_ALRMn state Logical state of the GLB_ALRMn output pin. 1 = asserted

0

RO 9 RX_LOS state Logical state of the RX_LOS output pin. 1 = asserted

0

RO 8 PRG_ALRM3 state Logical state of the PRG_ALRM3 output pin. 1 = asserted

0


0


0

RO 5 TX LOL Summary Logical OR of all Tx LOL signals from channel 0..n

0

RO 4 RX Sync Loss Summary

Logical OR of all Rx Sync Loss signals from channel 0..n

0

RO 3 Data_Ready Flag indicating the DDM data is available to host

0

RO 2 MOD_READY Flag dedicated for Startup. Bit is set when coming out of TX-Turn-on state. Cleared on read or reset.

0

RO 1 HIPWR_ON Flag dedicated for Startup. Bit is set when coming out of High-Power-up state. Cleared on read or reset.

0

A01D 1

RO/LH 0 Init_Complete Flag dedicated for Startup. Cleared upon reset. The module sets this bit to '1' when all MDIO registers (including A/D data) contain valid data and initialization is complete.

0

Module Fatal Fault Status Module Fatal Fault Status latched bit pattern. Only fatal faults that are potentially harmful to the module can trigger the bits here. All the bits are 0: Normal; 1: fault detected. When any bit in this register is a '1', The Module State register will also be set to the Fatal Fault State.

0000h A01E 1

RO/LH 15~11

Reserved for Future Fatal Fault Use 0




Size Access Type



RO/LH 10 Power class fault Module will be prevented from entering HighPower state because PowerClass (in NV Reg) is greater than allowed PowerClass value on the input pins (PRG_CNTL2,3).

0

RO/LH 9 APD Bias circuit fault APD Bias circuit fault detected RO/LH 8 TEC Fault TEC loop failed to close for more than

Specified TEC look time 0

RO/LH 7 Wavelength Control Fault aggregated over channels

Wavelength control circuit failure 0

RO/LH 6 0 RO/LH 5 TX FAULT Summed over channels Any channel's TX FAULT is set. 0 RO/LH 4 PLD or Flash Initialization Fault PLD, CPLD, or FPGA initialization fault 0 RO/LH 3 Power Supply fault Set if any power supply is out of range. 0 RO/LH 2 CFP NVR 2 Checksum Fault Set to 1 if CFP NVR 1 Checksum fails. 0 RO/LH 1 CFP NVR 1 Checksum Fault Set to 1 if CFP NVR 2 Checksum fails. 0 RO/LH 0 MOD_FAULT Summary Bit of all faults OR'ed in this

register. 0

Module Alarms and Warnings 1 0000h 15~1

2 Reserved 0

11 Mod Temp High Alarm Mod temp high Alarm; 0:Normal, 1:Alarm assert

0

10 Mod Temp High Warning Mod temp high Warning; 0:Normal, 1:Warning assert

0

9 Mod Temp Low Warning Mod temp low Warning; 0:Normal, 1:Alarm assert

0

8 Mod Temp Low Alarm Mod temp low Alarm; 0:Normal, 1:Warning assert

0

7 Mod Vcc High Alarm Input Vcc high Alarm; 0:Normal, 1:Alarm assert

0

6 Mod Vcc High Warning Input Vcc high Warning; 0:Normal, 1:Alarm assert

0

5 Mod Vcc Low Warning Input Vcc low Warning; 0:Normal, 1:Alarm assert

0

4 Mod Vcc Low Alarm Input Vcc low Alarm; 0:Normal, 1:Alarm assert

0

3 Mod SOA Bias High Alarm SOA bias current high alarm; 0:Normal, 1:Alarm assert

0

2 Mod SOA Bias High Warning SOA bias current high warning; 0:Normal, 1:Alarm assert

0

1 Mod SOA Bias Low Warning SOA bias current low warning; 0:Normal, 1:Alarm assert

0

A01F 1 RO

0 Mod SOA Bias Low Alarm SOA bias current low alarm; 0:Normal, 1:Alarm assert

0

Module Alarms and Warnings 2 0000h 15~8 Reserved 0

7 Mod Aux 1 High Alarm mod aux ch 1 high alarm; 0:Normal, 1:Alarm assert

0

6 Mod Aux 1 High Warning mod aux ch 1 high warning; 0:Normal, 1:Alarm assert

0

5 Mod Aux 1 Low Warning mod aux ch 1 low warning; 0:Normal, 1:Alarm assert

0

4 Mod Aux 1 Low Alarm mod aux ch 1 low alarm; 0:Normal, 1:Alarm assert

0

A020 1 RO

3 Mod Aux 2 High Alarm mod aux ch 2 high alarm; 0:Normal, 1:Alarm assert

0




Size Access Type



2 Mod Aux 2 High Warning mod aux ch 2 high warning; 0:Normal, 1:Alarm assert

0

1 Mod Aux 2 Low Warning mod aux ch 2 low warning; 0:Normal, 1:Alarm assert

0

0 Mod Aux 2 Low Alarm mod aux ch 2 low alarm; 0:Normal, 1:Alarm assert

0

A021 2 RO Reserved 0 Bit Latched Registers

Module General Status Latch 0000h RO/LH/C

OR 15 MOD_LOPWR state Latched logical state of the MOD_LOPWR

input pin. 1 = asserted 0

RO/LH/COR

14 TX_DIS state Latched logical state of the TX_DIS input pin. 1 = asserted

0

RO/LH/COR

13 PRG_CNTL3 Control State Latched logical state of the PRG_CNTL3 input pin. 1 = asserted

0

RO/LH/COR


0

RO/LH/COR


0

RO/LH/COR

10 GLB_ALRMn state Latched logical state of the GLB_ALRMn output pin. 1 = asserted

0

RO/LH/COR

9 RX_LOS state Latched logical state of the RX_LOS output pin. 1 = asserted

0

RO/LH/COR

8 PRG_ALRM3 state Latched logical state of the PRG_ALRM3 output pin. 1 = asserted

0

RO/LH/COR


0

RO/LH/COR


0

RO/LH/COR

5 TX LOL Summary Change Set to 1 on any change (0->1 or 1->0) of Tx LOL Summary. Cleared to 0 on read, independent of the unlatched signal status.

0

RO/LH/COR

4 Latched RX Sync Loss Summary Change

Set to 1 on any change (0->1 or 1->0) of Rx Sync Loss Summary. Cleared to 0 on read, independent of the (unlatched) Rx Sync Loss signal status.

0

RO/LH/COR

3 Data_Ready Flag indicating the AD data is available to host

0

RO/LH/COR

2 MOD_READY Flag dedicated for Startup. 1 = the module is in the Ready State.

0

RO/LH/COR

1 HIPWR_ON Flag dedicated for Startup. 1 = the module is fully powered up (high power).

0

A023 1

RO/LH/COR

0 Init_Complete Flag dedicated for Startup. Cleared upon reset. The module sets this bit to '1' when all MDIO registers (including A/D data) contain valid data and initialization is complete.

0

Module Fatal Fault Latch Module Fault Status latched bit pattern. 0000h RO/LH/C

OR 15~1

1 Reserved for Future Fatal Fault Use 0

RO/LH/COR

10 Latched Power class fault Module will be prevented from entering High-Power state because Power Class (in NV Reg) is greater than allowed Power Class value on the input pins (PRG_CNTL1,2).

0

A024 1

RO/LH/COR

9 Latched APD Bias circuit fault APD Bias circuit fault detected 0




Size Access Type



RO/LH/COR

8 Latched TEC Fault TEC loop failed to close for more than specified TEC look time

0

RO/LH/COR

7 Latched Wavelength Control Fault aggregated over channels

Wavelength control circuit failure 0

RO/LH/COR

6 Reserved 0

RO/LH/COR

5 Latched TX FAULT aggregated over channels

Any channel's TX FAULT is set. 0

RO/LH/COR

4 Latched PLD or Flash Initialization Fault

PLD, CPLD, or FPGA initialization fault 0

RO/LH/COR

3 Latched Power Supply fault Set if any power supply is out of range. 0

RO/LH/COR

2 Latched CFP NVR 2 Checksum Fault Set to 1 if CFP NVR 1 Checksum fails. 0

RO/LH/COR

1 Latched CFP NVR 1 Checksum Fault Set to 1 if CFP NVR 2 Checksum fails. 0

RO/LH/COR

0 Latched MOD_FAULT Summary Bit of all faults OR'ed in this register.

0

Module Alarms and Warnings 1 Latch

0000h

RO 15~12

Reserved 0

RO/LH/COR

11 Latched Mod Temp High Alarm Mod temp high Alarm; 0:Normal, 1:Alarm assert

0

RO/LH/COR

10 Latched Mod Temp High Warning Mod temp high Warning; 0:Normal, 1:Warning assert

0

RO/LH/COR

9 Latched Mod Temp Low Warning Mod temp low Warning; 0:Normal, 1:Alarm assert

0

RO/LH/COR

8 Latched Mod Temp Low Alarm Mod temp low Alarm; 0:Normal, 1:Warning assert

0

RO/LH/COR

7 Latched Mod Vcc High Alarm Input Vcc high alarm; 0:Normal, 1:Alarm assert

0

RO/LH/COR

6 Latched Mod Vcc High Warning Input Vcc high warning; 0:Normal, 1:Alarm assert

0

RO/LH/COR

5 Latched Mod Vcc Low Warning Input Vcc low warning; 0:Normal, 1:Alarm assert

0

RO/LH/COR

4 Latched Mod Vcc Low Alarm Input Vcc low alarm; 0:Normal, 1:Alarm assert

0

RO/LH/COR

3 Latched Mod SOA Bias High Alarm SOA bias current high alarm; 0:Normal, 1:Alarm assert

0

RO/LH/COR

2 Latched Mod SOA Bias High Warning

SOA bias current high warning; 0:Normal, 1:Alarm assert

0

RO/LH/COR

1 Latched Mod SOA Bias Low Warning SOA bias current low warning; 0:Normal, 1:Alarm assert

0

A025 1

RO/LH/COR

0 Latched Mod SOA Bias Low Alarm SOA bias current low alarm; 0:Normal, 1:Alarm assert

0

Module Alarms and Warnings 2 Latch

0

RO 15~8 Reserved 0 RO/LH/C

OR 7 Latched Mod Aux 1 High Alarm mod aux ch 1 high alarm; 0:Normal,

1:Alarm assert 0

RO/LH/COR

6 Latched Mod Aux 1 High Warning mod aux ch 1 high warning; 0:Normal, 1:Alarm assert

0

A026 1

RO/LH/COR

5 Latched Mod Aux 1 Low Warning mod aux ch 1 low warning; 0:Normal, 1:Alarm assert

0




Size Access Type



RO/LH/COR

4 Latched Mod Aux 1 Low Alarm mod aux ch 1 low alarm; 0:Normal, 1:Alarm assert

0

RO/LH/COR

3 Latched Mod Aux 2 High Alarm mod aux ch 2 high alarm; 0:Normal, 1:Alarm assert

0

RO/LH/COR

2 Latched Mod Aux 2 High Warning mod aux ch 2 high warning; 0:Normal, 1:Alarm assert

0

RO/LH/COR

1 Latched Mod Aux 2 Low Warning mod aux ch 2 low warning; 0:Normal, 1:Alarm assert

0

RO/LH/COR

0 Latched Mod Aux 2 Low Alarm mod aux ch 2 low alarm; 0:Normal, 1:Alarm assert

0

A027 2 Reserved 0 Bit Enable Registers

Module General Status Alarm Enable

1 = enable signal to assert GLB_ARLMn. Bits 10~0 are AND'ed with corresponding bits in the Module General Status Latch register; the result is used to assert GLB_ALRMn.

87FFh

RW 15 Reserved 0: Disable, 1: Enable GLB_ALRMn output pin

1

RW 14 Reserved 0 RW 13 Reserved 0 RW 12 Reserved 0 RW 11 Reserved 0 RW 10 Reserved 1 RW 9 Enable RX_LOS state 0: Disable, 1: Enable 1 RW 8 Enable PRG_ALRM3 state 0: Disable, 1: Enable 1 RW 7 Enable PRG_ALRM2 state 0: Disable, 1: Enable 1 RW 6 Enable PRG_ALRM1 state 0: Disable, 1: Enable 1 RW 5 Enable TX LOL Summary 0: Disable, 1: Enable 1 RW 4 Enable RX Sync Loss Summary 0: Disable, 1: Enable 1 RW 3 Enable Data_Ready 0: Disable, 1: Enable 1 RW 2 Enable MOD_READY 0: Disable, 1: Enable 1 RW 1 Enable HIPWR_ON 0: Disable, 1: Enable 1

A029 1

RW 0 Enable Init_Complete 0: Disable, 1: Enable 1 Module Fatal Fault Alarm Enable These bits are AND'ed with

corresponding bits in the Module Fatal Fault Latch register; the result is used to assert GLB_ALRMn. Optional features that are not implemented shall have their Enable bit forced to '0'.

03FFh

RO 15~10

Reserved for Future Fatal Fault Use 0

RW 9 Enable APD Bias circuit fault 0: Disable, 1: Enable 1 RW 8 Enable TEC Fault 0: Disable, 1: Enable 1 RW 7 Enable Wavelength Control Fault

Summary 0: Disable, 1: Enable 1

RW 6 Reserved 0: Disable, 1: Enable 1 RW 5 Enable TX FAULT aggregated over

channels 0: Disable, 1: Enable 1

RW 4 Enable PLD or Flash Initialization Fault

0: Disable, 1: Enable 1

RW 3 Enable Power Supply fault 0: Disable, 1: Enable 1 RW 2 Enable CFP NVR 2 Checksum Fault 0: Disable, 1: Enable 1 RW 1 Enable CFP NVR 1 Checksum Fault 0: Disable, 1: Enable 1

A02A 1

RW 0 Enable MOD_FAULT 0: Disable, 1: Enable 1




Size Access Type



Module Alarm and Warnings 1 Enable

These bits are AND'ed with corresponding bits in the Module Alarm and Warnings 1 Latch register; the result is used to assert GLB_ALRMn. Optional features that are not implemented shall have their Enable bit forced to '0'.

0FFFh

15~12

Reserved 0

11 Enable Mod Temp Hi Alarm 0: Disable, 1: Enable 1 10 Enable Mod Temp Hi Warn 0: Disable, 1: Enable 1 9 Enable Mod Temp Low Warning 0: Disable, 1: Enable 1 8 Enable Mod Temp Low Alarm 0: Disable, 1: Enable 1 7 Enable Mod Vcc High Alarm 0: Disable, 1: Enable 1 6 Enable Mod Vcc High Warning 0: Disable, 1: Enable 1 5 Enable Mod Vcc Low Warning 0: Disable, 1: Enable 1 4 Enable Mod Vcc Low Alarm 0: Disable, 1: Enable 1 3 Enable Mod SOA Bias High Alarm 0: Disable, 1: Enable 1 2 Enable Mod SOA Bias High Warning 0: Disable, 1: Enable 1 1 Enable Mod SOA Bias Low Warning 0: Disable, 1: Enable 1

A02B 1 RW

0 Enable Mod SOA Bias Low Alarm 1 Module Alarms and Warnings 2

Enable These bits are ANDed with corresponding bits in the Module Alarm and Warnings 2 Latch register; the result is used to assert GLB_ALRMn. Optional features that are not implemented shall have their Enable bit forced to '0'.

00FFh

RO 15~8 Reserved 00h RW 7 Enable Mod Aux 1 High Alarm 0: Disable, 1: Enable 1 RW 6 Enable Mod Aux 1 High Warning 0: Disable, 1: Enable 1 RW 5 Enable Mod Aux 1 Low Warning 0: Disable, 1: Enable 1 RW 4 Enable Mod Aux 1 Low Alarm 0: Disable, 1: Enable 1 RW 3 Enable Mod Aux 2 High Alarm 0: Disable, 1: Enable 1 RW 2 Enable Mod Aux 2 High Warning 0: Disable, 1: Enable 1 RW 1 Enable Mod Aux 2 Low Warning 0: Disable, 1: Enable 1

A02C 1

RW 0 Enable Mod Aux 2 Low Alarm 0: Disable, 1: Enable 1 A02D 2 RO Reserved 1

Analog A2D Values A02F 1 15~0 Module Temp Monitor 1 A/D Value Internally measured temperature in

degrees Celsius, a 16-bit signed integer with LSB = 1/256 of a degree Celsius, representing a total range from -128 to + 127 255/256 degC. MSA valid range is between –40 and +125C. Accuracy shall be better than +/- 3 degC over the whole temperature range.

0000h

A030 1 RO 15~0 Module Power supply 3.3 V Monitor A/D Value

Internally measured transceiver supply voltage, a 16-bit unsigned integer with LSB = 0.1 mV, yielding a total measurement range of 0 to 6.5535 Volts. Accuracy shall be better than +/-3% of the nominal value over specified operating temperature and voltage range.

0000h




Size Access Type



A031 1 RO 15~0 SOA Bias Current A/D Value Measured SOA bias current in uA, a 16-bit unsigned integer with LSB = 2 uA, representing a total range of from 0 to 131.072 mA. Accuracy shall be better than +/-10% of the nominal value over specified temperature and voltage.

0000h

A032 1 RO 15~0 Module Auxiliary 1 Monitor A/D Value

Definition depending upon the designated use.

0000h

A033 1 RO 15~0 Module Auxiliary 2 Monitor A/D Value

Definition depending upon the designated use.

0000h

5.4 Channel Specific DDM/BOL Data/Control Register Table This table contains channel specific DDM Registers listed in Table 10: Channel Specific DDM Register Details. The address associated with each register is only valid for Channel 0 table. For each network (optical) channel one table shall be provided. The corresponding address for any channel n shall be calculated as follows. Address_in_Channel_n = Address_in_Channel_0 + n x 80h, Where, 80h = 128 is the table size and n = 0, 1, …, N-1. N is the total number of channel a specific module supports. Depending upon application and vendor implementation, a maximal number of 12 network channel DDM channels are specified.

5.4.1 Channel Specific Alarm Registers (A200h, A201h) Descriptions are provided in the “Description” column at Registers A200h, A201h in Table 10: Channel Specific DDM Register Details.

5.4.2 Channel Specific Alarm Latch Registers (A202h, A203h) Descriptions are provided in the “Description” column at Registers A202h, A203h in Table 10: Channel Specific DDM Register Details.

5.4.3 Channel Specific Alarm Enable Registers (A204h, A205h) Descriptions are provided in the “Description” column at Registers A204h, A205h in Table 10: Channel Specific DDM Register Details.

5.4.4 Channel Specific Analog A/D Value Registers (A206h, A207h, A208h, A209h, A20Ah)

Descriptions are provided in the “Description” column at Registers A204h, A205h in Table 10: Channel Specific DDM Register Details.



Register A20Ah is the Ch 0 PRBS Error Count. Instead of containing A/D value, this register contains the PRBS test error counts used during system test.

5.4.5 Channel Specific BOL Measurement Registers (A20Bh, A20Ch, A20Dh, A20Eh)

This group of registers contains the beginning of life measurement results by vendor for user’s reference. The detailed description can be found in Table 10: Channel Specific DDM Register Details, associated with each corresponding register.

5.4.6 Channel Specific FEC Control Registers (A20Fh) In some forward error correction schemes, the host system may optimize the sensitivity of an optical link or minimize the error rate by adjusting the phase and amplitude threshold for data quantization in the limiting amplifier section of the module receive path. Implementation of FEC control functions is indicated in CFP NVR 2 Table Register 8083h, bit 3~ 1. The LSB (Bits 7~0) of register A20Fh is used to set the amplitude threshold of receive path quantization. It is a 2’s complement 7 bit value (-128 ~ +127), where the threshold is given by: Amplitude Threshold = 50% + (LSB of A20Fh)/256] * 100%. Similarly, the MSB of register A20Fh (bits 15~8) is used to set the phase point in the eye diagram for quantization, and is set in terms of unit interval relative to the eye center: Phase set-point = 0.5UI + [(MSB of A20Fh)/256] UI.



Table 10: Channel Specific DDM Register Details

Channel Specific (Channel 0) DDM, BOL Measurement, and Control Register Detail Hex Add

Size Access Type


Description Unit

Channel Specific Alarms Ch 0 TX Alarm 0000h

15~13 Reserved 0 12 Laser EOL Alarm 0:normal, 1:End of Life 0 11 Laser Bias Alarm 0:normal, 1:Alarm assert 0 10 Laser Bias Warning 0:normal, 1:Warning assert 0 9 Laser Temperature Alarm 0:normal, 1:Alarm assert 0 8 Laser Temperature Warning 0:normal, 1:Warning assert 0 7 Laser Wavelength Alarm 0:normal, 1:Alarm assert 0 6 Laser Wavelength Warning 0:normal, 1:Warning assert 0 5 TEC control fault 0:normal, 1:Fault assert 0 4 Wavelength control fault 0:normal, 1:Fault assert 0 3 Reserved 0 2 TX LOL 0:normal, 1:Fault assert 0 1 TX Fault 0:normal, 1:Alarm assert 0

A200 1 RO

0 Reserved 0 Ch 0 RX Alarm 0000h

15~5 Reserved 0 4 SOA Bias Current contorl

fault 0:normal, 1:Fault assert 0

3 RX LOS Alarm 0:normal, 1: Loss of Signal Alarm assert 0 2 RX LOS Warning 0:normal, 1: Loss of Signal Warning assert 0 1 RX Sync Loss 0:normal, 1:Alarm assert 0

A201 1 RO

0 Reserved 0 Channel Specific Alarm Latches

Ch 0 TX Alarm Latch 0000h 15~13 Reserved 0

12 Latched Laser EOL Alarm 0:normal, 1:End of Life 0 11 Latched Laser Bias Alarm 0:normal, 1:Alarm assert 0 10 Latched Laser Bias Warning 0:normal, 1:Warning assert 0 9 Latched Laser Temperature

Alarm 0:normal, 1:Alarm assert 0

8 Latched Laser Temperature Warning

0:normal, 1:Warning assert 0

7 Latched Laser Wavelength Alarm

0:normal, 1:Alarm assert 0

6 Latched Laser Wavelength Warning

0:normal, 1:Warning assert 0

5 Latched TEC control fault 0:normal, 1:Fault assert 0 4 Latched Wavelength control

fault 0:normal, 1:Fault assert 0

3 Reserved 2 Latched TX LOL 0:normal, 1:Loss of Lock Fault assert 0 1 Latched TX Fault 0:normal, 1:Loss of Lock Alarm assert 0

A202 1 RO/LH/COR

0 Reserved 0 Ch 0 RX Alarm Latch 0000h

15~5 Reserved 0 4 Latched SOA Bias Current

contorl fault 0:normal, 1:Fault assert 0

3 Latched RX LOS Alarm 0:normal, 1:Loss of Signal Alarm assert 0 2 Latched RX LOS Warning 0:normal, 1:Loss of Signal Warning assert 0 1 RX Sync Loss 0:normal, 1:Warning assert 0

A203 1 RO/LH/COR

0 Reserved 0




Size Access Type


Description Unit

Channel Specific Enables Ch 0 TX Alarm Enable Optional features that are not implemented

shall have their Enable bit forced to '0'.

RO 15~13 Reserved 0 RW 12 Enable bit of Laser EOL

Alarm 0: Disabled, 1: Enabled 0

RW 11 Enable bit of Laser Bias Alarm

0: Disabled, 1: Enabled 0

RW 10 Enable bit of Laser Bias Warning


RW 9 Enable bit of Laser Temperature Alarm


RW 8 Enable bit of Laser Temperature Warning


RW 7 Enable bit of Laser Wavelength Alarm


RW 6 Enable bit of Laser Wavelength Warning


RW 5 Enable bit of TEC control fault


RW 4 Enable bit of Wavelength control fault


RW 3 Reserved RW 2 Enable bit of TX LOL 0: Disabled, 1: Enabled 0 RW 1 Enable bit of TX Fault 0: Disabled, 1: Enabled 0

A204 1

RW 0 Reserved 0 Ch 0 RX Alarm Enable Optional features that are not implemented

shall have their Enable bit forced to '0'. 0000h

RO 15~5 Reserved 0 4 Enable bit of SOA Bias

Current contorl fault 0: Disabled, 1: Enabled 0

RW 3 Enable bit of RX LOS Alarm 0: Disabled, 1: Enabled 0 RW 2 Enable bit of RX LOS

Warning 0: Disabled, 1: Enabled 0

RW 1 Enable bit of RX Sync Loss 0: Disabled, 1: Enabled 0

A205 1

RW 0 Reserved 0 Channel Specific Analog A/D Values

A206 1 RO 15~0 Ch 0 Laser Bias Current monitor A/D value

Measured laser bias current in uA, a 16-bit unsigned integer with LSB = 2 uA, representing a total measurement range of 0 to 131.072 mA. Minimum accuracy is +/- 10% of the nominal value over temperature and voltage.

0000h

A207 1 RO 15~0 Ch 0 Laser Output Power monitor A/D value

Measured TX output power in uW, a 16-bit unsigned integer with LSB = 0.1 uW, representing a range of laser output power from 0 to 6.5535 mW (-40 to +8.2 dBm). Accuracy must be better than +/- 2 dB over temperature and voltage range. Relative accuracy must be better than 1 dB.

0000h




Size Access Type


Description Unit

A208 1 RO 15~0 Ch 0 Receiver Input Power monitor A/D value

Measured received input power in uW, a 16-bit unsigned integer with LSB = 0.1 uW, representing a power range from 0 to 6.5535 mW (-40 to +8.2 dBm). Value can represent either average received power or OMA depending upon how bit 3 of Register 8080h is set. Accuracy must be better than +/- 2dB over temperature and voltage. This accuracy shall be maintained for input power levels up to the lesser of maximum transmitted or maximum received optical power per the appropriate standard. It shall be maintained down to the minimum transmitted power minus cable plant loss per the appropriate standard. Relative accuracy shall be better than 1 dB over the received power range, temperature range, voltage range, and the life of the product.

0000h

A209 1 RO 15~0 Ch 0 Laser Temp Monitor A/D value

Internally measured temperature in degrees Celsius, a 16-bit signed integer with LSB = 1/256 of a degree Celsius, representing a total range from -128 to + 127 255/256 degC. MSA valid range is between –40 and +125C. Accuracy shall be better than +/- 3 degC over the whole temperature range.

0000h

A20A 1 RO/COR

15~0 Ch 0 PRBS Rx Error Count This 16-bit counter increments upon detection of each PRBS Rx error when PRBS Rx is enabled. Upon reaching terminal count (0xFFFF) the counter does not roll over. The counter is cleared only when read by the host.

0000h

Channel Specific BOL Measurements A20B 1 RO 15~0 Ch 0 RX Sensitivity Spec RX Sensitivity measured in dBm @ BER=1e-12

at Typical condition. The value is a signed 16-bit integer with LSB = 0.01dBm.

0000h

A20C 1 RO 15~0 Ch 0 TX Power Spec TX Power measured in dBm at typical condition. The value is a signed 16-bit integer with LSB = 0.01dBm.

0000h

A20D 1 RO 15~0 Ch 0 Measured ER Measured Extinction ratio at Typical condition in dB. The value is an unsigned 16-bit integer with LSB = 0.01dB.

0000h

A20E 1 RO 15~0 Ch 0 Path Penalty Path penalty @worst CD at Typical condition. The value is an unsigned 16-bit integer with LSB = 0.01dB.

0000h

Channel Specific Controls A20F 1 RO FEC Controls 0000h

15~8 Phase Adjustment Phase of receive quantization relative to 0.5 UI. 00h 7~0 Amplitude Adjustment Relative amplitude of receive quantization

threshold 00h

END OF DOCUMENT

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