CEG3420 Computer Design Lecture 4 MIPS Instruction Set
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Transcript of CEG3420 Computer Design Lecture 4 MIPS Instruction Set
11998 Morgan Kaufmann Publishers and UCB
CEG3420 Computer Design Lecture 4
MIPS Instruction Set
Philip Leong
21998 Morgan Kaufmann Publishers and UCB
Instructions:
• Language of the Machine• More primitive than higher level languages
e.g., no sophisticated control flow• Very restrictive
e.g., MIPS Arithmetic Instructions
• We’ll be working with the MIPS instruction set architecture– similar to other architectures developed since the 1980's– used by NEC, Nintendo, Silicon Graphics, Sony
Design goals: maximize performance and minimize cost, reduce design time
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MIPS arithmetic
• All instructions have 3 operands• Operand order is fixed (destination first)
Example:
C code: A = B + C
MIPS code: add $s0, $s1, $s2
(associated with variables by compiler)
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MIPS arithmetic
• Design Principle: simplicity favors regularity. Why?• Of course this complicates some things...
C code: A = B + C + D;E = F - A;
MIPS code: add $t0, $s1, $s2add $s0, $t0, $s3sub $s4, $s5, $s0
• Operands must be registers, only 32 registers provided• Design Principle: smaller is faster. Why?
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Registers vs. Memory
Processor I/O
Control
Datapath
Memory
Input
Output
• Arithmetic instructions operands must be registers, — only 32 registers provided
• Compiler associates variables with registers• What about programs with lots of variables
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Memory Organization
• Viewed as a large, single-dimension array, with an address.• A memory address is an index into the array• "Byte addressing" means that the index points to a byte of memory.
0123456...
8 bits of data
8 bits of data
8 bits of data
8 bits of data
8 bits of data
8 bits of data
8 bits of data
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Memory Organization
• Bytes are nice, but most data items use larger "words"• For MIPS, a word is 32 bits or 4 bytes.
• 232 bytes with byte addresses from 0 to 232-1• 230 words with byte addresses 0, 4, 8, ... 232-4• Words are aligned
i.e., what are the least 2 significant bits of a word address?
048
12...
32 bits of data
32 bits of data
32 bits of data
32 bits of data
Registers hold 32 bits of data
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Instructions
• Load and store instructions• Example:
C code: A[8] = h + A[8];
MIPS code: lw $t0, 32($s3)add $t0, $s2, $t0sw $t0, 32($s3)
• Store word has destination last• Remember arithmetic operands are registers, not memory!
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Our First Example
• Can we figure out the code?
swap(int v[], int k);{ int temp;
temp = v[k]v[k] = v[k+1];v[k+1] = temp;
} swap:muli $2, $5, 4add $2, $4, $2lw $15, 0($2)lw $16, 4($2)sw $16, 0($2)sw $15, 4($2)jr $31
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So far we’ve learned:
• MIPS— loading words but addressing bytes— arithmetic on registers only
• Instruction Meaning
add $s1, $s2, $s3 $s1 = $s2 + $s3sub $s1, $s2, $s3 $s1 = $s2 – $s3lw $s1, 100($s2) $s1 = Memory[$s2+100] sw $s1, 100($s2) Memory[$s2+100] = $s1
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• Instructions, like registers and words of data, are also 32 bits long– Example: add $t0, $s1, $s2– registers have numbers, $t0=9, $s1=17, $s2=18
• Instruction Format:
000000 10001 10010 01000 00000 100000
op rs rt rd shamt funct
• Can you guess what the field names stand for?
Machine Language
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• Consider the load-word and store-word instructions,– What would the regularity principle have us do?– New principle: Good design demands a compromise
• Introduce a new type of instruction format– I-type for data transfer instructions– other format was R-type for register
• Example: lw $t0, 32($s2)
35 18 9 32
op rs rt 16 bit number
• Where's the compromise?
Machine Language
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• Instructions are bits• Programs are stored in memory
— to be read or written just like data
• Fetch & Execute Cycle– Instructions are fetched and put into a special register– Bits in the register "control" the subsequent actions– Fetch the “next” instruction and continue
Processor Memory
memory for data, programs, compilers, editors, etc.
Stored Program Concept
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• Decision making instructions– alter the control flow,– i.e., change the "next" instruction to be executed
• MIPS conditional branch instructions:
bne $t0, $t1, Label beq $t0, $t1, Label
• Example: if (i==j) h = i + j;
bne $s0, $s1, Labeladd $s3, $s0, $s1Label: ....
Control
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• MIPS unconditional branch instructions:j label
• Example:
if (i!=j) beq $s4, $s5, Lab1 h=i+j; add $s3, $s4, $s5else j Lab2 h=i-j; Lab1: sub $s3, $s4, $s5
Lab2: ...
• Can you build a simple for loop?
Control
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So far:
• Instruction Meaning
add $s1,$s2,$s3 $s1 = $s2 + $s3sub $s1,$s2,$s3 $s1 = $s2 – $s3lw $s1,100($s2) $s1 = Memory[$s2+100] sw $s1,100($s2) Memory[$s2+100] = $s1bne $s4,$s5,L Next instr. is at Label if $s4 ° $s5beq $s4,$s5,L Next instr. is at Label if $s4 = $s5j Label Next instr. is at Label
• Formats:
op rs rt rd shamt funct op rs rt 16 bit address
op 26 bit address
R
I
J
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• We have: beq, bne, what about Branch-if-less-than?• New instruction:
if $s1 < $s2 then $t0 = 1
slt $t0, $s1, $s2 else $t0 = 0
• Can use this instruction to build "blt $s1, $s2, Label" — can now build general control structures
• Note that the assembler needs a register to do this,— there are policy of use conventions for registers
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Control Flow
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Policy of Use Conventions
Name Register number Usage$zero 0 the constant value 0$v0-$v1 2-3 values for results and expression evaluation$a0-$a3 4-7 arguments$t0-$t7 8-15 temporaries$s0-$s7 16-23 saved$t8-$t9 24-25 more temporaries$gp 28 global pointer$sp 29 stack pointer$fp 30 frame pointer$ra 31 return address
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• Small constants are used quite frequently (50% of operands) e.g., A = A + 5;B = B + 1;C = C - 18;
• Solutions? Why not?– put 'typical constants' in memory and load them. – create hard-wired registers (like $zero) for constants like one.
• MIPS Instructions:
addi $29, $29, 4slti $8, $18, 10andi $29, $29, 6ori $29, $29, 4
• How do we make this work?
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Constants
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• We'd like to be able to load a 32 bit constant into a register• Must use two instructions, new "load upper immediate" instruction
lui $t0, 1010101010101010
• Then must get the lower order bits right, i.e.,
ori $t0, $t0, 1010101010101010
1010101010101010 0000000000000000
0000000000000000 1010101010101010
1010101010101010 1010101010101010
ori
1010101010101010 0000000000000000
filled with zeros
How about larger constants?
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• Assembly provides convenient symbolic representation– much easier than writing down numbers– e.g., destination first
• Machine language is the underlying reality– e.g., destination is no longer first
• Assembly can provide 'pseudoinstructions'– e.g., “move $t0, $t1” exists only in Assembly – would be implemented using “add $t0,$t1,$zero”
• When considering performance you should count real instructions
Assembly Language vs. Machine Language
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• simple instructions all 32 bits wide• very structured, no unnecessary baggage• only three instruction formats
• rely on compiler to achieve performance— what are the compiler's goals?
• help compiler where we can
op rs rt rd shamt funct op rs rt 16 bit address
op 26 bit address
R
I
J
Overview of MIPS
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• Instructions:bne $t4,$t5,Label Next instruction is at Label if $t4 ° $t5beq $t4,$t5,Label Next instruction is at Label if $t4 = $t5j Label Next instruction is at Label
• Formats:
• Addresses are not 32 bits — How do we handle this with load and store instructions?
op rs rt 16 bit address
op 26 bit addressI
J
Addresses in Branches and Jumps
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• Instructions:bne $t4,$t5,Label Next instruction is at Label if $t4°$t5beq $t4,$t5,Label Next instruction is at Label if $t4=$t5
• Formats:
• Could specify a register (like lw and sw) and add it to address– use Instruction Address Register (PC = program counter)– most branches are local (principle of locality)
• Jump instructions just use high order bits of PC – address boundaries of 256 MB
op rs rt 16 bit addressI
Addresses in Branches
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MIPS arithmetic instructionsInstruction Example Meaning Commentsadd add $1,$2,$3 $1 = $2 + $3 3 operands; exception possiblesubtract sub $1,$2,$3 $1 = $2 – $3 3 operands; exception possibleadd immediate addi $1,$2,100 $1 = $2 + 100 + constant; exception possibleadd unsigned addu $1,$2,$3 $1 = $2 + $3 3 operands; no exceptionssubtract unsigned subu $1,$2,$3 $1 = $2 – $3 3 operands; no exceptionsadd imm. unsign. addiu $1,$2,100 $1 = $2 + 100 + constant; no exceptionsmultiply mult $2,$3 Hi, Lo = $2 x $3 64-bit signed productmultiply unsigned multu$2,$3 Hi, Lo = $2 x $3 64-bit unsigned productdivide div $2,$3 Lo = $2 ÷ $3, Lo = quotient, Hi = remainder
Hi = $2 mod $3 divide unsigned divu $2,$3 Lo = $2 ÷ $3, Unsigned quotient & remainder
Hi = $2 mod $3Move from Hi mfhi $1 $1 = Hi Used to get copy of HiMove from Lo mflo $1 $1 = Lo Used to get copy of Lo
Which add for address arithmetic? Which add for integers?
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MIPS logical instructions
Instruction Example Meaning Commentand and $1,$2,$3 $1 = $2 & $3 3 reg. operands; Logical ANDor or $1,$2,$3 $1 = $2 | $3 3 reg. operands; Logical ORxor xor $1,$2,$3 $1 = $2 $3 3 reg. operands; Logical XORnor nor $1,$2,$3 $1 = ~($2 |$3) 3 reg. operands; Logical NORand immediate andi $1,$2,10 $1 = $2 & 10 Logical AND reg, constantor immediate ori $1,$2,10 $1 = $2 | 10 Logical OR reg, constantxor immediate xori $1, $2,10 $1 = ~$2 &~10 Logical XOR reg, constantshift left logical sll $1,$2,10 $1 = $2 << 10 Shift left by constantshift right logical srl $1,$2,10 $1 = $2 >> 10 Shift right by constantshift right arithm. sra $1,$2,10 $1 = $2 >> 10 Shift right (sign extend) shift left logical sllv $1,$2,$3 $1 = $2 << $3 Shift left by variableshift right logical srlv $1,$2, $3 $1 = $2 >> $3 Shift right by variableshift right arithm. srav $1,$2, $3 $1 = $2 >> $3 Shift right arith. by variable
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MIPS data transfer instructionsInstruction CommentSW 500(R4), R3 Store wordSH 502(R2), R3 Store halfSB 41(R3), R2 Store byte
LW R1, 30(R2) Load wordLH R1, 40(R3) Load halfwordLHU R1, 40(R3) Load halfword unsignedLB R1, 40(R3) Load byteLBU R1, 40(R3) Load byte unsigned
LUI R1, 40 Load Upper Immediate (16 bits shifted left by 16)
Why need LUI?
0000 … 0000
LUI R5
R5
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MIPS Compare and Branch (Fixup)
• Compare and Branch– BEQ rs, rt, offset if R[rs] == R[rt] then PC-relative
branch– BNE rs, rt, offset <>
• Compare to zero and Branch– BLEZ rs, offset if R[rs] <= 0 then PC-relative branch
– BGTZ rs, offset >– BLT <– BGEZ >=– BLTZAL rs, offset if R[rs] < 0 then branch and link (into
R 31)– BGEZAL >=
• Remaining set of compare and branch take two instructions• Almost all comparisons are against zero
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MIPS jump, branch, compare instructionsInstruction Example Meaningbranch on equal beq $1,$2,100 if ($1 == $2) go to PC+4+100
Equal test; PC relative branchbranch on not eq. bne $1,$2,100 if ($1!= $2) go to PC+4+100
Not equal test; PC relative set on less than slt $1,$2,$3 if ($2 < $3) $1=1; else $1=0 Compare less than; 2’s comp. set less than imm. slti $1,$2,100 if ($2 < 100) $1=1; else $1=0 Compare < constant; 2’s comp.set less than uns. sltu $1,$2,$3 if ($2 < $3) $1=1; else $1=0 Compare less than; natural
numbersset l. t. imm. uns. sltiu $1,$2,100 if ($2 < 100) $1=1; else $1=0 Compare < constant; natural
numbersjump j 10000 go to 10000
Jump to target addressjump register jr $31 go to $31
For switch, procedure returnjump and link jal 10000 $31 = PC + 4; go to 10000
For procedure call
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Signed vs. Unsigned Comparison
R1= 0…00 0000 0000 0000 0001R2= 0…00 0000 0000 0000 0010R3= 1…11 1111 1111 1111 1111• After executing these instructions:
slt r4,r2,r1 ; if (r2 < r1) r4=1; else r4=0slt r5,r3,r1 ; if (r3 < r1) r5=1; else r5=0sltu r6,r2,r1 ; if (r2 < r1) r6=1; else r6=0sltu r7,r3,r1 ; if (r3 < r1) r7=1; else r7=0
• What are values of registers r4 - r7? Why?r4 = ; r5 = ; r6 = ; r7 = ;
two
two
two
Value?2’s comp Unsigned?
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Calls: Why Are Stacks So Great?Stacking of Subroutine Calls & Returns and Environments:
A: CALL B
CALL C
C: RET
RET
B:
A
A B
A B C
A B
A
Some machines provide a memory stack as part of the architecture (e.g., VAX)
Sometimes stacks are implemented via software convention (e.g., MIPS)
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Memory StacksUseful for stacked environments/subroutine call & return even if operand stack not part of architecture
Stacks that Grow Up vs. Stacks that Grow Down:
abc
0 Little
inf. Big 0 Little
inf. Big
MemoryAddresses
SP
NextEmpty?
LastFull?
How is empty stack represented?
Little --> Big/Last Full
POP: Read from Mem(SP) Decrement SP
PUSH: Increment SP Write to Mem(SP)
growsup
growsdown
Little --> Big/Next Empty
POP: Decrement SP Read from Mem(SP)
PUSH: Write to Mem(SP) Increment SP
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Call-Return Linkage: Stack Frames
FP
ARGS
Callee SaveRegisters
Local Variables
SP
Reference args andlocal variables atfixed (positive) offsetfrom FP
Grows and shrinks duringexpression evaluation
(old FP, RA)
• Many variations on stacks possible (up/down, last pushed / next )• Block structured languages contain link to lexically enclosing frame• Compilers normally keep scalar variables in registers, not memory!
High Mem
Low Mem
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0 zero constant 0
1 at reserved for assembler
2 v0 expression evaluation &
3 v1 function results
4 a0 arguments
5 a1
6 a2
7 a3
8 t0 temporary: caller saves
. . . (callee can clobber)
15 t7
MIPS: Software conventions for Registers
16 s0 callee saves
. . . (caller can clobber)
23 s7
24 t8 temporary (cont’d)
25 t9
26 k0 reserved for OS kernel
27 k1
28 gp Pointer to global area
29 sp Stack pointer
30 fp frame pointer
31 ra Return Address (HW)
Plus a 3-deep stack of mode bits.
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MIPS / GCC Calling ConventionsFPSPfact:
addiu $sp, $sp, -32sw $ra, 20($sp)sw $fp, 16($sp)addiu $fp, $sp, 32
. . .sw $a0, 0($fp)
...lw $31, 20($sp)lw $fp, 16($sp)addiu $sp, $sp, 32jr $31
raold FP
raold FP
ra
FPSPra
FPSP
lowaddress
First four arguments passed in registers.
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To summarize:MIPS operands
Name Example Comments$s0-$s7, $t0-$t9, $zero, Fast locations for data. In MIPS, data must be in registers to perform
32 registers $a0-$a3, $v0-$v1, $gp, arithmetic. MIPS register $zero always equals 0. Register $at is $fp, $sp, $ra, $at reserved for the assembler to handle large constants.
Memory[0], Accessed only by data transfer instructions. MIPS uses byte addresses, so
230 memory Memory[4], ..., sequential words differ by 4. Memory holds data structures, such as arrays,words Memory[4294967292] and spilled registers, such as those saved on procedure calls.
MIPS assembly languageCategory Instruction Example Meaning Comments
add add $s1, $s2, $s3 $s1 = $s2 + $s3 Three operands; data in registers
Arithmetic subtract sub $s1, $s2, $s3 $s1 = $s2 - $s3 Three operands; data in registers
add immediate addi $s1, $s2, 100 $s1 = $s2 + 100 Used to add constantsload word lw $s1, 100($s2) $s1 = Memory[$s2 + 100] Word from memory to registerstore word sw $s1, 100($s2) Memory[$s2 + 100] = $s1 Word from register to memory
Data transfer load byte lb $s1, 100($s2) $s1 = Memory[$s2 + 100] Byte from memory to registerstore byte sb $s1, 100($s2) Memory[$s2 + 100] = $s1 Byte from register to memoryload upper immediate lui $s1, 100 $s1 = 100 * 216 Loads constant in upper 16 bits
branch on equal beq $s1, $s2, 25 if ($s1 == $s2) go to PC + 4 + 100
Equal test; PC-relative branch
Conditional
branch on not equal bne $s1, $s2, 25 if ($s1 != $s2) go to PC + 4 + 100
Not equal test; PC-relative
branch set on less than slt $s1, $s2, $s3 if ($s2 < $s3) $s1 = 1; else $s1 = 0
Compare less than; for beq, bne
set less than immediate
slti $s1, $s2, 100 if ($s2 < 100) $s1 = 1; else $s1 = 0
Compare less than constant
jump j 2500 go to 10000 Jump to target addressUncondi- jump register jr $ra go to $ra For switch, procedure returntional jump jump and link jal 2500 $ra = PC + 4; go to 10000 For procedure call
371998 Morgan Kaufmann Publishers and UCB
Byte Halfword Word
Registers
Memory
Memory
Word
Memory
Word
Register
Register
1. Immediate addressing
2. Register addressing
3. Base addressing
4. PC-relative addressing
5. Pseudodirect addressing
op rs rt
op rs rt
op rs rt
op
op
rs rt
Address
Address
Address
rd . . . funct
Immediate
PC
PC
+
+
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• Things we are not going to coversupport for procedureslinkers, loaders, memory layoutstacks, frames, recursionmanipulating strings and pointersinterrupts and exceptionssystem calls and conventions
• Some of these we'll talk about later• We've focused on architectural issues
– basics of MIPS assembly language and machine code– we’ll build a processor to execute these instructions.
Other Issues
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• Design alternative:– provide more powerful operations– goal is to reduce number of instructions executed– danger is a slower cycle time and/or a higher CPI
• Sometimes referred to as “RISC vs. CISC”– virtually all new instruction sets since 1982 have been RISC– VAX: minimize code size, make assembly language easy
instructions from 1 to 54 bytes long!
• We’ll look at PowerPC and 80x86
Alternative Architectures
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PowerPC
• Indexed addressing– example: lw $t1,$a0+$s3 #$t1=Memory[$a0+$s3]– What do we have to do in MIPS?
• Update addressing– update a register as part of load (for marching through arrays)– example: lwu $t0,4($s3) #$t0=Memory[$s3+4];$s3=$s3+4– What do we have to do in MIPS?
• Others:– load multiple/store multiple– a special counter register “bc Loop”
decrement counter, if not 0 goto loop
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80x86
• 1978: The Intel 8086 is announced (16 bit architecture)• 1980: The 8087 floating point coprocessor is added• 1982: The 80286 increases address space to 24 bits, +instructions• 1985: The 80386 extends to 32 bits, new addressing modes• 1989-1995: The 80486, Pentium, Pentium Pro add a few instructions
(mostly designed for higher performance)• 1997: MMX is added
“This history illustrates the impact of the “golden handcuffs” of compatibility
“adding new features as someone might add clothing to a packed bag”
“an architecture that is difficult to explain and impossible to love”
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A dominant architecture: 80x86
• See your textbook for a more detailed description• Complexity:
– Instructions from 1 to 17 bytes long– one operand must act as both a source and destination– one operand can come from memory– complex addressing modes
e.g., “base or scaled index with 8 or 32 bit displacement”• Saving grace:
– the most frequently used instructions are not too difficult to build– compilers avoid the portions of the architecture that are slow
“what the 80x86 lacks in style is made up in quantity, making it beautiful from the right perspective”
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• Instruction complexity is only one variable– lower instruction count vs. higher CPI / lower clock rate
• Design Principles:– simplicity favors regularity– smaller is faster– good design demands compromise– make the common case fast
• Instruction set architecture– a very important abstraction indeed!
Summary