Redesign control FSM of a multicycle MIPS processor with low power state encoding.
378 - MIPS instruction encoding
description
Transcript of 378 - MIPS instruction encoding
378 - MIPS instruction encoding
From symbols to bits
A simple architecture
Instruction encoding
• Instructions, like registers and words of data, are 32 bits long
• Arithmetic Instruction Format (R format):add $t0, $s1, $s2
R format
op rs rt rd shamt funct
op 6-bits opcode that specifies the operation
rs 5-bits register file address of the first source operand
rt 5-bits register file address of the second source operand
rd 5-bits register file address of the result’s destination
shamt 5-bits shift amount (for shift instructions)
funct 6-bits function code augmenting the opcode
• Load/Store Instruction Format (I format):lw $t0, 24($s2)
Machine Language - Load Instruction
op rs rt 16 bit offset
Memory
data word address (hex)0x000000000x000000040x000000080x0000000c
0xf f f f f f f f
$s2 0x12004094
2410 + $s2 =
. . . 0001 1000+ . . . 1001 0100 . . . 1010 1100 = 0x120040ac
0x120040ac $t0
• MIPS conditional branch instructions:bne $s0, $s1, Lbl #go to Lbl if $s0$s1 beq $s0, $s1, Lbl #go to Lbl if $s0=$s1– Ex: if (i==j) h = i + j;bne $s0, $s1, Lbl1add $s3, $s0, $s1Lbl1:...
• Instruction Format (I format):op rs rt 16 bit offset
• How is the branch destination address specified?
Lab 1: Due April 24thCheck point April 17th
378: port yourStrcpy
378-HW: portStrcpy ANDMake a lightBlink in “slowly”
QuickTime™ and aTIFF (Uncompressed) decompressor
are needed to see this picture.
What is an FPGA?
QuickTime™ and aTIFF (Uncompressed) decompressor
are needed to see this picture.
QuickTime™ and aTIFF (Uncompressed) decompressor
are needed to see this picture.
What can you do with an FPGA?
• Emulate most circuits with about a factor of 10X slow down to full custom (that’s still 100mhz!)
• Largest FPGAs can hold ~ 8M gates. Pentium = 5M, Pentium4 = 44M
What can’t you do with FPGAs
• Content addressable memories• Memories with more than 1 write port.• Somethings are do-able, but large:
– arbitrary barrel shifters– Dividers / multipliers– Floating point (see shifters)
Tool flow
378:•Turn-in: Design, Waveforms, functional simulation output
378-HW:•Turn-in: Design, Waveforms, functional simulation output
Active HDL
Symplicty ISE tools Impact
XUP board
Active HDL
Verilog -> netlist Netlist -> FPGA
downloader
Demonstrate it working