September 14, 2019 Sam Siewert

CEC 320 and 322Microprocessor Systems

Class and Lab

Lecture 4 - Hardware Design Concurrent with Firmware and

Software

Lab #3 DemoCheck proper wiring of +3.3V, GND, and PD5, PD6, PD7 - Power to GND short on bread-board is the main risk, so have this checked by a TA or instructor prior to powering

PD5, PD6, PD7 input is Potentiometer wiper

Jumper on breadboard to power rail and GND

Shown direct connect to +3.3V and GND here (multiple on board) - rather than using bread-board

OPTIONAL: Analog discovery could be used to probe the signal output of the POT using Oscilloscope or Voltage level logging feature in Waveforms

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https://en.wikipedia.org/wiki/Potentiometer

Industry View - Full StackHardware, Firmware, Software - EE, CE, SELayers of Abstraction - System View

Sam Siewert Layers of Abstraction adapted from B. Davis 3

Hardware

Firmware(BSP, drivers, HAL (PDL))

System Software(CE Main+ISR, or OS, or

RTOS)

Application Software(e.g. UI, Services, Monitors)

Problems

Language

Instruction Set Architecture

Microarchitecture

Circuits

Devices

Algorithms

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Moore’s Law

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Out-of-class Viewing “Moore's Law and The Secret World Of Ones

And Zeroes”By : SciShow https://youtu.be/1qQE5Xwe7fs Good background material Overly Dramatic Somewhat dated : 32 nM, 12-Jul-2014 Fair game on exams – questions in Lecture

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Design ExamplesSoftware/Systems Continued

Hardware - HDLs (Verilog, VHDL)

Software (Systems) - SA/SD and UML, Block Diagrams– Block Diagram - useful to all engineers!– Goals and Objectives => Requirements, Constraints, Qualities– Know - SA/SD Flowchart, Dataflow Diagram, State Machine (Mealy)– Know - UML Structure vs. Behavior Diagrams

Structure - Class Diagram (Name, relation to other classes [association, hierarchy, aggregation, composition], attributes, methods)Behavior - OIM Sequence Diagram (how Objects or Classes Talk), and State Machine (extended)

– IDE for Software Implementation and Debug (e.g. IAR Tools)

Systems - SysML, SystemC, SystemVerilog, etc.– Beyond Scope of this Course– Useful for Hardware and Software Co-Design

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Design ExamplesHardware Introduction

Hardware - HDLs (Verilog, VHDL)– EDA - Electronic Design Automation– VHDL - VHSIC Hardware Design Language (Very High Speed

IC), a very structured HDL– Verilog - Alternative to VHDL (more like C)– PCB / PCA - Schematic Capture, Layout, Gerber file,

Fabrication, Test (https://youtu.be/ljOoGyCso8s )

Software (Systems) - SA/SD and UML, Block Diagrams

Systems - SysML, SystemC, SystemVerilog, etc.– Beyond Scope of this Course– Useful for Hardware and Software Co-Design

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Quick Look at TIVA Hardware and LabTIVA TM4C123G Dev Board - TIVA TM4C123G DEV BOARD (used in lab), TM4C123GXL Launch Pad– Coretex M4 MCU, ARM v7te ISA– USB to JTAG bridge and monitor (for debug, download, serial)– OLED color display– Buttons, GPIO, Multi-function I/O pins (ADC, DAC, I2C, etc.)– CAN, Micro-SD, USB-OTG

IDE - Latest EWARM for ARM (older on T drive or Canvas), IAR 7.70 Kickstart (code size limited)

Test Equipment - Analog Discovery, Waveforms

IoT Boards - IoT Enabled TM4C129X Connected Development Kit , TM4C1294XL Connected Launch Pad

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TM4C123 : Block Diagrams

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TM4C123 Device Interfaces

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Manufacturing• Global Foundries

https://youtu.be/UvluuAIiA50 Foundry consortium; originally (2009) AMD’s Fab assets

later merged with others fabs notably IBM in 2015. Will fab for “any” customer, notably AMD, STMicro,

Qualcomm, etc. TSMC, Samsung, IBM, Intel, Micron, etc. Full List of Fabs - here

• Intel https://youtu.be/Q5paWn7bFg4 Familiar company first micro -> current Top-to-bottom company, fab & IP design

• Other : “Sand to Silicon” (https://youtu.be/UvluuAIiA50 ) 40+ YouTube of various lengths &focus.

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Samsung 7nm Fab

Intel - Chandler AZ Fab-42

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Traditional VLSI Design Flow• Specification

what the system (or component) is supposed to do

• Architecture high-level design of component

state defined logic partitioned into major blocks

• Logic gates, flip-flops, and the connections

between them

• Circuit transistor circuits to realize logic

elements

• Device behavior of individual circuit elements

• Layout geometry used to define and connect

circuit elements

• Process steps used to define circuit elements

High Level Synthesis

GDSII

Synthesis

Placement

Routing

Extraction and Timing

Verification

Manufacturing

Architecture Design

Verification

RTL

http://vlsicad.ucsd.edu/courses/ece260b-w05/slides/ece260b-w05-intro-flow.ppt

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Don’t confuse with Compiler architectureIndependent RTL from which ASM is generated

Summary of Chip Design and TestPre-Silicon

– Specification - Goals, objectives => Requirements, constraints, qualities– Architecture - Block design, interfaces, function, sizing, state machines– Logic - Simulate with Cycle Approximate, Cycle Accurate– Test with Quick-turn FPGA (one step closer to ASIC) - Logic Verification

Fabrication Engineering (Depends on device type - standard cell, custom)– Circuit, Device, Layout, Process– Rev-A run

Post-Silicon– ASIC put down on PCB with PCA for verification (out of form factor for debug)– Signal integrity, Logic analysis, Firmware diagnostics, PCB cut-and-jumper– Report to Pre-Si and Fabrication Engineering– FIB (Focused Ion Beam) and Metal layer changes– Rev-B design if necessary

Firmware Development (Concurrent with PCB and ASIC design starting with Pre-Si)– Required for Post-Si quick turn-around– Required to ship unless chip has no firmware (not common today)– HW emulation

Host Drivers (concurrent with Firmware Development)– If chip is a chip-set rather than MCU, provide drivers for host– Provide drivers and HAL for MCU for evaluation– Device emulation

Delivery to OEMs (e.g. HP, Microsoft, Apple, etc.) or as Engineering Evaluation Sam Siewert 13

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Outline• HDL role• EDA tools• Types of Digital Circuit Design• PLD devices

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Hardware Description Language• Basic idea is a programming language to describe hardware

Different than programming languages (procedural, algorithmic) Emphasis on concurrent (parallel) vs. sequential execution Goal to close timing on logic designs (combinational and clocked state machines)

• Initial purpose was to allow abstract design and simulation Design could be verified then implemented in hardware

• Now Synthesis tools allow direct implementation from HDL Large improvement in designer productivity Manual IC Tape-out no longer done, but term is still used Automated Synthesis, Place and Route to produce GDSII

• Emerging Hybrid “Kernel” Languages (e.g. OpenCL) Compilation followed by Synthesis for FPGA Heterogenous Architectures (GP-GPU, DSP, or FPGA SoCs)

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The tapeout is specifically the point at which the graphic for the photomask of the circuit is sent to the fabrication facility.[1] … Historically, the term references the early days of printed circuit design, when the enlarged (for higher precision) "artwork" for the photomask was manually "taped out" using black line tape (commonly Bishop Graphics crepe). - Wikipedia

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VHDL – quick & dirty• VHDL - (VHSIC hardware description language)

VHSIC – Very High Speed Integrated Circuit• One of two HDL’s which maintain market share• VHDL & Verilog

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In 1983, VHDL was originally developed at the behest of the U.S Department of Defense in order to document the behavior of the ASICs that supplier companies were including in equipment. The standard MIL-STD-454N [2]

in Requirement 64 in section 4.5.1 "ASIC documentation in VHDL" explicitly requires documentation of "Microelectronic Devices" in VHDL.

Verilog was one of the first popular hardware description languages to be invented. It was created by Prabhu Goel, Phil Moorby and Chi-Lai Huang and Douglas Warmke between late 1983 and early 1984.[3] Cadence now has full proprietary rights to Gateway's Verilog and the Verilog-XL, the HDL-simulator that would become the de facto standard (of Verilog logic simulators) for the next decade. Originally, Verilog was only intended to describe and allow simulation. The automated synthesis of subsets of the language to physically realizable structures (gates etc.) was developed after the language had achieved widespread usage.

Verilog is a portmanteau of the words "verification" and "logic".[5] - Wikipedia

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VHDL VerilogGovernment Developed(Originally to document ASIC design)

Commercially Developed (Primarily as a Test-bench)

Ada based (verbose) C based (simple)

Strongly Type Cast Mildly Type Cast

Difficult to learn (easier to read?) Easier to Learn (harder to master?)

More Powerful Less Powerful?

VHDL vs. Verilog

Depends on design, logic device and opinion - e.g. here’s one

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VHDL Brief History• Very High Speed Integrated Circuit (VHSIC) Program

Launched in 1980 by DARPA Goal was to achieve significant gains in VLSI technology Need for common descriptive language

• July 1983 Intermetrics, IBM and Texas Instruments were awarded a contract to develop VHDL

• August 1985 Release of final version of the language under government contract, VHDL Version 7.2

• December 1987 IEEE Standard 1076-1987

• 1988 VHDL became an ANSI standard

• Between 1988 & 2008 Multiple revisions of IEEE 1076 released (1076-2000,1076-2002, etc…)

• January 2009 IEEE VHDL standard 1076-2008 released

• VHDL Has Been Accepted As a Draft International Standard by the IEC

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Outline• HDL role• EDA tools• Types of Digital Circuit Design• PLD devices

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EDA Tools• a VHDL simulator is just one tool in a typical

suite of design tools used in the design, simulation, verification, timing analysis, layout and fabrication of ICs

• Other Layout Synthesis Analog simulation Functional verification Mask preparation

• A commercial suite will have all of these in a package integrated to work together

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EDA Vendor Tools

• Not a exhaustive list – approximately 200617-Sep-19 /erau/cec320/s19/btd

Tools Cadence Synopsys MagmaSynthesis RTL Compiler (from Get2Chip) Design Compiler Blast RTLSVP/ floor planning First Encounter (from SPC) Jupiter XT/ Floorplan Compiler Blas Create, Blast Plan

Placement First Encounter (from SPC) Physical Compiler Blast Create, Blast Plan, Blast Fusion

Physical synthesis PKS (Get2Chip engine not yet integrated) Physical Compiler Blast Create, Blast Plan Routing Nanoroute (from Cadmos) Astro Blast FusionSignal Integrity CeltIC (from Cadmos) Galaxy S1 Blast Noise

Power analysisVoltageStorm (from Simplex); flow integration now, memory mid-2004 PrimePower Blast Rail

3-D RC extractionFire+Ice QXC (from Simplex); flow from integration now, memory mid-2004 Star-RCXT Blast Fusion

Static timingAmbit's CTE timing engine (not sold as

separate product) PrimeTime Blast Create, Blast Plan, Blast FusionLV5/DRC Assura Hercules Blast FusionChip finishing Virtuoso Chip Editor Astro/Columbia Blast FusionSource: EE Times

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VHDL Simulators (subset)• DirectVHDL-PE

Previously used in CEC220 – included with (prior) CEC220 text• Cypress Warp 6.2 Galaxy

Previously used in CEC320 – site license for ERAU• Altera Quartus

Integrated suite including VHDL Simulator that I am the most familiar with

• Xilinx Vivado Design Suite Another integrated suite targeted at FPGA Used in some CEC222 labs

• GHDL Open source VHDL simulator http://ghdl.free.fr/

• Cadence• Mentor Graphics

Commercial grade integrated suite(s) with VHDL

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VHDL Description• VHDL can be used to

describe an arbitrary digital circuit.

• Use of HDL eliminates all ambiguity in specification

• Facilitates simulation & synthesis

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VHDL Simulation• Simulation can be used to verify circuit

operation

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• Two primary types of simulation

• Functional (a) on

right• Timing

(b) on right

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VHDL Synthesis• After simulation, Synthesis can be used to

map the high-level circuit onto devices• Devices may be transistors (as shown) or

PLD – programmable routing and macro-cells

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Outline• HDL role• EDA tools• Types of Digital Circuit Design• PLD devices

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Circuit Implementation Choices• Implementation options

Discrete Devices PLD (Gate Array) PAL CPLD FPGA Standard Cell Full Custom

• More or less from slowest to fastest

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CPLDFPGA

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Comparison of Design StylesFull-

CustomStandard

Cell Gate Array FPGA

Area compact compact to moderate moderate large

Performance highhigh

to moderatemoderate low

Design cost high medium medium low

Time-to-market long medium medium short

www.ece.utexas.edu/~dpan/2005Fall_EE382V/notes/lecture25_fpga-conclude.ppt

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Comparison of Design StylesFull-Custom Standard Cell Gate Array FPGA

Cell size variable fixed height fixed fixed

Cell type variable variable fixed programmable

Cell placement variable in row fixed fixed

Interconnections variable variable variable programmable

Fabrication layers all layersall

layersrouting

layers only no layers

www.ece.utexas.edu/~dpan/2005Fall_EE382V/notes/lecture25_fpga-conclude.ppt

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Cost tradeoff

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Volume

Nonrecurring engineering costPLDASIC

• PLD Venn Diagram• Choice dependent upon many

parameters• Values given are hypothetical

Cost / Unit

NRE NRE Per-Unit Volume Sold

DesignMasks & Processing /

Test Setup 10 1000 1.00E+06 1.00E+08

Reprogrammable (FPGA) $100,000 $ - $80.00

Standard Cell $120,000 $500,000 $8.40

Custom ASIC $1,000,000 $500,000 $8.00

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Circuit Implementation Choices• No single Choice is the best

Next Intel Processor Full Custom

System-on-a-chip ASIC Standard Cell (or larger MACROs) Cells may be custom designed Only those cells required

Limited Volume Product/Prototype FPGA / Gate Array

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VLSI Layout• One of the steps in building an

ASIC is generation of VLSI layout• The masks are produced from the

VLSI layout• Left – inverter• Right – D flip-flop

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First Microprocessor Intel 4004, 1971

• 4-bit accumulator architecture

• 8µm pMOS• 2,300 transistors• 3 x 4 mm2

• 750kHz clock• 8-16 cycles/inst.• Designed using

MANUAL layout

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Die-Shot & Cross-Section• XPF 7400 Series Processor• 64 bit architecture

256 or larger SSE registers

• 6 core Processor• 1.9 billion transistors• 16 MB L3 cache• ~3 GHz clock speed

Cross section:

cores

cache

cores

cores

system interface

cach

e

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Sub 10 nanometer and Multi-layer PCBs

VLSI < 20 nm requires 3D process

TSMC - Fin FET (< 14 nm)

Intel - Tri-Gate (< 22 nm)

Multi-layer PCBs (e.g. 4 layer)– Top layer– Ground pour– Power pour– Bottom layer– Vias (vertical connect)– through-holes– Silk screen

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2011

The FinFET devices have significantly faster switching times and higher current density than the previous CMOS technology. FinFET is a type of non-planar transistor, or "3D" transistor.[1] It is the basis for modern nanoelectronic semiconductor device fabrication. Microchips utilizing FinFET gates first became commercialized in the first half of the 2010s, and became the dominant gate design at 14 nm, 10 nm and 7 nmprocess nodes.