CDP ECE 291 -- Spring 2000 ECE 291 Spring 2000 Lecture 16: Interrupts and Real-time Scheduling...

CDP ECE 291 -- Spring 2000

ECE 291

Spring 2000

Lecture 16:

Interrupts and Real-time Scheduling

Constantine D. Polychronopoulos

Professor, ECE

Office: 463 CSRL


String Instructions

• Very useful in graphics or in general for applying same operation on a region of locations in memory.

• Typical string ops copy from one range to another and filling a range of memory locations with specified values;

• EXAMPLE of string ops:

– rep movsd ; copy one DWORD from one string to another

– rep stosd ; set the DWORD to the value in EAX

– (last “d” is for doubleword - replace for B, W)


Plan your string operations clearly:

Always make sure you define the following 5 steps:

1 -Set source segment and offset

2 - Set the destination segment and offset

3 - Specify direction of processing (default is forward)

4 - Specify the number of units to apply each op (B, W, D)

5 - Specify the operation


Example:

1 -Set source segment and offset: use DS to point to sourcemov AX, SEG ScratchSeg ; from a defined segmentmov DS, AX

2 - Set ES to the destination segmentmov AX, 0A000h ; graphics segmentmov ES, AX

3 - Specify direction of processingcld ; set direction flag forward

4 - Specify the source offsetmov ESI, offset ScratchSeg ; set source offset

5- Specify the destination offsetmov EDI, 0 ; set destination offset

Specify # of times to repeat opetationmov ECX, 16000

Specify the operationrep movsd


More on Interrupts

• Each external device (disk, mouse, keyboard, sensor, etc) can generate an interrupt to the processor (attention-for-action request). Each such device usually contains a 1-bit “arm” register which can be set by the software if interrupts from that device are to be accepted.

• The processor can enable/disable interrupts by setting/clearing the I bit in the Flags or the CCR (condition code register). I=0 enables all armed interrupts and I=1 disables all interrupts.

• A good design should provide for extensibility in the number or devices that can issue interrupts as well as in the number/type of interrupt service routines (ISR).


Interrupts

• To process an interrupt the system does the following: – Execution of current routine is suspended and context is saved

onto the stack– The corresponding ISR is executed– Once ISR completes it restores the suspended routine from its

stack and execution resumes

• Two types of interrupts:

– Polled interrupts: All external devices share a common interrupt request line. All interrupts invoke a central (common) ISR which probes devices to determine which/what and calls appropriate ISR.

– Vectored interrupts: each device has its own interrupt line. Each interrupt request is processed directly by its corresponding ISR. This is faster but less scalable and more costly.


Interrupts: 2 Approaches

ArmRequest External

Device

ArmRequest External

Device

ArmRequest External

DeviceI Request

Microprocessor

ArmStatus External

Device

ArmStatus External

Device

ArmStatus External

DeviceI

Request3

Request2

Request1

Microprocessor

POLLED Interrupts:

VECTORED Interrupts:


Polling

• Polling is DIFFERENT from polled interrupts: Polling usually involves busy-waiting (gadfly) and RR checking for events at various devices. It can be done periodically at set intervals or through busy-waiting in very simple, dedicated tasks/environments.

• Polling is best suited for dedicated controllers, data acquisition systems with periodicity, and other simple scenarios.

• Interrupts are necessary in real-time environments where events are asynchronous and unpredictable, or when an event must be processed within a deadline or is lost.


DMA• DMA is used when low latency and/or high bandwidth is

required (e.g., disk I/O, video output, copying memory blocks, or low-latency data transfers in data acquisition, etc).

• Software DMA:

– Starts with a normal interrupt. Then the ISR for DMA sets up the device registers and initiates the I/O. The processor returns to what it was doing, and upon completion of I/O the device notifies processor about event done.

• Hardware DMA:

– All above done in hardware only

• Input device: DMA is triggered on NEW DATA AVAILABLE

• Output device: DMA is triggered on OUTPUT DEVICE IDLE

• Periodic events (e.g. signal generation): DMA is triggered by periodic timer.


Burst DMA

• If we put buffers in the I/O devices, then bulk data transfers are possible from the device buffers to/from memory: this is called burst DMA.

• Disk is an example of burst DMA

• Low-latency asynchronous I/O cannot use burst DMA since data need to be processed as soon as it arrives.


Reentrant Code

• A function/subroutine is reentrant if it can be simultaneously executed by two or more processes/threads.

• The above suggests that reentrant code can NOT use global variables, otherwise different threads may update the same mem. location in non-deterministic order.

• Solution:

– Use local variables (registers or stack) for parameter passing wherever possible.

– Use mutual exclusion for accessing global structures as Queues.

– Disable interrupts when executing in mutual exclusion regions

– Check for deadlocks and livelocks


Real-time Scheduling

• Interrupts are heavily used in scheduling real-time events when the processing of a hardware/software event must be done within a specified period of time.

– Example: scheduling execution of background processes with keyboard input (without interrupting the current process and handling keyboard I/O, key strokes can be lost, even if buffered on a small buffer.)

• Events=threads=tasks=processes: Real-time scheduling requires the notion of:

– event priority, deadline, blocking/restoring threads, interrupt nesting



• In general, the problem of scheduling with hard deadlines is NP-Hard, i.e., there are no simple optimal algorithms.

• Practical solutions involve simple, fast, near-optimal heuristics that work in practice.

• Most of these heuristics are “greedy”: they schedule the highest priority thread until another, yet higher priority thread arrives or the main thread completes.

• In general: GOAL is to be able to guarantee execution of critical threads (events) within a deadline regardless of what else is happening in the system. This is possible only under certain conditions (e.g., it’s impossible if the number of critical threads is unbounded).



• Optimal greedy algorithm ONLY for the following instance of the problem:

• Scheduling of unit-time threads (tasks) with deadlines and penalties on a single processor

• Assume:

– S = {1,2,3, …, n} is a set n of unit-time tasks

– A set of n integer deadlines {d1, d2, d3, …, dn}, such that 1<=di<=n and task i is supposed to finish by di.

– A set of n nonnegative weights or penalties {w1, w2, w3, …, wn} such that penalty wi is incurred only if task i does not complete by time di, and no penalty is incurred if a task is finished by its deadline.

• PRO BLEM: Find a schedule for S that minimizes the total penalty incurred by missed deadlines!


Scheduling

• A task is late if it finishes after its deadline, otherwise its early

• Observation 1: Any arbitrary schedule can be put into early-first form in which the early tasks precede the late ones: If some early task E follows some late task L, then we can switch L and E without affecting E being early and L being late!!

• Observation 2: Observation 1 suggests that any schedule can be put into a canonical form in which all early tasks precede all late tasks, and the early tasks are in order of nondecreasing deadlines.

This can be done by putting the schedule into early-first form. Then, as long as there are two tasks i, j finishing at times k and k+1 and such that dj < di, we can swap the positions of i and j without affecting either of them.

This is because since task j is early before the swap, k+1 < dj.

Since dj < di => k+1 <di and therefore task i is still early after the swap.


Algorithmic Steps

• Now the search for an optimal schedule reduces to finding a set A of tasks that are to be early in the optimal schedule. Once A is computed we create an actual schedule by determining a canonical order (i.e., listing the elements of A in nondecreasing deadline, then listing the late tasks (S-A) in any order).

• A set of tasks A is independent, if there exists a schedule of its tasks such that no tasks are late. Clearly, the set of early tasks in any schedule form an independent set of tasks.

• Let I denote the set of all independent sets of tasks.


Algorithmic Steps• Consider the problem of determining if a given set of tasks A is

independent. For t=1, 2,…, n let Nt(A) denote the number of tasks in A whose deadlines is t or earlier.

• Lemma: For any set of tasks A the following statements are equivalent:

1 - The set A is independent

2 - For t=1,2,…,n, we have Nt(A) <= t.

3 - If tasks in A are scheduled in order of nondecreasing deadlines, then no task is late!

Using property 2 we can easily determine if any A is independent!

Minimizing the sum of penalties of late tasks is = to maximizing the sum of penalties of early tasks

The following algorithm computer (optimal) A with max sum of penalties.


Greedy [Optimal] Algorithm

Algorithm RT-Schedule (S, I, w)

A <- 0

Sort S into nonincreasing order by weight w

for each x S, taken in nonincreasing order by weight wx

do if A {x} I

then A <- A {x}

return A


Example:

Task 1 2 3 4 5 6 7

di 4 2 4 3 1 4 6

wi 70 60 50 40 30 20 10

- The algorithm selects tasks 1, 2, 3, and 4- Rejects tasks 5 and 6- Accepts task 7

Final Optimal schedule: <2, 4, 1, 3, 7, 5, 6>


Dynamic Scheduling

• In reality we use near-optimal greedy heuristics in combination with priority-based interrupts in order to meet tasks around deadlines.

• Preemption is used to switch from one task to a higher priority task in order to meet the most crucial deadlines.

CDP ECE 291 -- Spring 2000 ECE 291 Spring 2000 Lecture 16: Interrupts and Real-time Scheduling...

Documents

Transcript of CDP ECE 291 -- Spring 2000 ECE 291 Spring 2000 Lecture 16: Interrupts and Real-time Scheduling...