C++ to RTL EE 382V - SoC Design Spring '08 Prof. Mark McDermott Sriram Sambamurthy Ramtilak Vemu...
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Transcript of C++ to RTL EE 382V - SoC Design Spring '08 Prof. Mark McDermott Sriram Sambamurthy Ramtilak Vemu...
C++ to RTL
EE 382V - SoC Design Spring '08Prof. Mark McDermott
Sriram SambamurthyRamtilak Vemu
University of Texas at Austin
2
Overview
• C++ to C– Input: Fixed-point DRM (from Lab1)– Output: Stand-alone C module (Lab2)
• C to threaded C (Lab2)– Output compiled using normal C compiler
• Threaded C to RTL (Lab3)– C2R compiler converts C to RTL– CebaTech (docs: user guide, cookbook)
3
C++ to C
• http://yenigul.net/tpop/handouts/CPP_to_C.htm
• Classes -> structures/ other data structures
• Memory management
• Type casting
• Declaration of variables
• Function prototyping
• Function overloading, OO concepts• http://www.icce.rug.nl/documents/cplusplus/
4
C to threaded C
• Threaded C – what is it?– Functions running in parallel (threads)– Threaded functions depict different clock
cycles of operation
• Why do we need to write this?– CebaTech C2R converts C to RTL
• Takes threaded C as input• Threaded C similar to SystemC
• There should be some notion of an FSM when writing threaded C
5
C to threaded C – skeleton example
main(){ fetch(); for every datum_width decode(); for every instruction read registers(); execute(); writeback();
}
• Five threads– FSM
• Data movement
– Each stage– State variables
• Every thread– While(1)– Sleep()– activation
6
C to threaded C – fibonacci
• Discuss with C2R user guide– Threaded C compiled using unix c
compiler• Points of interest
• Main function creates a thread• Passes values to “initiate” function
• wakes up the thread• while(1) – continuous execution• sleep() – denotes cycle boundaries?• Control FSM
7
Threaded C to C2R format C
• Why?– Need to attach specialized header files– Define specific width datatypes
• ... 8, 16, 32 ...– systasks
• Is the conversion trivial?– May look trivial, but its not– Fixing data types to actual width takes place
– need some range analysis– Setting up code in such a way that we get
what we expect to see in verilog simulation
8
Threaded C to C2R format C
• Discuss with c2r user guide
• Fibonacci example
• c2r header file
• data types – width
• c2r_process
• c2r_interface
• output: linked.v – must write top.v for providing clock and reset
9
DRM example
• Viterbi Decoder – stand alone module– Init( )– Decode( )
• Function to convert – decode( )• decode( ) has input/output arguments
– Arrays/ structures• FSM
– Get input arguments from DRM - Thread1• Store them for processing
– Decode the data• Butterfly - Thread2?• Traceback – Thread3?• Transfer of data back to DRM - Thread4?
10
Pipeline example
• SystemC to threaded C to RTL
• 4 stage pipeline
• stage1_addsub, stage2_multdiv, stage3_power, stage4_display
• Examples: multi-cycle, one-cycle
• Verilog code
• FSM logic for each function
• Next state logic for state variables
• Storage for state variables
11
Resources
• C2R user guide
• C2R environmental setup
• C2R cookbook
• Extra pipeline example – play with it– Connect pipe stages– Synthesis to RTL– Interface function– Dataflow between stages– Create one-clock pipelines, as by default
multi-clock dataflow will be the output
12
Thank You