C. Cattadori GERDA Phase II FE electronic- MiB 16th april 2010 GERDA Phase I: Status Carla...

C. Cattadori GERDA Phase II FE electronic- MiB 16th april 2010

GERDA Phase I: Status

Carla Cattadori, Alberto Pullia, Stefano Riboldi, Alessio D’Andragora, Francesca Zocca,

M. Barnabe-Heider, K. Gusev, D. Budjas

GERDA FE Phase II meeting

Milano Bicocca 16 april 2010


Outline

• GERDA Phase I specs• GERDA Phase I Detectors & Detector Assembly• The developed CSA based on semi-integrated

architecture (further integration see S. Riboldi talk)• Exp. Results for CSA based on

– CMOS ASIC PZ0– CMOS ASIC PZ1– Commercial CMOS OPAMP

• Radiopurity issues• Conclusion• Outlook and next steps


• Charge Sensitive Amplifier– Sensitivity: ~ 150 mV / MeV– Range Dynamic: > 5-6 MeV (now 8-9 MeV) – Working @ Criogenic T– Large Open loop gain (~ 105) to guarantee stability (but cryogenics helps)– Noise: <1 keV in Ge (< 150 e- r.m.s) @ 1 MeV, = 8 -10 s, at T= 77°K– Rise time: < 30 ns to allow PSD of ionization events in Ge detectors– Compact / integrated as possible– Drive 50 load through 6 m (later 10 m and then 20 m) long cables – Power dissipation: < 50 mW /ch (as low as possible)– Output stage: Better differential (later single ended)

• PCB requirements– 3ch modularity to serve 1 string– Radiopurity: as low as possible later set limit < 500 Bq 232Th and 2.5 mBq 238U

for distance– Interconnection with input detector and output/LV cables by pins– Cryogenic (stable vs deformations for thermal cycles etc.)

GERDA Phase I FE electronic:

Speca as in year 2005 (1st meeting at Milano Celoria Physic Department, and subsequent refinements)


GERDA Phase I detectors & detector assembly

• 8 enrGe + 6 natGe p-type coaxial Ge detector

• mass:1-3 kg

• Cdet = 30-50 pF

• Deployed in strings

• Mounted in low-mass Cu holders

• Cable from Detector to CSA Input & HV : Cu unshielded strip insulated in Teflon pipe

• HV contact: on Li surface by pressure

• Readout contact: in borehole spring-loaded


Phase I detectors

Drawing of phase I detector array:

•above:Non-enriched prototype detector assembly (p-type, 1.6 kg). Same performance as in a vacuum cryostat.

•IGEX and HDM crystals after dismounting from cryostat (prior to reprocessing at manufacturer)

•All Phase-I detectors reprocessed and mounted in a low-mass holder.


The chosen strategy

First rule to reduce significantly background is to minimize First rule to reduce significantly background is to minimize mass of each component close to crystals mass of each component close to crystals integrated integrated front end.front end.As a trade-off of noise, radioactivity and other specs a semi-integrated architecture was chosen and pursued: external JFET external JFET first stage followed by an ASIC second stage amplifier.first stage followed by an ASIC second stage amplifier.

• First stage FET: Philips BF862 as:

• Noise good

• Bandwidth good

• Can work at VGS =0

• FET can be replaced

@ cryo -T


BF862 characterization at room and cryo-T:gm drops ~ 2-3 at cryo-T

• Parallel white noise contribution substantially decreases at 77K as expected.

•The decreased temperature only partially compensates the effect of decreased transconductance

the overall series white noise is higher at 77 K than at room temperature.


CSA based on PZ0 (Pullia Zocca 0)

RD CF

BF862

Cdet

detector

Vout

G

new output stage (low impedance &

swinging to negative-rail)

RF 2.5 V

-3.5 V VD

discrete components

ASI C (CMOS 0.8um 5V)

12 V

+3V

-3V

VCC

Tested circuit structure: external BF862 JFET + 0.8m 5V CMOS

single-ended preamplifier

•ASIC CMOS circuit designed by A. Pullia in 2005•Produced by AMS foundry in 0.8 m 5V CZX CMOS technology•Single ended circuit•External feedback components

Closed loop gain A = gm x RD x G


Test chipTest chip

3.3

mm

3.3 mm

MOSFETs

resistors

MOSFETs

MOSFETs

MOSFETs

PREAMP 2pMOS + ext RF + int biasVmax = 550mV (50 Ohm)

PREAMP 1pMOS + ext RF + ext biasVmax = 550mV (50 Ohm)

PREAMP 1PREAMP 2

PREAMP 3pMOS + reset pMOS + shaper

PREAMP 3

PREAMP 4

PREAMP 4pMOS + ext RF + ext biasVmax = 2V (1 kOhm)HIGH VOLTAGE comp’s

TEST struct

TEST struct

CSP+OS simple CC=0pF

CSP+OS simple CC=0.2pF


CSP+OS simple CC=1pF


CSP+OS cplx CC=0pF

CSP+OS cplx CC=2pF

CSP+OS cplx CC=0.4pF

CSP+OS cplx CC=1.4pF

CSP+OS cplx CC=1pF

OPAMP OPAMP OPAMP OPAMP

CSP + OS simpleCSP with new rail-to-rail output stage. Various comp cap’s

CSP + OS cplxCSP with new rail-to-rail output stage. Various comp cap’s


Acquired output signal driving a 50 coaxial cable of ~ 10 m : rise time of ~ 15

ns

Comparison between noise measured at room

temperature (T=300°K) and in LN (T=77°K)

Working temperature

from -196°C to 55°C

(from 77 K to 328 K)

Negative output voltage swing on 150 impedance

~ 2.5 V (against a negative power supply of -2.7V)

Energy sensitivity

(CF = 0.2 pF)

~ 290 mV/MeV at preamp output

~ 217 mV/MeV after 150 termination

Input dynamic range

~ 8.6 MeV

Rise time~ 16 ns with ~ 10m

terminated coaxial cable

Fall time ~ 250 s ( RF = 1.2 G )

Open-loop gain ~ 3.5 *105

Loop gain ~ 600

Resolution at T= 77 K ( = 6s )

2.2 keV @ 1.332 MeV ( 60Co )

1.6 keV @ 932 keV pulser line

Power required at T=77K

23.4 mW

(VFET = +4V ID = 3mA

VCC= +3.6V VEE = -2.8V)


Spectroscopic performances of prototype PZ0 with prototype detectors @ Cryotemp T

Best resolution obtained with Best resolution obtained with (encapsulated) prototype crystal (encapsulated) prototype crystal and cold PZ0 CSAand cold PZ0 CSA

•With encapsulated SUB detector: R = 2.06 keV (best); 2.2 keV (typical) in LN (both CSA & Detector)

•With prototype naked detector in LAr in Gerda Underground Detector Lab: 2.6 keV @ 60Co

1ch CSA based on PZ0 ASIC (in ceramic carrier)


The 3ch CSA based on PZ0


Experimental Setup

HPGeLN

Ch1 Ch2 Ch3

3 Output Cables (50 terminated)

7 LVPS Cables (connected to the Power Supply Unit,

through a “filters box”)

1 Test Input Cable

• 11 cables used

• All cables 10/20 meters long

• Ch1 and Ch3 : 33 pF cap.

• Ch2 : Prototype HPGe detector

• Acquired data with both MCA and Flash ADCs (Caen)

JFET Power Supply = 3.7 v

LV Power Supply = ±3.1 V; - 2.0 V

Power Consumption ~ 40 mW 3 ch

Dynamic Range ~ 8 MeV on high imp.

GND GND


~ 40 cm from 1st detector (+15 cm 2nd, +15 cm 3rd)

CSA, Cu EM shield


Working Temperature

89 K

Rise Time SM 50 + RG 174

SM 50

Ch-1 (CDET=33 pF, on board )

74 ns 40 ns

Ch-2 (CDET=33 pF, short leg

~1 cm)

72 ns 41 ns

Ch_3 (DETECTOR) 73 ns 41 ns

Fall Time 250 s (RF = 1 G, CF = 0.3 pF)

Resolution Ch-1(CDET=33 pF, on board )

1.2 keV @ 1 MeV pulser line

Ch-2 (CDET=33 pF, short leg

~1 cm)

1.2 keV @ 1 MeV pulser line

Ch-3 (DETECTOR)

2.7 keV @ 1.332 MeV (60Co)2.3 keV @ 1 MeV pulser

line

Power Required (T=77K)

~ 40 mW (VFET = +3.7 V, ID = 3 mA; VCC= +3.1 V; VEE = -2 V)

RIN FADC removed


PZ0 open issuesPZ0 open issues

• Large number of physical components needed on PCB• Some mortality of CSA due to not fully optimized technology of ASIC

gluing on PCB and Cu cup sealing

• Some x-talk among channels (~1 %) going through LV ASIC VCC & VEE PS in relation to the 10 m long resistive Habia SM50 cables (10 for 10 m), and to PSRR of PZ0 circuit

• Removed ceramic carrier and ASIC bonded on board

• Defined technology for chip gluing

• Sealing of Cu cup to protect the ASIC and its bonding wires

• En res and x-talk among ASIC on same chip OK for high impedence load

PZ0 solved issuesPZ0 solved issues


PZ1 chip (PZ0 modified to drive 50 terminated cables at 77K)

Chip includes 3 versions of TRIPLE PZ1 and one TRIPLE PZ0 (as spare)

PZ1 prototype mounting (single channel, ceramic carrier, only for testing purpose)

Response of PZ1 at room T, Cdet=33pF, 12.5m cables and 50 ohm terminations. Transition time = 88ns.

Response of PZ1 at 77K, Cdet=33pF, 12.5m cables and 50 ohm terminations. Transition time = 21ns.

Chip area ~5 mm2



OK when removed

• Power supply of output buffer (VC, -VE) separated from first stage (VCC, -VEE)

• Bulk connection separated from power supply of output buffer

• Output buffer optimized

VCC, -VEE

VC, -VE

Two PS needed for 3 ch array:

1

2



• First tests* @ 300K and 77K of a single PZ1 very

promising

• No need of RC stabilizing network

• Able to drive 50 cable at 300K and 77K

• Noise ok (same as PZ0: ~1.1 keV @ 6us shaping time with

Cdet=33pF)

• Dynamic range ok (8MeV with CF=0.2pF, still to be tested with

0.3pF)

• Triple channel / cross-talk still to be measured

• Still to be tested with Ge detector

*tests performed in March 2010


PCBs

A high degree of radiopurity is required for the CSA, long R&D on physical components & PCBs materials to make a radiopure CSA.

• PCB material: Cuflon© (PTFE embedded in two Cu foils) for PCBs• Selected a company: PCB production process & electrogalvanic Ni/Au deposition (for ASIC bonding) qualified for radiopourity. •The ASIC is bonded directly on board and sealed by a radiopure Cu cup, providing both the EM shield and the protection of the bonding wires. • SMD Resistors and capacitors are of 0402 and 0603 size to reduce mass, and protection diodes have been added at the FET input (Philips BF862Philips BF862).• All the components (FET, C, R, Rf (high values), solder paste) screened and selected for radiopurity • Qualified the contacting pins.


Radioisotopes concentration in FE circuits

FE circuits: available at LNGS 3 x 3 ch PZ0 circuits (tested). Result of individual radioactivity measurement (reference value for B = 10-3 c/keV kg y):Th < 500 Bq/PCBU < 3 mBq/PCB

8 x 3-ch circuit in production

U-238/Ra-226 Th-232/Ra-228 Th-232/Th-228 K-40[mBq/PCB] [mBq/PCB] [mBq/PCB] [mBq/PCB]

0.54 +/- 0.08 0.24 +/- 0.09 0.29 +/- 0.08 3.2 +/-0.8

Pb-210:< 5.3 Bq/PCB

---------------------------------------------------------------------------------------------------------Pins for PCB to Habia Cable connection

U-238/Ra-226 Th-232/Ra-228 Th-232/Th-228 K-40[mBq/PCB] [mBq/PCB] [mBq/PCB] [mBq/PCB]<0.076 < 0,120 0,060+/- 0.02 0.4 +/- 0.2

---------------------------------------------------------------------------------------------------------


CSA Based on Commercial CMOS OPAMP Architecture: external JFET + CMOS OPAMP and Rf,Cf

Tested with encapsulated SUB detector along 3 weeks

In test in these days at LNGS GDL with naked BEGe detector

• PCB manufactured in FR4 material (2 layers)

• Same size as PZ0 for compatibility purpose (65 mm x 40 mm)


Experimental Setup

HPGeLN

Ch1 Ch2 Ch3

3 Output Cables (50 Ohm terminated)

3 LVPS Cables (directly to the Power Supply Unit,

no need for the “filters box” in between)

Test Input Cable

• 7 cables used

• All cables 10 meters long

• Ch1 and Ch3 : 33 pF cap.

• Ch2 : SUB HPGe detector

• Acquired data with both MCA and Flash ADCs (Caen)

JFET Power Supply = 6 - 12 V

LV Power Supply = ± 2.5 V

Power Consumption < 140 mW

Dynamic Range > 15 MeV

GND GND


Summary of CC2 measured characteristics

•Best energy resolution @ LNT : 0.7 kev FWHM (0 pF Cdet) 1.1 kev FWHM (33 pF Cdet) (with 1 Mev pulser signal, 12 us shaping time)

•Best energy resolution @ LNT : 1.96 kev FWHM for 22 Na (12 us shaping time, 5k counts acquisition)

• 15 MeV guaranteed energy dynamic range

• 50 drive capability with 10 m long cables

• Power consumption < 140 mW (down to 100 mW for 10 Mev dynamic range)

• Rise time : less then 55 ns with 50 Ohm terminated, long cables and energy up to 15 Mev

• Cross-talk : < 0.1%

• Power Supply Rejection Ratio : should allow HPGe spectroscopy within the Gerda setup

• Expected reduction on CSA radio-activity < 150 Bq for both 232Th & 238U

• Operated (in Milano) with 7 cables (3 for power supplies, 3 for outputs, 1 for input test)

• Small size, no bonding wires, no PCB copper shield, no LVPS “filters box”, simple and robust


CC2- PCB Redesigned

• Reduced PCB Size (38 mm x 50 mm)

• Mechanical Stability (4 distributed holes: M25) (no need for Teflon Layer in Copper Shield)

• Reduced Connector Pin Number (11 vs 14)

• Eliminated Feedback and Test Capacitors (implemented with PCB copper traces, after Alessio’s work)

• Various BOM configurations to trade-off between: Radiopurity and Channel Crosstalk

CSA BOM (as tested in Milano)

3 JFET3 Operational Amplifiers11 Tantalum Capacitors (LV decoupling)22 Resistors3 Discharge Protection Devices (JFET)

Less than 0.1% measured crosstalk

Redesigned CC2 PCB

First CC2 PCB(same size as PZ0)

Detector Input Contacts

Pin Connector

Minimum CSA BOM

3 JFET3 Operational Amplifiers3 Tantalum Capacitors (LV decoupling)13 Resistors3 Discharge Protection Devices (JFET)

Crosstalk ? ? ?


CC2-PCB Redesigned

Component layer Bottom layer

PCB capacitors

• Value of PCB copper traces capacitors (FR4 PCB) reproducible. (Cf=0.7 pF,Ct= 0.2pF) • a 3 ch CC2 CSA will be coupled to a naked BEGe detector in the next days•


ConclusionsConclusions

• 2 CSA available semi-integrated architecture: external JFET BF862 + CMOS ASIC PZ0-1 / Commercial OPAMP with adequate performances for GERDA specs (cryo-T).

• R&D to produce low radioactivity PCB and selected physical components to produce CSA with radionuclide concentrations << limit value for Phase I Background index (10-3 c/kg y keV); valid for both options.

• Implementation of printed Cu traces Capacitors instead of C physical components allow to produce a very low background CSA (expected <150 Bq for a 3 ch circuit) the CSA can be the CSA can be approached to detector stringapproached to detector string

possible to separate the Very FE (VFE= FET,Cf,Rf) to detectors to reduce Cu strip cable length i.e. reduce microphonism, pick-up etc.

• Very good solution for Phase II unsegmented detectors• Can be a solution for Phase II segmented detctors, but PCB needs

to be re-designed +………


Outlook and next steps


EXTRA slides


Radioactivity issues

• CC2 CSA expected to improve the radioactivity issues related to the FE electronics

• Radioactivity budget estimated on the base of already measured components is:

< 150 < 150 Bq / PCB (for both Th & Ra) pins includedBq / PCB (for both Th & Ra) pins included

as a result of:

- 3 BF862 JFET (228Th= 15 ± 4 Bq / PCB, 226Ra= 14 ± 4 Bq / PCB)

- 3 OpAmp (228Th < 11 Bq / PCB, 226Ra= 6.3 ± 1.2 Bq / PCB)

- 0 NP0 Ceramic Capacitor (for test and feed-back) replaced by PCB Capacitors - 0 NP0 Ceramic Capacitor (for test and feed-back) replaced by PCB Capacitors

- 11 max. (down to 3 min.) Tantalum Capacitors for LVPS decoupling (228Th= 88 ± 22 Bq / PCB , 226Ra= <33 Bq / PCB, 40K=770 ± 330 Bq / PCB)

- Cuflon for PCB (228Th <12 Bq / PCB , 226Ra <3 Bq / PCB, 40K =200 ± 62 Bq / PCB)

- 22 max. (down to 13 min.) resistors (3 for feed-back; 19 for polarization and LVPS decoupling) Only upper limit available, but from integral radioactivity of PZ0 are not dominant

- 7 (for signals) + 4 (for ground) PCB Pins for cable connection (228Th = 42 ±14 Bq / PCB , 226Ra= < 53 Bq / PCB, 40K= 280 ± 140 Bq / PCB) but research of better pins in progress


CSA Intrinsic Energy Resolution

2 4 6 8 10 120.5

1

1.5

2

2.5

3

3.5

Shaping Time [us]

Ene

rgy

Res

olut

ion

[kev

]

2 4 6 8 10 120.5

1

1.5

2

2.5

3

3.5

Shaping Time [us]

Ene

rgy

Res

olut

ion

[kev

]

Circle : 6 V JFET Power Supply Triangle : 12 V JFET Power Supply

Cdet = 33 pF

Room Temperature LN Temperature


CSA Rise Time

0 2 4 6 8 10 12 14 16 18 2035

40

45

50

55

60

Equivalent Input Energy [Mev]

10%

- 9

0% R

ise

Tim

e [n

s]

• Blue line: CSA + 10 m long output cables (50 Ohm terminated)

• Red line: CSA + 1 m long output cables (50 Ohm terminated)

• Pulser signal 5 ns rise time

• Rise time defined as time interval between 10% and 90% of CSA output signal


Spectroscopy with CC2 CSA

Irradiation with 22Na source.

FWHM = 2.15 kev

• Analog Amplifier (10 us Shaping Time)

• MCA

• Reproducible Energy Resolution (σ = 0.03 kev over 20 short measurements)


Spectroscopy with CC2 CSA

• Analog Amplifier (10 us Shaping Time)

• MCA

• Background long acquisition (over the night)

FWHM = 2.28 kev (40 K)

FWHM = 2.75 kev (232 Th)


Digital Spectroscopy with CC2 CSA

FWHM = 2.27 keV

• CAEN FADC

• Off-line processing

• Digital FIR filtering with symmetric weighting function for baseline

• CSA output signals with 700 us decaying time

(from 10% to 90%)

• Good agreement with single-pole exponentially decaying pulse model


Crosstalk between Channels

• Between Ch2 (detector) and Ch1

• Same procedure as for PZ0: Ch1 and Ch2 through analog shaper (10us) Gain amplification for Ch2 = 200 Gain amplification for Ch1 = 1000

• Experimental Result:

ΔCh1 / ΔCh2 = (15 mV / 5 V) / 5 = 0.06 %

• Very similar results for cross-talk measurement between Ch2 and Ch3

• Because cross-talk is low, it is also difficult to estimate because of the electronic noise

• As a conservative assumption :

Cross-talk < 0.1%

Inducing signal:Ch2

Inducted signal:Ch1

256 Scope Averages: Ch1


CSA Power Supply Rejection Ratio

• Important parameter to be evaluated (because of unavoidable LVPS variation across long and resistive cables)

• Low PSRR may cause: cross-talk between channels noise on output signals as a result of disturbances on LVPS

• In order to practically estimate the CSA PSRR: we measured the 22Na peak shift on the energy spectrum for ± 10% variation of each LVPS

Less than 1/4000 shift of the centroid of the peak (5k counts)

C. Cattadori GERDA Phase II FE electronic- MiB 16th april 2010 GERDA Phase I: Status Carla...

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